U.S. patent application number 11/307664 was filed with the patent office on 2006-06-08 for apparatus and method for small signal sensing in an sram cell utilizing pfet access devices.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to John E. Jr. Barth, George M. Braceras, Harold Pilo.
Application Number | 20060120144 11/307664 |
Document ID | / |
Family ID | 34986083 |
Filed Date | 2006-06-08 |
United States Patent
Application |
20060120144 |
Kind Code |
A1 |
Barth; John E. Jr. ; et
al. |
June 8, 2006 |
APPARATUS AND METHOD FOR SMALL SIGNAL SENSING IN AN SRAM CELL
UTILIZING PFET ACCESS DEVICES
Abstract
A method for small signal sensing during a read operation of a
static random access memory (SRAM) cell includes coupling a pair of
complementary sense amplifier data lines to a corresponding pair of
complementary bit lines associated with the SRAM cell, and setting
a sense amplifier so as to amplify a signal developed on the sense
amplifier data lines, wherein the bit line pair remains coupled to
the sense amplifier data lines at the time the sense amplifier is
set.
Inventors: |
Barth; John E. Jr.;
(Williston, VT) ; Braceras; George M.; (Essex
Junction, VT) ; Pilo; Harold; (Underhill,
VT) |
Correspondence
Address: |
CANTOR COLBURN LLP-IBM BURLINGTON
55 GRIFFIN ROAD SOUTH
BLOOMFIELD
CT
06002
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
|
Family ID: |
34986083 |
Appl. No.: |
11/307664 |
Filed: |
February 16, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10708713 |
Mar 19, 2004 |
|
|
|
11307664 |
Feb 16, 2006 |
|
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|
Current U.S.
Class: |
365/154 |
Current CPC
Class: |
G11C 11/412
20130101 |
Class at
Publication: |
365/154 |
International
Class: |
G11C 11/00 20060101
G11C011/00 |
Claims
1. A method for small signal sensing during a read operation of a
static random access memory (SRAM) cell, the method comprising:
coupling a pair of complementary sense amplifier data lines to a
corresponding pair of complementary bit lines associated with the
SRAM cell; setting a sense amplifier so as to amplify a signal
developed on said sense amplifier data lines, wherein said bit line
pair remains coupled to said sense amplifier data lines at the time
said sense amplifier is set; and configuring the SRAM cell with
PFET access transistors so as to clamp one of said pair of
complementary sense amplifier data lines to a logic high voltage
upon activation of a word line associated with the SRAM cell.
2. The method of claim 1, wherein said clamping is implemented
through one of a pair of pull up transistors within the SRAM
cell.
3. The method of claim 1, wherein said pair of complementary sense
amplifier data lines is coupled to said corresponding pair of
complementary bit lines through a pair of activated bit
switches.
4. A method for implementing a read operation for a static random
access memory (SRAM) cell, the method comprising: activating a word
line associated with the SRAM cell; deactivating a precharge
circuit configured for precharging a pair of complementary bit
lines associated with the SRAM cell; coupling a corresponding pair
of complementary sense amplifier data lines to said pair of
complementary bit lines associated with the SRAM cell; setting a
sense amplifier so as to amplify a signal developed on said sense
amplifier data lines, wherein said bit line pair remains coupled to
said sense amplifier data lines at the time said sense amplifier is
set; and configuring the SRAM cell with PFET access transistors so
as to clamp one of said pair of complementary sense amplifier data
lines to a logic high voltage upon activation of a word line
associated with the SRAM cell.
5. The method of claim 4, wherein said clamping is implemented
through one of a pair of pull up transistors within the SRAM
cell.
6. The method of claim 4, wherein said pair of complementary sense
amplifier data lines is coupled to said corresponding pair of
complementary bit lines through a pair of activated bit
switches.
7. An apparatus for small signal sensing during a read operation of
a static random access memory (SRAM) cell, comprising: a pair of
complementary sense amplifier data lines selectively coupled to a
corresponding pair of complementary bit lines associated with the
SRAM cell; a sense amplifier configured to amplify a signal
developed on said sense amplifier data lines, wherein said bit line
pair is coupled to said sense amplifier data lines whenever said
sense amplifier is set; and a pair of PFET access transistors
associated with the SRAM cell, said PFET access transistors
configured to clamp one of said pair of complementary sense
amplifier data lines to a logic high voltage upon activation of a
word line associated with the SRAM cell.
8. The apparatus of claim 7, wherein said clamp is further
implemented through one of a pair of pull up transistors within the
SRAM cell.
9. The apparatus of claim 7, wherein said pair of complementary
sense amplifier data lines is coupled to said corresponding pair of
complementary bit lines through a pair of activated bit switches.
Description
BACKGROUND
[0001] The present invention relates generally to integrated
circuit memory devices and, more particularly, to an apparatus and
method for small signal sensing in static random access memory
(SRAM) cells utilizing PFET access devices.
[0002] A typical static random access memory (SRAM) cell includes
an array of individual SRAM cells. Each SRAM cell is capable of
storing a binary voltage value therein, which voltage value
represents a logical data bit (e.g., "0" or "1"). One existing
configuration for an SRAM cell includes a pair of cross-coupled
devices such as inverters. With CMOS (complementary metal oxide
semiconductor) technology, the inverters further include a pull-up
PFET (p-channel) transistor connected to a complementary pull-down
NFET (n-channel) transistor. The inverters, connected in a
cross-coupled configuration, act as a latch that stores the data
bit therein so long as power is supplied to the memory array.
[0003] In a conventional six-transistor cell 100 such as shown in
FIG. 1, a pair of access transistors or pass gates T1, T2 (when
activated by a word line LWL) selectively couples the inverters to
a pair of complementary bit lines BLT, BLC. Prior to a read
operation, the bit lines BLT, BLC are precharged to the power
supply voltage VDD. A read operation commences when a restore
circuit (not shown) is turned off, and the word line LWL is driven
high so as to activate NFET pass gates T1, T2. This in turn
electrically connects the internal nodes A, B of the cell 100 to
bit lines BLT, BLC, respectively. Whichever of the two bit lines is
connected to the "low" (logic 0) cell node will begin to discharge
to ground at a rate proportional to the current drive of the cell
(i.e., the series connection of either T2 and T4, or T1 and T3),
and the capacitance of the bit lines. The bit line connected to the
"high" (logic 1) cell node will be left floating high, since its
respective word line access device is cut off (i.e., both the drain
and source terminals thereof are at VDD potential). The voltage
difference between the bit line discharging to ground and the bit
line left floating high is referred to as the bit line signal.
Because the bit lines are typically highly capacitive, and cell
current is typically relatively low, it generally takes a
significant amount of time to generate an adequate amount of signal
to reliably sense and amplify the cell data.
[0004] Accordingly, it would be desirable to be able to accurately
sense the data in an SRAM cell at smaller level of signal
differential than a conventional cell, and thus at an earlier time
in the read cycle.
SUMMARY
[0005] The foregoing discussed drawbacks and deficiencies of the
prior art are overcome or alleviated by a method for small signal
sensing during a read operation for a static random access memory
(SRAM) cell. In an exemplary embodiment, the method includes
coupling a pair of complementary sense amplifier data lines to a
corresponding pair of complementary bit lines associated with the
SRAM cell, and setting a sense amplifier so as to amplify a signal
developed on the sense amplifier data lines, wherein the bit line
pair remains coupled to the sense amplifier data lines at the time
the sense amplifier is set.
[0006] In another embodiment, a method for implementing a read
operation for a static random access memory (SRAM) cell includes
activating a word line associated with the SRAM cell, and
deactivating a precharge circuit configured for precharging a pair
of complementary bit lines associated with the SRAM cell. A
corresponding pair of complementary sense amplifier data lines is
coupled to the pair of complementary bit lines associated with the
SRAM cell, and a sense amplifier is set so as to amplify a signal
developed on the sense amplifier data lines. The bit line pair
remains coupled to the sense amplifier data lines at the time the
sense amplifier is set.
[0007] In still another embodiment, an apparatus for small signal
sensing during a read operation of a static random access memory
(SRAM) cell includes a pair of complementary sense amplifier data
lines selectively coupled to a corresponding pair of complementary
bit lines associated with the SRAM cell, and a sense amplifier
configured to amplify a signal developed on the sense amplifier
data lines. The bit line pair is coupled to the sense amplifier
data lines whenever the sense amplifier is set.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Referring to the exemplary drawings wherein like elements
are numbered alike in the several Figures:
[0009] FIG. 1 is a schematic diagram of a conventional SRAM storage
cell;
[0010] FIG. 2 is a schematic diagram of an SRAM storage cell and
associated sense amplifier, configured in accordance with an
embodiment of the invention;
[0011] FIG. 3 is a timing diagram illustrating a method for small
signal sensing in SRAM cells employing PFET pass gates, in
accordance with a further embodiment of the invention; and
[0012] FIG. 4 is a graph comparing simulated results between a
conventional SRAM read operation and the present method.
DETAILED DESCRIPTION
[0013] Disclosed herein is an apparatus and method for small signal
sensing in SRAM cells, in which a bit switch pair couples a true
and complement bit line pair to a corresponding pair of sense amp
data lines both prior to and during activation of the sense
amplifier. By configuring an SRAM cell with PFET access
transistors, whichever of the bit lines (true or complement) that
is coupled to the high node is clamped to VDD through the
corresponding PFET access transistor of the SRAM cell that is
coupled to the word line. As a result of this clamping assistance
provided by the memory cell PFET, the sense amplifier will be able
to properly amplify with a smaller degree of signal on the bit
lines.
[0014] Referring now to FIG. 2, there is shown a schematic diagram
of an SRAM storage cell 200 and associated sense amplifier 202,
configured in accordance with an embodiment of the invention. In
contrast to the cell 100 shown in FIG. 1, cell 200 utilizes PFET
devices P1, P2 as the access transistors thereto. Accordingly, the
local word line LWL coupled to the gate terminals of P1 and P2 is
active low. FIG. 2 also illustrates a portion of the global word
line circuitry 205, the operation of which is well known to those
skilled in the art.
[0015] The designations "S" and "L" associated with the cell
transistors and the local word line inverter 204 refer to the
relative strengths of the NFET and PFET devices. In a conventional
CMOS inverter or SRAM cell, the relative strength of a PFET pull up
device is weaker with respect to the NFET pull down device. Thus,
the inverter 204 is labeled "S" (small) above the inverter symbol
in FIG. 2 and "L" (large) below the inverter symbol, meaning the
PFET device therein is small compared to the NFET device therein.
In contrast, the SRAM cell 200 in FIG. 2 has large strength pull up
PFETs compared to the cell NFETs, for purposes that will become
apparent hereinafter.
[0016] The bit lines BLT, BLC of cell 200 are precharged to VDD
prior to a read operation by precharge circuitry including a series
of pull up devices 206a, 206b and 206c, controlled by an active low
signal labeled "BL Restore". The precharge circuitry operates in
conjunction with a pair of read bit switches 208a, 208b, controlled
by an active low signal labeled "R Bitswitch". The read bit
switches selectively couple the cell bit line pair BLT, BLC, to a
corresponding sense amplifier data line pair DLT, DLC, during a
read operation. More specifically, during a read operation, the
precharge circuitry is deactivated as the local wordline LWL is
activated so as to couple the SRAM cell nodes to the bit line pair
BLT, BLC. As this occurs, the bit line initially coupled to the
logic high at the beginning of the read operation will begin to
discharge to ground through one of the corresponding SRAM cell
NFETs while the other bit line (left floating at high in a
conventional cell) is actually clamped to VDD due to the PFET
access device (P1 or P2). Therefore, a voltage differential is now
developed across the bit line pair.
[0017] In addition, the signal developed on the bit line pair BLT,
BLC, is also transferred to the sense amplifier data line pair,
since the read bit switches are also activated at the beginning of
the read operation. When a sufficiently large signal (i.e., voltage
differential) is developed on the sense amplifier data line pair
DLT, DLC, the sense amplifier 202 is set (i.e., activated) from an
initial floating state by coupling the NFET devices T1, T2 therein
to ground through a pull down device activated by a set signal
(SET). Once activated, the sense amplifier 202 amplifies the
developed signal on DLT, DLC, to the full VDD swing value. Because
the sense amplifier 202 actually latches a data value opposite that
stored in the SRAM cell 200, a pair of inverters 212a, 212b is used
to drive the correct data onto the data true and complement nodes
DTN, DCN.
[0018] Ignoring momentarily the fact that the present embodiment of
FIG. 2 utilizes PFET access devices, in a conventional SRAM cell
having NFET devices, the activation of the control signals BL
Restore, R Bitswitch and SET are precisely coordinated with one
another with regard to timing and interlocking. This is done so
that the sense amplifier 202 is not set too early before there is
adequate time to develop a sufficiently strong signal differential
on DLT, DLC. If the sense amplifier 202 were to be activated too
early, and if there were a voltage threshold mismatch in the sense
amplifier pull down devices, then it is possible that the sense
amplifier 202 could latch incorrect data therein.
[0019] In contrast, the use of PFET access devices in the present
invention allows the clamping of precharged bit line associated
with the low cell node to VDD through the corresponding PFET access
transistor P1, P2. Moreover, unlike a conventional read operation,
the bit switch pair 208a, 208b, remains active during the setting
of the sense amplifier 202, thereby effectively clamping one of the
data lines to VDD through one of the "large" PFET pull up devices
in the cell 200. However, this would not be the case for an SRAM
cell having NFET access devices, since they would not provide a
clamp to VDD when activated. Moreover, a coupling of the bit line
pair to the data line pair during the sense amplifier set in a
conventional scheme would also provide unwanted capacitive loading
on the sense amplifier, further adding to the signal development
time. Thus, it will be appreciated that with the configuration of
FIG. 2, any problems with voltage threshold mismatch in the sense
amplifier 202 will be easier to overcome. Therefore, the SET signal
can be activated at an earlier point in time when the signal
differential on DLT, DLC is smaller than conventionally
required.
[0020] FIG. 3 is a timing diagram illustrating a read operation
using the cell configuration of FIG. 2. As is shown, the read
operation begins at time t1, at which point the local word line LWL
is rendered active by transitioning from high to low. Concurrently,
the R Bitswitch signal transitions from high to low in order to
couple the sense amplifier data lines to the bit lines, while the
bit line precharge circuitry is deactivated by signal BL Restore
transitioning from low to high. Shortly thereafter, the voltage on
one of the precharged bit lines BLT, BLC begins to drop (as shown
at t2) while the other bit line remains clamped to VDD. Upon
development of a sufficient signal at time t3, the sense amplifier
is activated, reflected by the SET signal transitioning from low to
high in FIG. 3.
[0021] For purposes of illustration, the dashed transition in the R
Bitswitch signal indicates the operation of a conventional cell, in
which the sense amp data lines would be uncoupled from the bit
lines when the sense amplifier is set, as discussed above. However,
in the present embodiment, R Bitswitch remains active through the
setting of the sense amplifier to maintain the clamping function.
Thus, when the amplifier latches the cell data at time t4, the
correct data is read from the cell and the SET signal can be
triggered with a smaller amount of signal present on the bit
lines.
[0022] Finally, FIG. 4 is a graph 400 comparing simulated results
between a conventional SRAM read operation and a read operation in
accordance with the apparatus and method shown in FIGS. 2 and 3.
The upper portion of the graph demonstrates both a successful data
read operation and an unsuccessful data read operation for a
conventional SRAM cell coupled to a sense amplifier having a +30 mV
voltage threshold mismatch on one pull down transistor and a -30 mV
voltage threshold mismatch on the other pull down transistor. With
the conventional cell with NFET access transistors, the read
operation commences at t1 with the word line signal (WL)
transitioning from low to high. In the simulation of FIG. 4, it is
assumed that the SRAM cell node coupled to the true bit line has a
logic 1 stored therein.
[0023] Time t2 in FIG. 4 represents an "early" set of the sense
amplifier; in other words, the amount of time indicated by "WL to
SET #1" is considered to be too early for an appropriate amount of
signal to be developed on the bit line pair (i.e., a relatively
small voltage differential between BLT and BLC). As a result of
both a voltage threshold mismatch in the sense amplifier and an
early set signal at time t2, the sense amplifier has incorrectly
latched the true data line DLT to low and the complementary data
line DLC to high. As such, time t3 (WL to SET #2) may be considered
a sufficiently long time for a signal to be developed on BLT and
BLC. Thus, if the set signal is activated at t3 for the
conventional SRAM cell, the sense amplifier will properly latch DLT
to high and DLT to low.
[0024] In contrast, the lower portion of FIG. 4 illustrates that
the sense amplifier will properly latch DLT and DLC to the correct
logic levels, even if the set signal is activated at the earlier
time t2. Although the signal developed on the bit line pair is
smaller at t2 than at t3, the clamping function provided by the
PFET access transistor combined with keeping the sense amplifier
data line pair coupled to the bit line pair prevents the sense
amplifier from latching an incorrect cell state. Thus configured,
the read operation timings are less susceptible to voltage
threshold mismatches in the sense amplifier, and can allow for
shorter read times.
[0025] While the invention has been described with reference to a
preferred embodiment or embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted for elements thereof without departing from the
scope of the invention. In addition, many modifications may be made
to adapt a particular situation or material to the teachings of the
invention without departing from the essential scope thereof.
Therefore, it is intended that the invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention will include
all embodiments falling within the scope of the appended
claims.
* * * * *