U.S. patent application number 11/326078 was filed with the patent office on 2006-06-08 for lead frame assemblies and decoupling capacitors.
Invention is credited to David J. Corisis, Chris G. Martin.
Application Number | 20060118924 11/326078 |
Document ID | / |
Family ID | 21739035 |
Filed Date | 2006-06-08 |
United States Patent
Application |
20060118924 |
Kind Code |
A1 |
Corisis; David J. ; et
al. |
June 8, 2006 |
Lead frame assemblies and decoupling capacitors
Abstract
A lead frame assembly includes at least two layers, each
including an electrically conductive bus and a group of leads that
extend substantially from a first edge of the assembly. The leads
of each layer may include portions that extend in substantially the
same direction. The electrically conductive buses are at least
partially superimposed with respect to one another. Leads of one of
the layers may be arranged in groups which flank the remainder of
the lead of another layer. A dielectric element is disposed at
least partially between the layers; for example, between at least
portions of the superimposed regions of the buses. One of the buses
may be connectable to a power supply source (V.sub.cc), while the
other may be connectable to a power supply ground (V.sub.ss). In
such an arrangement, the mutually superimposed regions of the buses
may form a decoupling capacitor.
Inventors: |
Corisis; David J.;
(Meridian, ID) ; Martin; Chris G.; (Boise,
ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
21739035 |
Appl. No.: |
11/326078 |
Filed: |
January 5, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10269191 |
Oct 11, 2002 |
|
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11326078 |
Jan 5, 2006 |
|
|
|
09009668 |
Jan 20, 1998 |
6515359 |
|
|
10269191 |
Oct 11, 2002 |
|
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|
Current U.S.
Class: |
257/666 ;
257/E23.057 |
Current CPC
Class: |
H01L 24/48 20130101;
H01L 2924/01076 20130101; H01L 2924/181 20130101; H01L 2224/48091
20130101; H01L 2924/30107 20130101; H01L 2924/19041 20130101; H01L
2224/05554 20130101; H01L 2924/01029 20130101; H01L 24/49 20130101;
H01L 2924/01027 20130101; H01L 2224/49171 20130101; H01L 2224/48247
20130101; H01L 2924/00014 20130101; H01L 2924/01079 20130101; H01L
2224/48095 20130101; H01L 2224/48095 20130101; H01L 2224/48091
20130101; H01L 2224/48257 20130101; H01L 2224/49171 20130101; H01L
2924/181 20130101; H01L 23/49589 20130101; H01L 2924/1433 20130101;
H01L 2924/3025 20130101; H01L 2224/48247 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/00 20130101; H01L
2924/00012 20130101; H01L 2224/05599 20130101; H01L 2924/00014
20130101; H01L 2224/45099 20130101; H01L 2924/00014 20130101; H01L
2224/32145 20130101; H01L 2924/3011 20130101; H01L 2924/14
20130101 |
Class at
Publication: |
257/666 |
International
Class: |
H01L 23/495 20060101
H01L023/495 |
Claims
1. A lead frame assembly, comprising: a first layer including: at
least a portion of a first electrically conductive bus; and a first
group of leads including a first plurality of leads, at least one
of which extends from a first edge of the lead frame assembly; a
second layer including: at least a portion of a second electrically
conductive bus, the second bus being at least partially
superimposed with respect to the first bus; and a second group of
leads including a second plurality of leads, at least one of which
extends from the first edge of the lead frame assembly; and a
dielectric element located between portions of the first and second
layers.
2. The lead frame assembly of claim 1, wherein the first group of
leads is located substantially centrally along an edge of the
semiconductor device assembly and the second group of leads is
located laterally adjacent to the first group of leads.
3. The lead frame assembly of claim 1, comprising two second groups
of leads positioned on opposite sides of the first group of
leads.
4. The lead frame assembly of claim 1, wherein at least one of the
first and second buses is electrically connected to a lead finger
of the first and second groups.
5. The lead frame assembly of claim 1, wherein the dielectric
element is positioned at least partially between superimposed
portions of the first and second electrically conductive buses.
6. The lead frame assembly of claim 5, wherein superimposed
portions of the first electrically conductive bus, the dielectric
element, and the second electrically conductive bus comprise a
capacitor.
7. The lead frame assembly of claim 1, wherein superimposed
portions of the first layer, the dielectric element, and the second
layer comprise a capacitor.
8. The lead frame assembly of claim 1, further comprising: another
dielectric element located on at least one of the first and second
layers, opposite from the dielectric element.
9. The lead frame assembly of claim 8, wherein the another
dielectric element comprises an adhesive material.
10. The lead frame assembly of claim 8, wherein the another
dielectric element is configured to be positioned between the lead
frame assembly and a semiconductor device.
11. The lead frame assembly of claim 1, wherein leads of the first
plurality of leads include portions that are oriented substantially
parallel to one another.
12. The lead frame assembly of claim 11, wherein leads of the
second plurality of leads include portions that are oriented
substantially parallel to one another.
13. The lead frame assembly of claim 1, wherein the first and
second layers mutually define the first edge of the lead frame
assembly.
14. The lead frame assembly of claim 13, wherein the leads of the
first and second pluralities of leads extend from the first
edge.
15. The lead frame assembly of claim 14, wherein the leads of the
first and second pluralities of leads include portions that are
oriented substantially parallel to one another.
16. A decoupling capacitor, comprising: a first layer including: at
least a portion of a first electrically conductive bus; and a first
group of leads including a first plurality of leads; a second layer
including: at least a portion of a second electrically conductive
bus, the second bus being at least partially superimposed with
respect to the first bus; and a second group of leads including a
second plurality of leads; and a dielectric element located at
least partially between superimposed regions of the first and
second electrically conductive buses.
17. The decoupling capacitor of claim 16, wherein the first group
of leads is located substantially centrally along an edge of the
semiconductor device assembly and the second group of leads is
located laterally adjacent to the first group of leads.
18. The decoupling capacitor of claim 16, comprising two second
groups of leads positioned on opposite sides of the first group of
leads.
19. The decoupling capacitor of claim 16, wherein at least one of
the first and second buses is electrically connected to a lead
finger of the first and second groups.
20. The decoupling capacitor of claim 16, further comprising:
another dielectric element located on an exposed surface of at
least one of the first layer and the second layer configured to
separate the first or second layer from a semiconductor device.
21. The decoupling capacitor of claim 20, wherein the another
dielectric element is configured to separate the first or second
layer from a semiconductor device.
22. The decoupling capacitor of claim 20, wherein the another
dielectric element comprises an adhesive material.
23. The decoupling capacitor of claim 20, wherein the another
dielectric element is configured to secure the decoupling capacitor
to the semiconductor device.
24. The decoupling capacitor of claim 16, wherein leads of the
first plurality of leads include portions that are oriented
substantially parallel to one another.
25. The decoupling capacitor of claim 24, wherein leads of the
second plurality of leads include portions that are oriented
substantially parallel to one another.
26. The decoupling capacitor of claim 16, wherein the first and
second layers mutually define a common edge of the decoupling
capacitor.
27. The decoupling capacitor of claim 26, wherein the leads of the
first and second pluralities of leads extend from the common
edge.
28. The decoupling capacitor of claim 27, wherein the leads of the
first and second pluralities of leads are oriented substantially
parallel to one another.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No.
10/269,191, filed Oct. 11, 2002, pending, which is a continuation
of application Ser. No. 09/009,668, filed Jan. 20, 1998, now U.S.
Pat. No. 6,515,359, issued Feb. 4, 2003.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to semiconductor device
assemblies employing multi-layered lead frames and, more
specifically, to semiconductor device assemblies disposing a
decoupling capacitor in a close, substantially co-extensive
relationship with a semiconductor device bearing an integrated
circuit.
[0004] 2. Background of Related Art
[0005] There is a continued trend in the computer industry toward
ever-higher speed integrated circuit (IC) assemblies based upon
semiconductor device technology. Such high signal speeds, however,
lack utility unless accompanied by suppression of system noise to
an acceptable level. The trend toward lower operational signal
voltages in combination with such high speeds exacerbates noise
problems.
[0006] At state-of-the art operational speeds, signal propagation
delays, switching noise, and crosstalk between signal conductors
resulting from mutual inductance and self inductance phenomena of
the conductive paths all become significant to signal degradation.
Mutual inductance results from an interaction between magnetic
fields created by signal currents flowing to and from a lead
frame-mounted, packaged semiconductor device through the leads or
"lead fingers," while self inductance results from the interaction
of the foregoing fields with magnetic fields created by
oppositely-directed currents flowing to and from ground.
[0007] Therefore, the integrated circuits carried on a
semiconductor device would ideally be electrically connected to
conductive traces on carrier substrates such as printed circuit
boards and thus to other semiconductor devices carried on the same
or other such substrates by infinitesimally short conductors,
eliminating impedance problems such as undesirable inductance and
other conductor-induced system noise.
[0008] As a practical matter, however, as the capacity and speed of
many semiconductor devices such as dynamic random access memories
(DRAMs) has increased, the number of inputs and outputs (I/Os) to
each semiconductor device has increased, requiring more numerous
and complex external connections thereto, and in some instances
requiring undesirably long lead frame lead fingers to place the
inner lead ends in contact with, or in close proximity to, the bond
pads serving as I/Os for the typical semiconductor device.
[0009] While lead inductance in IC packages has not traditionally
been troublesome because slow signal frequencies of past devices
render such inductance relatively insignificant, faster and
ever-increasing signal frequencies of state-of-the-art electronic
systems have substantially increased the practical significance of
lead inductance. For example, at such faster signal frequencies,
performance of integrated circuit dice using lead frames for
external electrical connection is slower than desirable because the
inductance associated with the lead fingers slows changes in signal
currents through the leads, prolonging signal propagation through
the leads. Further, digital signals propagating along the lead
fingers are dispersing or "spreading out" because the so-called
"Fourier" components of various frequencies making up the digital
signals propagate through the inductance associated with the lead
fingers at different speeds, causing the signal components and thus
the signals themselves to disperse along the lead fingers. While
mild dispersion merely widens the digital signals without
detrimental effect, severe dispersion can make the digital signals
unrecognizable upon receipt. In addition, so-called "reflection"
signals propagating along the lead fingers as a result of impedance
mismatches between the lead fingers and associated semiconductor
device or between the lead fingers and external circuitry, caused
in part by lead-associated inductance, can distort normal signals
propagating along the lead fingers concurrently with the reflection
signals. Further, magnetic fields created by signal currents
propagating through the lead-associated inductance can induce
currents in adjacent lead fingers, causing so-called "crosstalk"
noise on the latter. While these various effects might be
troublesome in any electronic system, the aforementioned trend
toward lower voltage systems (currently 3.3 volts) and away from
the traditional 5.0 volt systems increases their visibility and
significance.
[0010] Certain currently-popular semiconductor device and package
configurations serve to exacerbate the noise problems by favoring a
large plurality of laterally adjacent lead fingers of substantial
length. For example, so-called lead-over-chip (LOC) configurations
typically place the bond pads of a semiconductor device in one or
two rows extending along the longitudinal axis of the semiconductor
device. To accommodate the centralized bond pad location for
wire-bonding and at the same time eliminate the need for a
conventional die-attach paddle as a physical semiconductor device
support, LOC lead frames have been developed which employ lead
fingers extending from the sides of the semiconductor device and
over the active surface into close proximity with the bond pad row
or rows. The semiconductor device is then supported from the
undersides of the extending lead fingers, typically through an
intervening polyimide film such as a Kapton.TM. tape having an
adhesive coating on its upper and lower surfaces, the film serving
as a dielectric, an alpha barrier and a protective coating for the
active surface.
[0011] While a mechanically desirable packaging concept, the
LOC-type long, mutually parallel lead fingers running over the
active surface become abusive in terms of unacceptably increasing
real impedance as well as lead inductance (both self and mutual) in
the circuit. These lead finger runs also increase signal reflection
in the circuit due to transmission line effects and degrade signal
integrity due to the aforementioned propagation delays, switching
noise, and crosstalk. Further, elimination of the die-attach paddle
also eliminates the potential for employing a ground plane under
the semiconductor device without additional processing steps, and
such a ground plane in any case would not alleviate the problems
attendant to use of the long lead fingers extending over the
semiconductor device's active surface.
[0012] LOC configurations are merely one example of the type of
packaging promoting the above-referenced undesirable noise
phenomena. However, the same undesirable characteristics may be
experienced with other lead frame configurations employing extended
lead fingers, particularly large groups of such lead fingers in
close mutual proximity. Such configurations include lead-under-chip
(LUC) configurations, and configurations wherein a large number of
leads extend from several sides of a semiconductor device to a
single side or edge of a package, such as in a vertical surface
mount package, or VSMP.
[0013] Packages have previously been configured in an attempt to
reduce package noise of the type described above. For example, U.S.
Pat. No. 5,214,845, assigned to the assignee of the present
invention, employs a flexible, laminated sandwich assembly of an
outer ground plane and an outer power plane dielectrically isolated
from a series of conductive traces running therebetween. The traces
and planes are connected to corresponding bond pads on the
semiconductor device at one end, and to lead fingers on the other,
as by thermocompression bonding (in the case of a TAB embodiment)
or by wire bonds. Such an arrangement obviously doubles the number
of required I/O connections, necessitating additional fabrication
time and increasing the possibility of a faulty connection.
Further, the flexible sandwich assembly constitutes an additional
element of the package, increasing material cost.
[0014] Another approach to the problem is disclosed in U.S. Pat.
No. 5,559,306, wherein metal plates are employed above and below
leads extending to the exterior of plastic and ceramic packages to
effect reduction of self and mutual inductance. However, such
configurations as disclosed appear to require relatively complex
fabrication techniques to locate and fix the plates relative to the
semiconductor device and lead fingers or other conductors for
subsequent transfer molding of a filled-polymer package thereabout,
while the ceramic package embodiment is not cost-effective for
high-volume, commercial packaging.
[0015] Accordingly, the inventors have recognized the need for a
low-cost, reduced-inductance circuit configuration adaptable to
current packaging designs and employing conventional and
readily-available materials, equipment and fabrication
techniques.
SUMMARY OF THE INVENTION
[0016] A semiconductor device package according to the present
invention includes a substrate and a semiconductor device disposed
upon the substrate.
[0017] A multi-layer lead frame of the leads-over-chip (LOC) type,
leads-under-chip (LUC) type, or other type of lead frame
arrangement provides an electrically conductive passageway from the
semiconductor device disposed upon the substrate to devices that
are external of the assembly. The multiple layers of the lead frame
are joined by an interposed dielectric layer, which is also
referred to as an insulator element, and each include a wide,
electrically conductive bus. The layers may form a "paddle" or
"support platform" to which a semiconductor device is secured. The
bus of one of the lead frame layers is a power supply bus, while
the bus of the other lead frame layer is a ground bus. The buses of
each layer at least partially overlap to form a decoupling
capacitor over a portion of the semiconductor device.
[0018] One of the lead frame layers includes a wide bus having one
or more ground (V.sub.ss) lead fingers electrically connected
thereto. Another of the lead frame layers includes a wide bus
having one or more power (V.sub.cc) lead fingers electrically
connected thereto.
[0019] The decoupling capacitor reduces coupling and suppresses
noise that is typically produced by the power supply components.
Moreover, the juxtaposition and placement of the power supply lead
fingers adjacent the sides of the semiconductor device package and
away from (i.e., not interleaved with) the remaining lead fingers
reduces the troublesome characteristics of mutual inductance and
self inductance. Further, the placement of the buses in positions
that would otherwise be occupied by long, adjacent, bent lead
fingers also eliminates the magnetic fields that are typically
generated by such lead fingers.
[0020] The multi-layer lead frame of the present invention also
imparts at least a nominal heat sink effect to the semiconductor
device, promoting the more even distribution of heat that is
generated during operation of the semiconductor device than might
be achieved through the lead fingers alone. This heat sink effect
may be enhanced by increasing the mass of one or more of the lead
frame buses, as by enhancing their thickness within the constraints
of the package dimensions, or by configuring the buses with one or
more portions extending to the exterior of the package. While this
latter approach may render the device more susceptible to external
radio-frequency interference, such an arrangement may be shielded,
if necessary, by techniques known in the art. Such variation is
especially useful in embodiments of the present invention wherein
the semiconductor device is enclosed in a plastic, ceramic, or
other type of package.
[0021] Should the device to be fabricated comprise a
leads-over-chip device, conventional polyimide or other dielectric
film or tape strips may be adhered to one side of the lead fingers,
and the semiconductor devices subsequently adhered to the film by
their active surfaces as known in the art prior to electrical
connection of the semiconductor device and lead frames.
[0022] Those of ordinary skill in the art will recognize and
appreciate that the multi-layered lead frame according to the
present invention may be employed for an enhancement to any
conventional plastic package design having adequate depth between
the planes in which the lead fingers are positioned and the
exterior surface of the package.
[0023] Other advantages of the present invention will become
apparent to those of ordinary skill in the relevant art through a
consideration of the appended drawings and the ensuing
description.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0024] FIG. 1 is a top plan view of a vertical surface mount
package- (VSMP-) configured semiconductor device and multi-layered
lead frame assembly secured together such that the lead frame
overlaps the active surface of the semiconductor device, and
employing a decoupling capacitor according to the present
invention;
[0025] FIG. 1A is a schematic view of a variation of the
VSMP-configured semiconductor device and multi-layered lead frame
assembly shown in FIG. 1, wherein the leads of each lead frame
layer extend partially over the active surface of the semiconductor
die;
[0026] FIG. 2 is an enlarged side plan view of the assembly of FIG.
1;
[0027] FIG. 3 is an enlarged side plan view illustrating a vertical
surface mount package-configured semiconductor device and lead
frame assembly secured together such that the lead frame overlaps
the back side of the semiconductor device, and employing a
decoupling capacitor according to the present invention;
[0028] FIG. 4 is a top plan view of a packaged embodiment of the
assembly of the present invention, depicting an alternative
decoupling capacitor wherein at least one of the capacitor plates
extends to the periphery of the package to provide enhanced heat
transfer and distribution capabilities;
[0029] FIG. 5 is an enlarged side plan view of a portion of a
leads-over-chip- (LOC-) configured semiconductor device and lead
frame assembly as depicted in FIG. 4, but employing at least one
capacitor plate modified to provide enhanced heat transfer and
distribution capabilities;
[0030] FIG. 6 is a top plan view of the assembly in FIG. 1,
depicting alternatively shaped lead frame layers; and
[0031] FIG. 7 is a schematic representation of the semiconductor
device assembly according to the present invention associated with
an electronic system.
DETAILED DESCRIPTION OF THE INVENTION
[0032] With reference to FIGS. 1 and 2, a semiconductor device
assembly 20 of the present invention is shown which includes a
semiconductor device 100, also termed an integrated circuit die,
that is mounted to a lead frame 102 and upon a substrate 108 in a
vertical surface mount package (VSMP) configuration. An outline of
the outer periphery of substrate 108 is shown at line 110. Lead
frame 102 includes a plurality of lead fingers 104, 105A, 105B,
each of which are configured to extend across the outer periphery
of substrate 108 along a single side or edge 106 thereof for
external connection.
[0033] Substrate 108 preferably comprises any suitable, well-known
substrate material for use with a semiconductor device.
Semiconductor device 100 may be secured to a major surface of
substrate 108 by any suitable means, such as adhesive
attachment.
[0034] As shown, lead frame 102 includes a first layer 102A and a
second layer 102B and performs as a die attach paddle, to which the
active surface 122 of semiconductor device 100 is secured. Lead
frame 102 may be secured to substrate 108 so that first bus 112
overlaps semiconductor device 100 and so the lead frame is oriented
relative to the semiconductor device in either a lead-over-chip
(LOC) configuration or so the lead fingers 104, 105A, 105B thereof
terminate proximate to the periphery of the semiconductor device,
without overlapping the same. Alternatively, lead frame 102 may be
secured to substrate 108, and the back side of semiconductor device
100 disposed over the lead frame, such as in a leads-under-chip
configuration or otherwise. Lead fingers 104 may also be attached
to substrate 108. The securing material 111, which secures
semiconductor device 100 and/or lead frame 102 to substrate 108, is
preferably a good thermal conductor to facilitate the distribution
and dissipation of heat from semiconductor device 100 to lead frame
102 and/or substrate 108. Securing material 111 may comprise any
suitable well-known type of electrically insulative film that may
be adhesively coated to secure semiconductor device 100 and lead
frame 102 to substrate 108, such as the polyimide film having
adhesive on both surfaces thereof that is sold under the trade name
KAPTON.TM. by E.I. du Pont de Nemours & Company of Wilmington,
Del.
[0035] Returning to FIGS. 1 and 2, the first layer 102A of lead
frame 102 includes an electrically conductive, wide first bus 112
that extends over a portion of the surface of semiconductor device
100 and a first plurality of lead fingers 105A, 105B that extend in
substantially the same direction. Lead fingers 105A, 105B of first
layer 102A extend from or are otherwise electrically connected with
first bus 112.
[0036] Second layer 102B includes an electrically conductive, wide
second bus 114 that also extends over a portion of the surface of
semiconductor device 100 and a second plurality of lead fingers 104
that extend therefrom in substantially the same direction. Some of
lead fingers 104 extend from or are otherwise electrically
connected with second bus 114. First bus 112 and second bus 114 are
oriented in such a manner that a substantial portion of the area of
each of first bus 112 and second bus 114 overlap.
[0037] First bus 112 and second bus 114 each preferably comprise a
low resistivity, high conductivity sheet of material such as copper
or gold, although copper is preferred from a cost standpoint. An
insulating element 148 (FIG. 2) is disposed between first layer
102A and second layer 102B to adhere the first and second lead
frame layers together and to separate the overlapping portions of
first bus 112 and second bus 114. Insulating element 148 is
preferably manufactured from a dielectric or insulating material
such as a polyimide film carrying adhesive on both surfaces
thereof. An example of such a film is that sold under the trade
name KAPTON.TM. by du Pont.
[0038] Bond wires 124 establish electrical connections between bond
pads 120 on the active surface 122 of semiconductor device 100 and
the lead fingers 104 of lead frame 102. Thus, bond wires 124
facilitate the passage of signals between the integrated circuitry
that is carried on active surface 122 of semiconductor device 100
and external circuitry (not shown), such as conductive traces on a
carrier substrate (e.g., a printed circuit board), and other
conductors and active and passive components packaged in the same
or a higher level. Alternatively, as depicted in FIG. 1A, device
assemblies which employ direct thermocompression bonding of lead
fingers 104, 105A, 105B to bond pads 120, flex-circuit-type
connections between lead fingers 104, 105A, 105B and bond pads 120
using conductors in a preformed pattern carried on a thin
dielectric (typically termed tape automated bonding, or "TAB,"
connections), or other known apparatus and processes may be
employed for establishing electrical connections with the bond pads
of a semiconductor device.
[0039] A central group 140 of lead fingers 104 extends between a
side 126 of semiconductor device 100 that lies closest to edge 106
of substrate 108. Each of the lead fingers 104 of central group 140
are extremely short, straight, mutually parallel, and of
substantially uniform length. Adjacent each side of central group
140 are flanking groups 141 and 142 of discrete lead fingers 104.
Each lead finger in flanking groups 141 and 142 extends between
transverse sides 128 and 130 of semiconductor device 100 and edge
106 and have various lengths. Most of the lead fingers 104 of
flanking groups 141 and 142 curve to form a 90-degree angle from
their respective, substantially perpendicular orientation relative
to transverse sides 128, 130 to an orientation that is
substantially perpendicular to edge 106 as they exit the
latter.
[0040] Flanking groups 141 and 142 are each flanked by a group of
lead fingers 105B, which are electrically connected with and may be
commonly connected to and extend from second bus 114, and are
referred to as second bus extension groups 143 and 144,
respectively. In turn, each of second bus extension groups 143 and
144 are flanked by another group of lead fingers 105A that are
electrically connected with first bus 112, and are referred to as
first bus extension groups 145 and 146, respectively. Lead fingers
105A may be commonly connected to first bus 112 and extend
therefrom.
[0041] One of the first and second buses 112 or 114 is electrically
connected to a ground (V.sub.ss) through its respective groups of
lead fingers 105A, 105B while the other of the buses is
electrically connected to a power supply source (V.sub.cc), which
is also referred to as a power source (V.sub.cc), through its
respective groups of lead fingers 105A, 105B. As depicted, first
bus 112 of first layer 102A of lead frame 102 may be electrically
connected to a power source (V.sub.cc) by its corresponding lead
fingers 105A (of first bus extension groups 145 and 146), and
second bus 114 is electrically connected to a ground (V.sub.ss) by
its corresponding lead fingers 105B (of second bus extension groups
143 and 144). By commonly connecting lead fingers 105A to each
other and lead fingers 105B to each other, as depicted, impedance
is reduced, thereby facilitating the use of semiconductor devices
100 having high operating frequencies in semiconductor device
assembly 20. Additionally, the depicted arrangement imparts lead
fingers 105A and 105B with impedance that is similar to that of
lead fingers 104.
[0042] The ground and power supply bond pads 120 on semiconductor
device 100 are electrically connected (by bond wires 124) to the
respective ground bus (second bus 114 in the embodiment illustrated
in FIGS. 1 and 2) and power supply bus (first bus 112 in the
embodiment illustrated in FIGS. 1 and 2). Preferably, the shape and
orientation of the first and second buses 112 and 114 facilitate
the use of very short bond wires 124 in order to reduce the
conductor inductances between the decoupling capacitor and the bond
pads 120 that are electrically connected therewith.
[0043] First bus 112 and second bus 114 act as capacitor plates
and, in combination with insulating element 148, create a
decoupling capacitor 116 that extends over a portion of the surface
of semiconductor device 100. Alternatively, the orientation of
V.sub.cc and V.sub.ss (i.e., of first bus 112 and second bus 114)
relative to semiconductor device 100 may be reversed, as may the
positioning of the first and second bus extension groups 145, 146
and 143, 144 relative to flanking groups 141 and 142.
[0044] Preferably, as illustrated in FIG. 1, the power supply
(V.sub.cc) lead fingers 105A (i.e., the lead fingers of groups 145
and 146) are separated from the lead fingers 104 of central group
140 and flanking groups 141 and 142 by grounded lead fingers 105B
(i.e., the lead fingers of groups 143 and 144). This arrangement
reduces the incidence of magnetic coupling or mutual inductance
that may be caused by a power supply lead finger that is adjacent
to another lead finger.
[0045] Decoupling capacitor 116 and the juxtaposition and grouping
of power supply lead fingers 105A in first bus extension groups 145
and 146 (i.e., their isolation from the majority of lead fingers
104), as well as the juxtaposition and grouping of ground lead
fingers 105B in second bus extension groups 143 and 144, alleviate
the aforementioned detrimental effects of many packaged
semiconductor devices in the prior art by lowering inductance,
decoupling the power supply (V.sub.cc) from the ground (V.sub.ss),
and thereby benefiting the electrical performance of the integrated
circuitry carried by the associated semiconductor device 100 (e.g.,
by decreasing impedance, improving reflection, providing better
signal integrity, etc.).
[0046] With continued reference to FIGS. 1 and 2, semiconductor
device 100 preferably comprises a 64-megabit vertical surface mount
package-configured, seventy (70) lead dynamic random access memory
(DRAM), although the invention is not limited to the package
configuration shown and described, or to a dynamic random access
memory or other memory devices including, without limitation,
static random access memories (SRAMs), synchronous dynamic random
access memories (SDRAMs), sequential graphics random access
memories (SGRAMs), electrically erasable programmable read-only
memories (EEPROMS) and flash memories. The invention also has
utility with regard to processors and application-specific
integrated circuits (ASICs).
[0047] Referring to FIG. 3, another embodiment of the semiconductor
device assembly 20' according to the present invention is shown
wherein the multi-layered lead frame 202, including a first bus 212
and a second bus 214, is attached to the base 218 of semiconductor
device 200 with a securing material 211, such as that described
above in reference to FIG. 1. First bus 212 and second bus 214 are
separated by an insulating element 248, such as that described
above in reference to FIG. 1, in order to form a decoupling
capacitor. Lead fingers 204, which preferably extend substantially
unidirectionally from semiconductor device assembly 20', are
electrically connected with bond pads 220 on the active surface 222
of semiconductor device 200. This electrical connection may be
established by bond wires 224, or as otherwise known in the art. A
so-called "plastic" package 208, as known in the art, may be
disposed over semiconductor device 200 and lead frame 202.
[0048] Turning now to FIG. 4, semiconductor device assembly 20 may
also comprise a so-called "plastic" package 109' comprising a
transfer-molded, filled polymer compound, as known in the art
(FIGS. 1 and 2 also depict a package 109). However, alternative
packaging such as preformed ceramic packages and potted
encapsulants may also be used in the present invention.
[0049] If desired, or required by excessive heat output from a
particular semiconductor device 100', lead frame 102', which
include layers 102A' and 102B', may also include extensions 113' of
either first bus 112', second bus 114', or both of them which
extend to the outer periphery of the semiconductor device package
in order to facilitate the dissipation of heat from the same. While
extensions 113' may render the semiconductor device package more
susceptible to external radio-frequency interference, such an
arrangement may be shielded, if necessary, by techniques known in
the art.
[0050] Similarly, with reference to FIG. 5, in another embodiment
of the semiconductor device assembly 20'', if desired or required
by excessive heat output from a particular semiconductor device
200', the outermost (relative to the semiconductor device) bus 212'
may be configured with additional mass in the form of fins or other
projections 270' opposite the underlying bus 214' and the
semiconductor device. Projections 270' may extend to the exterior
of package 209', which surrounds semiconductor device 200', as
shown in broken lines 272'. Other mass increasing configurations
are also possible and limited only by the available interior space
of the package and the need to maintain the electrical performance
of the packaged device. The approach of extending a portion of
outermost bus 212' to the exterior of package 209' may render the
semiconductor device package 20'' susceptible to external
radio-frequency interference. However, shielding techniques are
known in the art, and may be employed if necessary with a package
so configured.
[0051] The heat sinks depicted in FIGS. 4 and 5 may also be used in
embodiments of the semiconductor device assembly that are not
enclosed within a package.
[0052] FIG. 6 illustrates a variation of the lead frame layers 102A
and 102B of semiconductor device package 20, wherein the shape of
the lead frame layers differs from that illustrated in FIGS. 1 and
4.
[0053] To maximize the benefit of the invention during
implementation thereof, an attempt should be made to maximize the
surface area of the decoupling capacitor. It may be preferable, if
possible, to extend the buses laterally beyond the sides of the end
lead fingers of a group, since the electrical field lines tend to
be radial. It is also noteworthy that the decoupling capacitor of
the invention also provides a modest improvement to electromagnetic
interference (EMI) shielding. Finally, as those of ordinary skill
in the art will appreciate, the beneficial effect of the invention
also is dependent upon the distance between the capacitor plates
(i.e., the buses), as well as the material chosen for the insulator
element.
[0054] As a matter of practical and effective implementation of the
present invention, there are several factors to be accommodated.
First, if the buses are to be wire bonded to the semiconductor
device bond pads, the buses should extend over the semiconductor
device in a manner which permits the wire-bonding capillary to form
a wire bond over the desired bond pads. Additionally, the
transverse distance or space between the buses should be minimized,
in order to maximize the beneficial effects of the invention.
Finally, the surface areas of the coextensive portions of the buses
should be maximized, but a sufficient portion of the periphery of
the buses should be contained within the material of the package
surrounding the semiconductor device and lead frame combination,
with enough space or clearance between the edges of the buses and
the exterior of the package so that package integrity and
reliability is not affected.
[0055] FIG. 7 is a schematic representation of an electronic system
700, which includes a carrier substrate 702. A semiconductor device
assembly 20 according to the present invention is in electrical
communication with carrier substrate 702. Thus, semiconductor
device assembly 20 is operatively associated with electronic system
700.
[0056] Although the foregoing description contains many
specificities, these should not be construed as limiting the scope
of the present invention, but merely as providing illustrations of
some of the presently preferred embodiments. Similarly, other
embodiments of the invention may be devised which do not depart
from the spirit or scope of the present invention. The scope of
this invention is, therefore, indicated and limited only by the
appended claims and their legal equivalents, rather than by the
foregoing description. All additions, deletions and modifications
to the invention as disclosed herein which fall within the meaning
and scope of the claims are to be embraced within their scope.
* * * * *