U.S. patent application number 11/206613 was filed with the patent office on 2006-06-01 for selective spacer layer deposition method for forming spacers with different widths.
Invention is credited to Ming-Ta Lei, Cheng-Chung Lin, Chia-Hui Lin, Yih-Shung Lin, Ai-Sen Liu, Baw-Ching Perng.
Application Number | 20060113616 11/206613 |
Document ID | / |
Family ID | 33097783 |
Filed Date | 2006-06-01 |
United States Patent
Application |
20060113616 |
Kind Code |
A1 |
Liu; Ai-Sen ; et
al. |
June 1, 2006 |
Selective spacer layer deposition method for forming spacers with
different widths
Abstract
A method of forming spacers with different widths on a
semiconductor substrate, includes the steps of disposing a first
spacer layer over the substrate, defining the first spacer layer
into a plurality of spacers of a first width, and disposing a
second spacer layer selectively over the first spacer layer of a
number of the spacers preselected for the second spacer layer, the
predetermined number of the spacers with the second spacer layer
each having a second width which is different from the first
width.
Inventors: |
Liu; Ai-Sen; (Hsinchu City,
TW) ; Perng; Baw-Ching; (Hsin-Chu County, TW)
; Lei; Ming-Ta; (Hsin-Chu, TW) ; Lin;
Yih-Shung; (Sanchung, TW) ; Lin; Cheng-Chung;
(Taipei, TW) ; Lin; Chia-Hui; (Hsin-Chu,
TW) |
Correspondence
Address: |
Duan Morris LLP
P.O. Box 5203
Princeton
NJ
08543-5203
US
|
Family ID: |
33097783 |
Appl. No.: |
11/206613 |
Filed: |
August 18, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10408689 |
Apr 7, 2003 |
6943077 |
|
|
11206613 |
Aug 18, 2005 |
|
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Current U.S.
Class: |
257/412 ;
257/900; 257/E21.241; 257/E21.268; 257/E21.624; 257/E21.626;
257/E27.06 |
Current CPC
Class: |
H01L 21/823456 20130101;
H01L 29/6656 20130101; H01L 21/823468 20130101; H01L 21/3144
20130101; H01L 21/3105 20130101 |
Class at
Publication: |
257/412 ;
257/900; 257/E27.06 |
International
Class: |
H01L 29/94 20060101
H01L029/94 |
Claims
1-24. (canceled)
25. A semiconductor device comprising: a substrate; a plurality of
spacers disposed on the substrate; a first number of the spacers
formed by a first spacer layer of a first dielectric material, the
first spacer having a first width; and a second number of the
spacers defined by the first spacer layer of the first dielectric
material and at least a second spacer layer of a second dielectric
material, the second spacer having a second width which is
different than the first width, the at least second dielectric
material comprising one of an oxygen-rich SiON and a nitrogen-rich
SiON.
26. The semiconductor device according to claim 25, wherein the
first dielectric material comprises SiO.sub.2 and the second
dielectric material comprises the oxygen-rich SiON.
27. The semiconductor device according to claim 26, further
comprising a third number of the spacers defined by the first
spacer layer of the first dielectric material, the second spacer
layer of the second dielectric material, and a third spacer layer
of a third dielectric material, the third spacer having a third
width which is different than the first and second widths, the
third dielectric material comprising the nitrogen-rich SiON.
28. The semiconductor device according to claim 25, further
comprising a third number of the spacers defined by the first
spacer layer of the first dielectric material, the second spacer
layer of the second dielectric material, and a third spacer layer
of a third dielectric material, the third spacer having a third
width which is different than the first and second widths, the
third dielectric material comprising one of the oxygen-rich SiON
and the nitrogen-rich SiON.
29. The semiconductor device according to claim 25, wherein the
first dielectric material comprises SiN and the second dielectric
material comprises the nitrogen-rich SiON.
30. The semiconductor device according to claim 29, further
comprising a third number of the spacers defined by the first
spacer layer of the first dielectric material, the second spacer
layer of the second dielectric material, and a third spacer layer
of a third dielectric material, the third spacer having a third
width which is different than the first and second widths, the
third dielectric material comprising the oxygen-rich SiON.
Description
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/408,689, filed Apr. 7, 2003. The entire disclosure of
U.S. patent application Ser. No. 10/408,689 is incorporated herein
by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to a method of fabricating a
semiconductor device, and more particularly, to a method of forming
spacers with different widths on a semiconductor substrate.
BACKGROUND OF THE INVENTION
[0003] Fabricating integrated circuits with faster and/or an
increasing number of semiconductor devices is a continuing trend in
integrated circuit technology. A very influential factor in this
trend is technology scaling, i.e., the reduction in transistor
feature sizes. Technology scaling has enabled transistors to become
smaller, thus allowing for more dense integrated circuits in terms
of the number of transistors packed on a chip.
[0004] At virtually the same time that transistors are becoming
smaller, chip sizes have been increasing in size. The chip size
increase has, in turn, resulted in transistor driving capability
decreases and interconnect parasitics increases. Accordingly,
integrated circuits, such as, embedded memory circuits,
mixed-mode/RF signal circuits, and System on a Chip (SOC) circuits,
must be very carefully designed to meet future speed demands.
Design issues which are very critical in the development of such
circuits include, for example, transistor architecture.
Specifically, careful gate design, transistor sizing, and other
such feature parameters are extremely important in order to
optimize transistor performance.
[0005] Spacers are commonly used in the fabrication of
semiconductor devices and integrated circuits. The spacers may be
used, for example, to control transistor gate size, source and
drain regions placement or other features. Because variously sized
transistors and other features are often required in a particular
integrated circuit design, spacers of different widths must be
utilized during the fabrication thereof.
[0006] Spacers of different widths are typically formed using
conventional etching methods. These etching methods, unfortunately,
may damage the thin, dielectric gate insulating layer and
substrate. Accordingly, a new method is needed for forming spacers
of varying width.
SUMMARY OF THE INVENTION
[0007] A method is disclosed herein for forming spacers with
different widths on a semiconductor substrate. The method comprises
the steps of disposing a first spacer layer over the substrate,
defining the first spacer layer into a plurality of spacers of a
first width, and disposing a second spacer layer selectively over
the first spacer layer of a number of the spacers preselected for
the second spacer layer, the predetermined number of the spacers
with the second spacer layer each having a second width which is
different from the first width.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1-7 are cross sectional views illustrating a method
for forming spacers with different widths on a semiconductor device
according to the present invention.
DETAILED DESCRIPTION
[0009] FIGS. 1-7 illustrate a method for forming two or more
spacers with different widths on a semiconductor device according
to the present invention.
[0010] Referring to FIG. 1, there is illustrated a cross-section of
a portion of a semiconductor device 10. The semiconductor device 10
includes a substrate 20 that may be comprised of a semiconductor
material, such as single crystal silicon or gallium arsenide. A
plurality of features with different line widths are disposed over
the substrate 20 and may include, for purposes of illustrating the
method of the invention and not limitation, a first gate electrode
30a of a first length, a second gate electrode 30b of a second
length, and a third gate electrode 30c of a third length are
disposed over the substrate 20. The different gate lengths used in
this embodiment of the invention may be provided, for example, to
optimize the transistor performance of an embedded DRAM
semiconductor device 10. The gate electrodes 30a-30c are
electrically insulated from the substrate 20 by thin, dielectric
gate insulating layers 32a-32c.
[0011] The gate electrodes 30a-30c may be formed from a
polysilicon, such as undoped poly, amorphous poly, doped poly, and
the like, using conventional forming methods, such as physical
vapor deposition (PVD) or chemical vapor deposition (CVD). The
thin, dielectric gate insulating layers 32a-32c, may be formed on
the substrate 20 from an oxide layer using conventional forming
methods, such as physical or chemical vapor deposition, prior to
the formation of the gate electrodes 30a-30c. In another
embodiment, the thin, dielectric gate insulating layers may be
formed from a nitride layer.
[0012] Referring to FIG. 2, a first dielectric insulating spacer
layer 40 is formed over the substrate 10 and gate electrodes
30a-30c using conventional forming methods, such as PVD or CVD. The
first spacer layer 40 may be formed from a nitride such as silicon
nitride SiN, or an oxide such as silicon oxide SiO.sub.2. The first
spacer layer 40 may be deposited to a thickness ranging from
approximately 500 .ANG. to 1000 .ANG..
[0013] Referring to FIG. 3, a first patterned photoresist layer or
mask layer (not shown) is provided over the first spacer layer 40,
and the semiconductor device 10 is anisotropically etched to define
the first spacer layer 40 into three spacers 50a-50c each having
the same width W1, adjacent the side walls of the gate electrodes
30a-30c. The anisotropic etch may be performed using a conventional
plasma reactive-ion etching method. After etching, the first mask
layer is removed.
[0014] Referring to FIG. 4, spacers of other widths are formed in
accordance with the present invention using selective deposition.
For example, spacers having a width W2, which is greater than width
W1, may be formed by providing a second mask layer 60 over the
spacer 50a of the first width and adjacent gate electrode 30a, and
then selectively depositing a second spacer layer 70 over the first
spacer layer 40 of the two unmasked spacers 50b and 50c. The
selective deposition may be accomplished by treating the substrate
20 with a plasma to generate dangling bonds on the surface of the
first spacer layer 40 of the two unmasked spacers 50b and 50c. The
dangling bonds alter the chemical properties of the surface, e.g.
the bonding properties, solvent resistivity properties, and the
like. The plasma treatment does not generate dangling bonds on the
unmasked gate electrodes 30b and 30c and the substrate 20 because
these features are made from different materials than the first
spacer layer 40. After the plasma treatment, the second spacer
layer 70 may be formed over the substrate using PVD or CVD. The
portions 70a of the second spacer layer 70 overlying the first
spacer layers 40 of the unmasked spacers 50b and 50c firmly bond
thereto via the dangling bonds at the interface of the first spacer
layer 40 and the directly overlying portions 70a of the second
spacer layer 70. However, the portions 70b of the second spacer
layer 70 directly overlying the untreated features are easily
removed using for example, a wet bench, due to the lack of dangling
bonds at the interface thereof. After enlarging the spacers 50b and
50c, the second mask layer 60 may then be removed.
[0015] FIG. 5 illustrates the device 10 after removal of the weakly
bonded portions of the second spacer layer 70. As illustrated, the
selective deposition process enlarges the spacers 50b and 50c to a
width W2.
[0016] If spacers having a width W3, which is greater than width
W2, are desired, a third mask layer 80 may be provided over the
spacer 50a of width W1 and its adjacent gate electrode 30a and
spacer 50b of width W2 and its adjacent gate electrode 30b as
illustrated in FIG. 6. A third spacer layer 90 is then selectively
deposited over the second spacer layer portions 70a of the unmasked
spacer 50c using the selective deposition process described above,
i.e., treating the substrate with a plasma to generate dangling
bonds on the surface of the second spacer layer portions 70a of the
unmasked spacer 50c; forming the third spacer layer 90 over the
substrate using PVD or CVD; removing the weakly bonded portions 90b
of the third spacer layer 90 using a wet bench, and removing the
third mask layer 80, thereby leaving the spacer 50c enlarged by the
firmly bonded third spacer layer portions 90a to a width of W3 as
illustrated in FIG. 7.
[0017] The plasma treatment may be performed using conventional CVD
processing equipment. The plasma used in this process may comprise
an NH.sub.3 or N.sub.2O plasma, depending upon the composition of
the spacer layer to be treated. For example, in one embodiment of
the invention where the first spacer layer is composed of
SiO.sub.2, an NH.sub.3 plasma may be used to generate Si--N
dangling bonds over the surface of the SiO.sub.2 first spacer
layer. The second spacer layer will then be formed by depositing
SiO.sub.2 over the plasma treated first spacer layer. The SiO.sub.2
deposition produces an oxygen-rich, silicon oxynitride (SiON) film
over the first spacer layer due to the Si--N dangling bonds, the
oxygen-rich SiON film forming the second spacer layer. The unwanted
portions of the second spacer layer formed over the other features
of the device, such as the gate electrodes (made of poly-silicon
for example) and the substrate (made of silicon for example), will
still be composed of SiO.sub.2 because these features do not have
dangling bonds. These unwanted SiO.sub.2 portions of the second
spacer layer are easily removed by solvent selectivity due to the
different materials.
[0018] If a third spacer layer is desired, the oxygen-rich SiON
film forming the second spacer layer may be treated with an
N.sub.2O plasma to generate Si--O dangling bonds over the surface
of the second spacer layer. Next, the third spacer layer will be
formed by depositing SiN over the second spacer layer. The SiN
deposition produces a nitrogen-rich, SiON film over the second
spacer layer, the nitrogen-rich SiON film forming the third spacer
layer. The unwanted portions of the third spacer layer formed over
the other features of the device are still composed of SiN. These
unwanted portions of the third spacer layer are easily removed by
solvent selectivity due to the different materials.
[0019] In a second embodiment of the invention where the first
spacer layer is composed of SiN, an N.sub.2O plasma may be used to
generate Si--O dangling bonds over the surface of the SiN first
spacer layer. The second spacer layer will then be formed by
depositing SiN over the plasma treated first spacer layer. The SiN
deposition produces an nitrogen-rich, silicon oxynitride (SiON)
film over the first spacer layer due to the Si--O dangling bonds,
the nitrogen-rich SiON film forming the second spacer layer. The
unwanted portions of the second spacer layer formed over the other
features of the device, such as the gate electrodes and the
substrate, will still be composed of SiN because these features do
not have dangling bonds. These unwanted SiN portions of the second
spacer layer are easily removed by solvent selectivity due to the
different materials.
[0020] If a third spacer layer is desired, the nitrogen-rich SiON
film forming the second spacer layer is treated with an NH.sub.3
plasma to generate Si--N dangling bonds over the surface of the
second spacer layer. Next, the third spacer layer will be formed by
depositing SiO.sub.2 over the second spacer layer. The SiO.sub.2
deposition produces an oxygen-rich, SiON film over the second
spacer layer, the oxygen-rich SiON film forming the third spacer
layer. The unwanted portions of the third spacer layer formed over
the other features of the device are still composed of SiO.sub.2.
These unwanted portions of the third spacer layer are easily
removed by solvent selectivity due to the different materials.
[0021] Spacers of increasing widths may be formed by repeating the
selective deposition process as many times as desired. The width of
a spacer formed in accordance with the present invention is
determined by the number of spacer layers used to form the
spacer.
[0022] The present invention addresses and solves the problems
associated with forming spacers of varying widths. Through
selective deposition to form spacers of varying width, damage to
the thin, dielectric gate insulating layer and substrate is
avoided.
[0023] While the foregoing invention has been described with
reference to the above embodiments, various modifications and
changes can be made without departing from the spirit of the
invention. Accordingly, all such modifications and changes are
considered to be within the scope of the appended claims.
* * * * *