U.S. patent application number 10/973228 was filed with the patent office on 2006-04-27 for nonplanar device with thinned lower body portion and method of fabrication.
Invention is credited to Justin K. Brask, Robert S. Chau, Brian Doyle, Thomas A. Letson, Uday Shah.
Application Number | 20060086977 10/973228 |
Document ID | / |
Family ID | 35735429 |
Filed Date | 2006-04-27 |
United States Patent
Application |
20060086977 |
Kind Code |
A1 |
Shah; Uday ; et al. |
April 27, 2006 |
Nonplanar device with thinned lower body portion and method of
fabrication
Abstract
A nonplanar semiconductor device having a semiconductor body
formed on an insulating layer of a substrate. The semiconductor
body has a top surface opposite a bottom surface formed on the
insulating layer and a pair of laterally opposite sidewalls wherein
the distance between the laterally opposite sidewalls at the top
surface is greater than at the bottom surface. A gate dielectric
layer is formed on the top surface of the semiconductor body and on
the sidewalls of the semiconductor body. A gate electrode is formed
on the gate dielectric layer on the top surface and sidewalls of
the semiconductor body. A pair of source/drain regions are formed
in the semiconductor body on opposite sides of the gate
electrode.
Inventors: |
Shah; Uday; (Portland,
OR) ; Doyle; Brian; (Portland, OR) ; Brask;
Justin K.; (Portland, OR) ; Chau; Robert S.;
(Beaverton, OR) ; Letson; Thomas A.; (Beaverton,
OR) |
Correspondence
Address: |
Michael A. Bernadicou;BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP
Seventh Floor
12400 Wilshire Boulevard
Lod Angeles
CA
90025
US
|
Family ID: |
35735429 |
Appl. No.: |
10/973228 |
Filed: |
October 25, 2004 |
Current U.S.
Class: |
257/347 ;
257/E29.137 |
Current CPC
Class: |
H01L 29/785 20130101;
H01L 21/823431 20130101; H01L 27/0886 20130101; H01L 29/7854
20130101; H01L 27/1211 20130101; H01L 29/42384 20130101; H01L
29/66795 20130101; H01L 21/845 20130101; Y10S 438/978 20130101;
H01L 29/7856 20130101; H01L 29/7853 20130101; H01L 2924/13067
20130101; H01L 29/66818 20130101 |
Class at
Publication: |
257/347 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 27/01 20060101 H01L027/01; H01L 31/0392 20060101
H01L031/0392 |
Claims
1. A semiconductor device comprising: a semiconductor body formed
on an insulating layer of a substrate, said semiconductor body
having a top surface opposite a bottom surface formed on said
insulating layer and a pair of laterally opposite sidewalls wherein
the distance between said laterally opposite sidewalls at said top
surface is greater than at said bottom surface; a gate dielectric
layer formed on said top surface of said semiconductor body and on
said sidewalls of said semiconductor body; a gate electrode formed
on said gate dielectric layer on said top surface and sidewalls of
said semiconductor body; and a pair of source/drain region formed
in said semiconductor body on opposite sides of said gate
electrode.
2. The semiconductor device of claim 1 wherein said distance
between said sidewalls at the bottom surface of said semiconductor
body is approximately 1/2 to 2/3 of the distance between the
sidewall on top surface of said semiconductor body.
3. The semiconductor device of claim 1 wherein the distance between
said sidewalls of said semiconductor body become smaller than at
the top surface at approximately the mid portion of said
semiconductor body.
4. The semiconductor device of claim 1 wherein the distance between
said sidewalls is uniform at the top portion of said semiconductor
body and becomes increasingly smaller towards the bottom portion of
said semiconductor body.
5. The semiconductor device of claim 1 wherein the distance between
said sidewall at the bottom portion of said semiconductor body is
made sufficiently small so as to improve the short channel effects
of said transistor.
6. The semiconductor device of claim 1 wherein the distance between
said laterally opposite sidewalls at said top surface of said
semiconductor body is approximately 30-20 nm.
7. The semiconductor device of claim 1 wherein the distance between
said laterally opposite sidewalls near at said bottom portion of
said semiconductor body is approximately 15-10 nm.
8. A semiconductor device comprising: a semiconductor body formed
on an insulating layer of a substrate, said semiconductor body
having a top surface opposite a bottom surface formed on said
insulating layer, and a pair of laterally opposite sidewalls
wherein said laterally opposite sidewalls have a facet such that
the bottom portion of said semiconductor body is thinner than the
top portion of said semiconductor body; a gate dielectric layer
formed on said top surface said semiconductor body and on said
sidewalls of said semiconductor body; a gate electrode formed on
said gate dielectric layer on said sidewalls of said semiconductor
body and on said top surface of said semiconductor body; and a pair
of source/drain regions formed in said semiconductor body on
opposite sides of said gate electrode.
9. The semiconductor device of claim 8 wherein said semiconductor
body comprises silicon.
10. The semiconductor device of claim 8 wherein the distance
between said sidewalls near the bottom surface of said
semiconductor body is approximately 50-66% of the distance between
said sidewalls at the top of said semiconductor body.
11. A method of forming a device comprising: forming a
semiconductor body on an insulating layer of a substrate, said
semiconductor body having a top surface opposite a bottom surface
formed on said insulating layer and a pair of laterally opposite
sidewalls wherein the distance between said laterally opposite
sidewalls is less at the bottom surface of said semiconductor body
than at the top surface of said semiconductor body; forming a gate
dielectric layer on said top surface of said semiconductor body and
on said sidewalls of said semiconductor body; forming a gate
electrode on said gate dielectric layer on said top surface of said
semiconductor body and adjacent to said gate dielectric layer on
said sidewalls of said semiconductor body; and forming a pair of
source/drain regions in said semiconductor body on opposite sides
of said gate electrode.
12. The method of claim 11 wherein the width at the bottom of said
semiconductor body is approximately 1/2 to 2/3 of the width at the
top of said semiconductor body.
13. The method of claim 11 wherein said distance between said
sidewalls is uniform at the top portion of said semiconductor body
and becomes increasingly smaller near the bottom portion of said
semiconductor body.
14. The method of claim 11 wherein the distance between said
sidewalls of said semiconductor body at the top surface is between
20-30 nm and wherein the distance between said laterally opposite
sidewalls near the bottom is between 10-15 nm.
15. A method of forming a transistor comprising: providing a
substrate having an oxide insulating layer formed thereon and a
semiconductor thin film formed on the oxide insulating layer;
etching said semiconductor film to form a semiconductor body having
a top surface opposite a bottom surface on said oxide insulating
film and a pair laterally opposite sidewalls; etching said
semiconductor body to reduce the distance between laterally
opposite sidewalls near the bottom of said semiconductor body
relative to the top of said semiconductor body; forming a gate
dielectric layer on the top surface and sidewalls of said
semiconductor body; forming a gate electrode on said gate
dielectric layer on the top of said semiconductor body and adjacent
to the gate dielectric layer on the sidewalls of said semiconductor
body; and forming a pair of source/drain regions in said
semiconductor body on opposite sides of said gate electrode.
16. The method of claim 15 wherein said etching of said
semiconductor film stops on said oxide insulating layer.
17. The method of claim 15 wherein said semiconductor body
comprises silicon and wherein said etching of said semiconductor
film is a dry etching process which utilizes a chemistry comprising
HBr/O2.
18. The method of claim 15 wherein the etching of said
semiconductor body reduces the distance between the laterally
opposite sidewalls near the bottom portion of said semiconductor
body without significantly etching the top portion of said
semiconductor body.
19. The method of claim 18 wherein said semiconductor body is
silicon and is etched by a dry etching process utilizing a
chemistry comprising HBr/O.sub.2.
20. The method of claim 18 wherein the power utilized during said
etching of said semiconductor body to reduce the thickness of the
bottom portion utilizes an RF bias between 50-70 watts.
21. The method of claim 18 wherein the etching process utilized to
reduce the distance between the sidewalls on the bottom portion of
said semiconductor body utilizes a total HBr/O.sub.2 gas flow
between 150-180 mL/min.
22. The method of claim 15 further comprising after etching said
semiconductor body to reduce the distance between laterally
opposite sidewalls of said semiconductor body near the bottom
portion, exposing said semiconductor body to a wet chemistry
comprising NHyOH.
23. The method claim 15 wherein said etching of said semiconductor
film to form said body utilizes a first process gas chemistry and a
first RF bias and said etching of said semiconductor body to reduce
the thickness of said bottom portion utilizes a second process gas
and a second RF bias wherein said second RF bias is less than said
first RF bias.
24. The method of claim 23 wherein said first process gas is the
same as said second process gas.
25. The method of claim 24 wherein said first and second process
gas comprises HBr/Ar/O.sub.2.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the field of semiconductor
devices and more particularly to a nonplanar tri-gate transistor
having a thinned lower body portion and method of fabrication.
[0003] 2. Discussion of Related Art
[0004] In order to increase the performance of modern integrated
circuits, such as microprocessors, silicon on insulator (SOI)
transistors have been proposed. Silicon on insulator (SOI)
transistors have an advantage in that they can be operated in a
fully depleted manner. Fully depleted transistors have an advantage
of ideal subthreshold gradients for optimized ON current/OFF
current ratios.
[0005] An example of a proposed SOI transistor which can be
operated in a fully depleted manner is a tri-gate transistor 100,
such as illustrated in FIG. 1. Tri-gate transistor 100 includes a
silicon body 104 formed on an insulating substrate 102 having a
buried oxide layer 103 formed on a monocrystalline silicon
substrate 105. A gate dielectric layer 106 is formed on the top and
sidewalls of the silicon body 104 as shown in FIG. 1. A gate
electrode 108 is formed on the gate dielectric layer and surrounds
the body 104 on three sides, essentially providing a transistor 100
having three gate electrodes (G.sub.1, G.sub.2, G.sub.3), one on
each of the sidewalls of the silicon body 104 and one on the top
surface of the silicon body 104. A source region 110 and a drain
region 112 are formed in the silicon body 104 on opposite sides of
the gate electrode 108 as shown in FIG. 1.
[0006] An advantage of the tri-gate transistor 100 is that it
exhibits good short channel effects (SCE). One reason tri-gate
transistor 100 achieves good short channel effects is that the
nonplanarity of the device places the gate electrode 108 in such a
way as to surround the active channel region. That is, in the
tri-gate device, the gate electrode 108 is in contact with three
sides of the channel region. Unfortunately, the fourth side, the
bottom part of the channel is isolated from the gate electrode by
the buried oxide layer 103 and thus is not under close gate
control.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is an illustration of a nonplanar or tri-gate
device.
[0008] FIGS. 2A and 2B illustrate a tri-gate or nonplanar device
with a thinned lower body portion in accordance with the present
invention.
[0009] FIG. 3A illustrates a nonplanar device having multiple
thinned lower body portions.
[0010] FIG. 3B is an illustration of a nonplanar device having a
thinned lower body portion and including sidewall spacers,
source/drain extensions and silicided source/drain regions.
[0011] FIGS. 4A-4H illustrate a method of forming a nonplanar
device with a thinned lower body portion in accordance with an
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0012] The present invention is a novel nonplanar device with a
thinned lower body portion and a method of fabrication. In the
following description, numerous specific details are set forth in
order to provide a thorough understanding of the present invention.
In other instances, well known semiconductor processes and
manufacturing techniques have not been described in particular
detail in order to not unnecessarily obscure the present
invention.
[0013] Embodiments of the present invention include a nonplanar or
tri-gate transistor having a semiconductor body which is wrapped
around on three sides by a gate dielectric layer and a gate
electrode. In embodiments of the present invention, the bottom
portion of the semiconductor body is made thinner than the top
portion of the semiconductor body. Making the bottom portion of the
semiconductor body thinner than the top portion increases the gate
control over the bottom portion of the body resulting in better
short channel effects. In an embodiment of the present invention, a
semiconductor film is etched into a semiconductor body utilizing a
dry etching process which utilizes a first process gas chemistry
and a first RF bias. After forming the semiconductor body, the
lower portion of the body is thinned utilizing the same etch
chemistry and equipment but utilizing a lower RF bias in order to
inwardly taper or facet the lower body portion.
[0014] FIGS. 2A and 2B illustrate a nonplanar or tri-gate device
200 having a semiconductor body with a thinned lower body portion.
FIG. 2A is an overhead/side view of transistor 200 while FIG. 2B is
an illustration of a cross-sectional view taken through the gate
electrode. Transistor 200 is formed on a substrate 202 and includes
a semiconductor body or fin 204. A gate dielectric layer 206 is
formed on the top surface 234 and sidewalls 230 and 232 of a
semiconductor body 204. A gate electrode 208 is formed on the gate
dielectric layer 206 and surrounds the semiconductor body or fin on
three sides. A source regions 210 and a drain region 212 are formed
in the semiconductor body on opposite sides of the gate electrode
208 as shown in FIG. 2A.
[0015] As is readily apparent from FIGS. 2A and 2B, the
semiconductor body 204 has a bottom portion 222 which is thinner
than the top portion 224. That is, the distance between the
sidewalls 230 and 232 is greater at the top surface 234 than at the
bottom surface 236. In an embodiment of the present invention,
sidewalls 230 and 232 of the top portion 224 are substantially
vertical and are spaced a uniform distance apart while the
sidewalls 230 and 232 of the bottom portion 222, are faceted or
inwardly tapered to reduce the distance between the sidewalls 230
and 232 in the bottom portion. In an embodiment of the present
invention, the distance between the sidewalls 230 and 232 near the
bottom surface is between 1/2 to 2/3 the distance between the
sidewalls 230 and 232 near the top surface 234. In an embodiment of
the present invention, the sidewalls 230 and 232 begin to taper
inwardly at approximately the midpoint of the height 238 of the
semiconductor body 204 (i.e., sidewalls start tapering inwardly at
the midpoint between the top surface 234 and bottom surface 236).
In an embodiment of the present invention, the distance between the
sidewalls 230 and 232 at the top surface 234 is between 20-30
nanometers while the distance between the sidewalls 230 and 232
near the bottom surface 236 is between 10-15 nanometers. In an
embodiment of the present invention, the bottom portion 222 of the
semiconductor body 204 is made sufficiently thin so that the gate
control of the bottom portion is made similar to the gate control
of the top portion. In an embodiment of the present invention, the
bottom portion 222 of the semiconductor body 204 is made
sufficiently thin relative to the top portion to improve the short
channel effects of transistor 200.
[0016] Additionally, as illustrated in FIGS. 5A-5D, other
semiconductor body profiles or shapes may be utilized to improve
the short channel effects (SCE) of the tri-gate or nonplanar
transistor 200. For example, as illustrated in FIG. 5A, the
semiconductor body 204 can have a pair of sidewalls 230 and 232
which continually taper inward from the top surface 234 to the
bottom surface 236. Additionally, in an embodiment of the present
invention, as illustrated in FIG. 5B the semiconductor body 204 can
have sidewalls 230 and 232 which continually taper inward from the
top surface to the bottom surface and reach the bottom surface 236
at a point or substantially at point 502. In yet another embodiment
of the present invention as illustrated in FIG. 5C, the
semiconductor body 204 can have a pair of sidewalls 230 and 232
which include an upper vertical portion 510 separated by uniform
distance, a middle inwardly tapered portion 512 and a lower portion
514 of vertical sidewalls separated by a second distance which is
less than the distance separating the top portion sidewalls 510. In
yet another embodiment of the present invention, the semiconductor
body can have an upper portion 224 where the sidewalls 230 and 232
are faceted or tapered inwardly and a bottom portion 222 where the
sidewalls 230 and 232 are vertical or substantially vertical. In
each of the example illustrated in FIGS. 5A-5D, the distance
between the sidewalls 230 and 232 of semiconductor body 204 on the
top surface is greater than the distance between the semiconductor
body on the bottom surface. In this way, the gate electrode 208 can
have better control of the semiconductor body at the bottom surface
and thereby improve the short channel effects of the device.
[0017] In an embodiment of the present invention, the tri-gate
transistor 200 is formed on an insulating substrate 202 which
includes a lower monocrystalline silicon substrate 250 upon which
is formed an insulating layer 252, such as a silicon dioxide film.
In an embodiment of the present invention, insulating layer 252 is
a buried oxide layer of an SOI substrate. The tri-gate transistor
200, however, can be formed on any well known insulating substrate,
such as substrates formed from silicon dioxide, nitrides, oxides,
and sapphires.
[0018] Semiconductor body 204 is formed on insulating layer 252 of
insulating substrate 202. Semiconductor body 204 can be formed on
any well known material, such as but not limited to silicon (Si),
germanium (Ge), silicon germanium (Si.sub.xGe.sub.y), gallium
arsenide (GaAs), InSb, GaP and GaSb. Semiconductor body 204 can be
formed of any well known material which can be reversely altered
from an insulating state to a conductive state by applying external
electrical controls. Semiconductor body 204 is ideally a single
crystalline film when best electrical performance of transistor 200
is desired. For example, semiconductor body 204 is a single
crystalline film when transistor 200 is used in higher performance
applications, such as high density circuit, such as a
microprocessor. Semiconductor body 204, however, can be a
polycrystalline film when transistor 200 is used in applications
requiring less stringent performance, such as liquid crystal
displays. Insulator 252 isolate semiconductor body 204 from the
monocrystalline silicon substrate 250. In an embodiment of the
present invention, semiconductor body 204 is a single crystalline
silicon film.
[0019] Gate dielectric layer 206 is formed on and around three
sides of semiconductor body 204 as shown in FIGS. 2A and 2B. Gate
dielectric layer 206 is formed on or adjacent to sidewall 230, on
the top surface 234 of body 204 and on or adjacent to sidewall 232
of body 204 as shown in FIGS. 2A and 2B. Gate dielectric layer 206
can be any well known gate dielectric layer. In an embodiment of
the present invention, the gate dielectric layer is a silicon
dioxide (SiO.sub.2), silicon oxynitride (SiO.sub.xN.sub.y) or a
silicon nitride (Si.sub.3N.sub.4) dielectric layer. In an
embodiment of the present invention, the gate dielectric layer 206
is a silicon oxynitride film formed to a thickness between 5-20
.ANG.. In an embodiment of the present invention, gate dielectric
layer 206 is a high k gate dielectric layer, such as a metal oxide
dielectric, such as but not limited to tantalum pentaoxide
(TaO.sub.5), titanium oxide (TiO.sub.2) and hafnium oxide (HfO).
Gate dielectric layer 206 can be other types of high k dielectric
layers, such as but not limited to PZT and BST.
[0020] Gate electrode 208 is formed on and around gate dielectric
layer 206 as shown in FIGS. 2A and 2B. Gate electrode 208 is formed
on or adjacent to gate dielectric layer 206 formed on sidewall 230
of semiconductor body 204 is formed on gate dielectric layer 206
formed on the top surface 234 of semiconductor body 204 and is
formed adjacent to or on gate dielectric layer 206 formed on
sidewall 232 of semiconductor body 204. Gate electrode 208 has a
pair of laterally opposite sidewalls 260 and 262 separated by a
distance which defines the gate length (Lg) 264 of transistor 200.
In an embodiment of the present invention, laterally opposite
sidewalls 260 and 262 of gate electrode 208 run in a direction
perpendicular to sidewalls 230 and 232 of semiconductor body
204.
[0021] Gate electrode 208 can be formed of any suitable gate
electrode material. In an embodiment of the present invention, gate
electrode 208 comprises a polycrystalline silicon film doped to a
concentration density between 1.times.10.sup.9 atoms/cm.sup.3 to
1.times.10.sup.20 atoms/cm.sup.3. In an embodiment of the present
invention, the gate electrode can be a metal gate electrode, such
as but not limited to tungsten, tantalum, titanium and their
nitrides. In an embodiment of the present invention, the gate
electrode is formed from a material having a midgap workfunction
between 4.5 to 4.8 eV. It is to be appreciated that gate electrode
208 need not necessarily be a single material and can be a
composite stack of thin films, such as but not limited to
polycrystalline silicon/metal electrode or metal/polycrystalline
silicon electrode.
[0022] Transistor 200 has a source region 210 and a drain region
212. Source region 210 and drain region 212 are formed in
semiconductor 204 on opposite sides of gate electrode 208 as shown
in FIG. 2A. Source region 210 and drain region 212 are formed to an
n type conductivity type when forming a NMOS transistor and are
formed to a p type conductivity when forming a PMOS device. In an
embodiment of the present invention, source region 210 and drain
region 212 have a doping concentration between 1.times.10.sup.9
atoms/cm.sup.3 to 1.times.10.sup.21 atoms/cm.sup.3. Source region
210 and drain region 212 can be formed of the uniform concentration
or can include subregions of different concentrations or dopant
profiles, such as tip regions (e.g., source/drain extensions) and
contact regions. In an embodiment of the present invention, when
transistor 200 is a symmetrical transistor, source region 210 and
drain region 212 have the same doping concentration and profile. In
an embodiment of the present invention, when transistor 200 is
formed as an asymmetrical transistor, then the doping concentration
profile of the source region 210 and drain region 212 may vary in
order to any particular electrical characteristics as well known in
the art. Source region 210 and drain region 212 can be collectively
referred to as a pair of source/drain regions.
[0023] The portion of semiconductor body 204 located between source
region 210 and drain region 212, defines the channel region 270 of
transistor 200. The channel region 270 can also be defined as the
area of the semiconductor body 204 surrounded by the gate electrode
208. At times however, the source/drain region may extend slightly
beneath the gate electrode through, for example, diffusion to
define a channel region slightly smaller than the gate electrode
length (Lg). In an embodiment of the present invention channel
region 270 is intrinsic or undoped monocrystalline silicon. In an
embodiment of the present invention, channel region 270 is doped
monocrystalline silicon. When channel region 270 is doped it is
typically doped to a conductivity level of between 1.times.10.sup.6
to 1.times.10.sup.9 atoms/cm.sup.3. In an embodiment of the present
invention, when the channel region is doped it is typically doped
to the opposite conductivity type of the source region 210 and the
drain region 212. For example, when the source and drain regions
are n type conductivity the channel region would be doped to p type
conductivity. Similarly, when the source and drain regions are p
type conductivity the channel region would be n type conductivity.
In this manner a tri-gate transistor 200 can be formed into either
a NMOS transistor or a PMOS transistor respectively. Channel region
270 can be uniformly doped or can be doped non-uniformly or with
differing concentrations to provide particular electrical and
performance characteristics. For example, channel regions 270 can
include well-known "halo" regions, if desired.
[0024] By providing a gate dielectric and a gate electrode which
surrounds the semiconductor body on three sides, the tri-gate
transistor is characterized in having three channels and three
gates, one gate and channel (G.sub.1) which extends between the
source and drain regions on side 230 of silicon body 204, a second
gate and channel (G.sub.2) which extends between the source and
drain regions on the top surface of silicon body 204, and a third
gate and channel (G.sub.3) which extends between the source and
drain regions on the sidewall of silicon body 204. The gate "width"
(Gw) of transistor 200 is the sum of the widths of the three
channel regions. That is, the gate width of transistor 200 is equal
to the length of sidewall 230 of silicon body 204, plus the length
of top surface 234 of silicon body of 204, plus the length of
sidewall 232 of silicon body 204. Larger "width" transistors can be
obtained by using multiple devices coupled together (e.g., multiple
silicon bodies 204 surrounded by a single gate electrode 208) as
illustrated in FIG. 3A.
[0025] Because the channel region 270 is surrounded on three sides
by gate electrode 208 and gate dielectric 206, transistor 200 can
be operated in a fully depleted manner wherein when transistor 200
is turned "on" the channel region 270 fully depletes thereby
providing the advantageous electrical characteristics and
performance of a fully depleted transistor. That is, when
transistor 200 is turned "ON" a depletion region is formed in
channel region 270 along with an inversion layer at the surfaces of
region 270 (i.e., an inversion layer is formed on the side surfaces
and top surface of the semiconductor body). The inversion layer has
the same conductivity type as the source and drain regions and
forms a conductive channel between the source and drain regions to
allow current to flow therebetween. The depletion region depletes
free carriers from beneath the inversion layer. The depletion
region extends to the bottom of channel region 270, thus the
transistor can be said to be a "fully depleted" transistor. In
embodiments of the present invention, the lower portion 222 of the
semiconductor body 204 has been thinned relative to the upper
portion so that the gate electrode can better control the lower
portion of the semiconductor body. By thinning the lower portion,
the two sidewall gates G.sub.1 and G.sub.3 can more easily deplete
free carriers from beneath the inversion layer formed on the
sidewalls of the lower portion of the semiconductor body 204. By
thinning the lower portion 222 of semiconductor body 204, the two
gates G.sub.1 and G.sub.3 from the sidewall can control the channel
region in a manner similar to the way the three gates G.sub.1,
G.sub.2 and G.sub.3 control the channel in the upper portion 224 of
the semiconductor body 204. Thinning the bottom part of the body or
fin not only decreases the thickness of a semiconductor between the
two gates, but also decreases the width of that part of the body
which is in contact with the buried oxide. These effects combined
decrease the short channel effects in the tri-gate device having a
thinned lower body portion.
[0026] Transistor 200 of the present invention, can be said to be
an nonplanar transistor because the inversion layer of channel 270
is formed in both the horizontal and vertical directions in
semiconductor body 204. The semiconductor device of the present
invention, can also be considered to be a nonplanar device because
the electric field from gate electrode 208 is applied from both
horizontal (G.sub.2) and vertical sides (G.sub.1 and G.sub.3).
[0027] As stated above the gate width of transistor 200 is equal to
the sum of the three gate widths created from semiconductor body
204 of transistor 200. In order to fabricate transistors with
larger gate widths, transistor 200 can include additional or
multiple semiconductor bodies or fins 204 as illustrated in FIG.
3A. Each semiconductor body or fin 204 has a gate dielectric layer
206 formed on its top surface and sidewalls as shown in FIG. 3A.
Gate electrode 208 is formed on and adjacent to each gate
dielectric layer 206 on each semiconductor body 204. Each
semiconductor body 204 includes a source region 210 and drain
region 212 formed in the semiconductor body 204 on opposite sides
of gate electrode 208 as shown in FIG. 3A. In an embodiment of the
present invention, each semiconductor body 208 is formed with same
width and height (thickness) as other semiconductor bodies 204. In
an embodiment of the present invention, each source region 210 and
drain region 212 of the semiconductor bodies 204 are electrically
coupled together by semiconductor material used to form
semiconductor body 204 to form a source landing pad 310 and a drain
landing pad 312 as shown in FIG. 3A. Alternatively, the source
regions 210 and drain regions 212 can be coupled together by higher
levels of metallization (e.g., metal 1, metal 2, metal 3) used to
electrically interconnect various transistors 200 together in the
functional circuits. The gate width of transistor 200 as shown in
FIG. 3A would be equal to the sum of the gate width created by each
of the semiconductor bodies 204. In this way, a nonplanar or
tri-gate transistor 200 can be formed with any gate width desired.
In an embodiment of the present invention, each of the
semiconductor bodies 204 include a bottom portion 222 which is
thinner than the top portion 224 as described above.
[0028] In an embodiment of the present invention, the source 210
and drain 212 can include a silicon or other semiconductor film 350
formed on and around semiconductor body 204 as shown in FIG. 3B.
For example, semiconductor film 350 can be a silicon film or
silicon alloy, such as silicon germanium (Si.sub.xGe.sub.y). In an
embodiment of the present invention, the semiconductor film 350 is
a single crystalline silicon film formed of the same conductivity
type as a source region 210 and drain region 212. In an embodiment
of the present invention, the semiconductor film can be a silicon
alloy, such as silicon germanium where silicon comprises
approximately 1-99 atomic percent of the alloy. The semiconductor
film 350 need not necessarily be a single crystalline semiconductor
film and in embodiment can be a polycrystalline film. In an
embodiment of the present invention, semiconductor film 350 is
formed on the source region 210 and the drain region 212 of
semiconductor body 204 to form "raised" source and drain regions.
Semiconductor film 350 can be electrically isolated from a gate
electrode 208 by a pair of dielectric sidewalls spacers 360, such
as silicon nitride or silicon oxide or composites thereof. Sidewall
spacers 360 run along laterally opposite sidewalls 260 and 262 of
gate electrode 208 as shown in FIG. 3B thereby isolating the
semiconductor film 350 from the gate electrode 208. In an
embodiment of the present invention, sidewall spacer 360 have a
thickness of between 20-200 .ANG.. By adding a silicon or
semiconductor film of the source and drain regions 210 and 212 of
the semiconductor body and forming "raised" source and drain
regions, the thickness of the source and drain regions is increased
thereby reducing the source/drain contact resistance to transistor
200 improving its electrical characteristics and performance.
[0029] In an embodiment of the present invention, a silicide film
370, such as but not limited to titanium silicide, nickel silicide,
cobalt silicide is formed on the source region 210 and drain region
212. In an embodiment of the present invention, silicide 370 is
formed on silicon film 350 on semiconductor body 204 as shown in
FIG. 3B. Silicide film 370, however, can be formed directly onto
silicon body 204, if desired. Dielectric spacers 360 enables
silicide 370 to be formed on semiconductor body 204 or silicon film
250 in a self-aligned process (i.e., a salicide process).
[0030] In an embodiment of the present invention, if desired, the
silicon film 350 and/or the silicide film 370 can also be formed on
the top of gate electrode 208 when gate electrode 208 is a silicon
or silicon germanium film. The formation of silicon film 350 and
silicide film 370 on the gate electrode 208 reduces the contact
resistance of the gate electrode thereby improving the electrical
performance of transistor 200.
[0031] FIGS. 4A-4H illustrate a method of forming a nonplanar
transistor having a thinned lower body portion. The fabrication of
the transistor begins with substrate 402. A silicon or
semiconductor film 408 is formed on substrate 402 as shown in FIG.
4A. In an embodiment of the present invention, the substrate 402 is
an insulating substrate, such as shown in FIG. 4A. In an embodiment
of the present invention, insulating substrate 402 includes a lower
monocrystalline silicon substrate 404 and a top insulating layer
406, such as a silicon dioxide film or silicon nitride film.
Insulating layer 406 isolates semiconductor film 408 from substrate
404, and in embodiment is formed to a thickness between 200-2000
.ANG.. Insulating layer 406 is sometimes referred to as a "buried
oxide" layer. When a silicon or semiconductor film 408 is formed on
an insulating substrate 402, a silicon or semiconductor on
insulating (SOI) substrate is created.
[0032] Although semiconductor film 408 is ideally a silicon film,
in other embodiments it can be other types of semiconductor films,
such as but not limited to germanium (Ge), a silicon germanium
alloy (Si.sub.xGe.sub.y), gallium arsenide (GaAs), InSb, GaP and
GaSb. In an embodiment of the present invention, semiconductor film
408 is an intrinsic (i.e., undoped) silicon film. In other
embodiments, semiconductor film 408 is doped to a p type or n type
conductivity with a concentration level between
1.times.10.sup.16-1.times.10.sup.19 atoms/cm.sup.3. Semiconductor
film 408 can be insitu doped (i.e., doped while it is deposited) or
doped after it is formed on substrate 402 by for example
ion-implantation. Doping after formation enables both PMOS and NMOS
tri-gate devices to be fabricated easily on the same insulating
substrate. The doping level of the semiconductor body at this point
can be used to set the doping level of the channel region of the
device.
[0033] Semiconductor film 408 is formed to a thickness which is
approximately equal to the height desired for the subsequently
formed semiconductor body or bodies of the fabricated tri-gate
transistor. In an embodiment of the present invention,
semiconductor film 408 has a thickness or height 409 of less than
30 nanometers and ideally less than 20 nanometers. In an embodiment
of the present invention, semiconductor film 408 is formed to the
thickness approximately equal to the gate "length" desired of the
fabricated tri-gate transistor. In an embodiment of the present
invention, semiconductor film 408 is formed thicker than desired
gate length of the device. In an embodiment of the present
invention, semiconductor film 480 is formed to a thickness which
will enable the fabricated tri-gate transistor to be operated in a
fully depleted manner for its designed gate length (Lg).
[0034] Semiconductor film 408 can be formed on insulating substrate
402 in any well-known method. In one method of forming a silicon on
insulator substrate, known as the SIMOX technique, oxygen atoms are
implanted at a high dose into a single crystalline silicon
substrate and then anneal to form the buried oxide 406 within the
substrate. The portion of the single crystalline silicon substrate
above the buried oxide becomes the silicon film 408. Another
technique currently used to form SOI substrates is an epitaxial
silicon film transfer technique which is generally referred to as
bonded SOI. In this technique a first silicon wafer has a thin
oxide grown on its surface that will later serve as the buried
oxide 406 in the SOI structure. Next, a high dose hydrogen implant
is made into the first silicon wafer to form a high stress region
below the silicon surface of the first wafer. This first wafer is
then flipped over and bonded to the surface of a second silicon
wafer. The first wafer is then cleaved along the high stress plain
created by the hydrogen implant. This results in a SOI structure
with a thin silicon layer on top, the buried oxide underneath all
on top of the single crystalline silicon substrate. Well-known
smoothing techniques, such as HCl smoothing or chemical mechanical
polishing (CMP) can be used to smooth the top surface of
semiconductor film 408 to its desired thickness.
[0035] At this time, if desired, isolation regions (not shown) can
be formed into SOI substrate in order to isolate the various
transistors to be formed therein from one another. Isolation
regions can be formed by etching away portions of the substrate
film 408 surrounding a tri-gate transistor, by for example
well-known photolithographic and etching techniques, and then back
filling the etched regions with an insulating film, such as
SiO.sub.2.
[0036] In an embodiment of the present invention, a hard mask
material 410 formed on semiconductor film 408 as shown in FIG. 4A.
Hard mask material 410 is a material which can provide a hard mask
for the etching of the semiconductor film 408. A hard mask material
is a material which can retain its profile during etching of the
semiconductor film 408. A hard mask material 410 is a material
which will not etch or only slightly etch during the etching of
semiconductor film 408. In an embodiment of the present invention,
the hard mask material is formed of a material such that the
etchant used to etch the semiconductor film 408 will etch thin film
408 at least five times faster than the hard mask material and
ideally at least ten times faster. In an embodiment of the present
invention, when semiconductor film 408 is a silicon film, the hard
mask material 410 can be a silicon nitride or silicon oxynitride
film. Hard mask material 410 is formed to a thickness sufficient to
retain its profile during the entire etch of semiconductor film 408
but not too thick to cause difficulty in its patterning. In an
embodiment of the present invention, the hard mask material 410 is
formed to a thickness between 3 nanometers to 20 nanometers and
ideally to a thickness less than 10 nanometers.
[0037] Next, as also shown in FIG. 4A, a photoresist mask 412 is
formed on hard mask layer 410. Photoresist mask 412 contains a
feature pattern to be transferred into the semiconductor film 408.
The photoresist mask 412 can be formed by any well known
techniques, such as by blanket depositing a photoresist material by
masking, exposing and developing the photoresist film into a
photoresist mask 412 having a desired pattern for the semiconductor
film 408 to be patterned. Photoresist mask 412 is typically formed
of an organic compound. Photoresist mask 412 is formed to a
thickness sufficient to retain its profile while patterning the
hard mask film 410 but yet is not formed to thick to prevent
lithographic patterning into the smallest dimensions (i.e.,
critical dimensions) possible with photolithography system and
process used.
[0038] Next, as shown in FIG. 4B, the hard mask material 410 is
etched in alignment with photoresist mask 412 to form a hard mask
414 as shown in FIG. 4B. Photoresist mask 412 prevents the
underlying portion of hard mask material 410 from becoming etched.
In an embodiment of the present invention, the hard mask is etched
with an etchant which can etch the hard mask material but does not
etch the underlying semiconductor film 208. The hard mask material
is etched with an etchant that has almost perfect selectivity to
the underlying semiconductor film 208. That is, in an embodiment of
the present invention, the hard mask etchant etches the hard mask
material at least one hundred times faster than the underlying
semiconductor film 208 (i.e., an etchant has a hard mask to
semiconductor film selectivity of at least 50:1). When the hard
mask material 414 is a silicon nitride or silicon oxynitride film,
hard mask material 410 can be etched into a hard mask 414 utilizing
a dry etch process, such as a reactive ion etching/ecr plasma
etching. In an embodiment of the present invention, a silicon
nitride or silicon oxynitride hard mask is reactive ion etched
utilizing chemistry comprising CHF.sub.3 and O.sub.2 and
Ar/CH.sub.2F.sub.2 and C.sub.4F.sub.8 and Ar and O.sub.2.
[0039] Next, as shown in FIG. 4C, after hard mask film 410 has been
patterned into a hard mask 414, photoresist mask 412 can be removed
by well known techniques. For example, photoresist mask 412 can be
removed utilizing a "piranha" clean solution which includes
sulfuric acid and hydrogen peroxide. Additionally, residue from
photoresist mask 412 can be removed with an O.sub.2 ashing.
[0040] Although not required, it is desirable to remove photoresist
mask 412 prior to etching semiconductor film 408 so that a polymer
film from the photoresist does not form on the sidewalls of the
patterned semiconductor film 408. It is desirable to first remove
the photoresist mask 412 prior to etching of the semiconductor film
408 because dry etching processes can erode the photoresist mask
and cause a polymer film to develop on the sidewalls of the
semiconductor body which can be hard to remove and which can
detrimentally device performance. By first removing the photoresist
film 412 prior to patterning the semiconductor thin film 408, the
semiconductor thin film 408 can be patterned and pristine sidewalls
maintained.
[0041] Next, as shown in FIG. 4D, semiconductor film 408 is etched
in alignment with hard mask 414 to form a semiconductor body 416
having a pair of laterally opposite sidewalls 418 and 420. Hard
mask 414 prevents the underlying portion of semiconductor film 208
from becoming etched during the etching process. The etch is
continued until the underlying insulating substrate is reached. In
an embodiment of the present invention, the etch "end points" on
the buried oxide layer 406. Semiconductor film 208 etched with an
etchant which etches semiconductor 208 without significantly
etching hard mask 414. In an embodiment of the present invention,
semiconductor film 408 is anisotropically etched so that
semiconductor body 416 has nearly vertical sidewalls 418 and 420
formed in alignment with the sidewalls of hard mask 414 thereby
providing an almost perfect fidelity with hard mask 414. When hard
mask 414 is a silicon nitride or silicon oxynitride hard mask and
semiconductor film 408 is a silicon film, silicon film 408 can be
etched utilizing a dry etch process comprising HBr/Ar/O.sub.2.
[0042] In an embodiment of the present invention, semiconductor
body 408 is etched utilizing an electron cyclotron residence (ECR)
plasma etcher. In an embodiment of the present invention, an ECR
plasma etcher using a chemistry comprising HBr/O.sub.2 with a
pressure between 0.2 to 0.8 pascal and the RF power of
approximately 120 watts is used to etch a silicon thin film 408
into a silicon body 416. Such an etch process produces a
substantially anisotropic etch to provide substantially vertical
sidewalls 418 and 420 as shown in FIG. 4D. Additionally, such an
etch has a high selectivity (approximately 20:1) to the buried
oxide layer 406 so that the buried oxide layer etches very little
and can be used as an etch stop and for end point detection. The
ability to end point detect is important to insure that all of the
semiconductor film clears from the buried oxide layer because the
thickness 409 of the thin film across the wafer may vary and the
etch rate of different width semiconductor bodies may also vary. In
an embodiment of the present invention, an RF bias of between
100-120 watts is used. The RF bias controls the electron energy in
the etch which in turn controls the anisotropic profile of the
etch.
[0043] Next, as shown in FIG. 4F, the semiconductor body 416 is
etched so as the reduce the distance between the sidewalls 418 and
420 in the lower portion of the semiconductor body 416. The etching
of a semiconductor body to thin the lower portion of the
semiconductor body can be referred to as the "profile" etch. In an
embodiment of the present invention, the profile etch is utilized
to inwardly taper or form facets 422 and 424 on the sidewalls 418
and 420 as illustrated in FIG. 4E. It is to be appreciated that in
other embodiments of the present invention, the profile etch can
thin the lower body portion as illustrated in FIGS. 5A-5D. In an
embodiment of the present invention, a plasma etch process which
produces an isotropic etch is utilized to reduce the distance
between the sidewalls in lower portion of the semiconductor body as
compared to the upper portion of the semiconductor body. In an
embodiment of the present invention, the same plasma etch equipment
and etch chemistry is used during the profile etch as is used
during the patterning of the semiconductor film 408 except that the
RF bias is decreased so that the vertical directionality of the
ions is reduced. In an embodiment of the present invention, when
semiconductor body 416 is a silicon body, the profile etch can be
accomplished utilizing an ECR plasma etcher with a chemistry
comprising HBr/O2 and a pressure between 0.2 to 0.8 pascal with an
RF bias between 50-70 watts.
[0044] Next, as also shown in FIG. 4F, the hard mask 414 is removed
from semiconductor body 416 having a thinned lower body portion. In
an embodiment of the present invention, when hard mask 414 is a
silicon nitride or silicon oxynitride film, a wet chemistry
comprising phosphoric acid and Di water can be used to remove the
hard mask. In an embodiment of the present invention, the hard mask
etch comprises between 80-90% phosphoric acid (by volume) and Di
water heated to a temperature between 150-170.degree. C. and
ideally to 160.degree. C. is used. Such an etchant will have an
almost perfect selectivity between the silicon nitride hard mask
214 and buried oxide layer 406.
[0045] Next, if desired, after removing hard mask 414 as
illustrated in FIG. 4F, semiconductor body 416 can be exposed to a
wet etchant to clean the body 416. In an embodiment of the present
invention, a silicon body 416 is exposed to a wet etchant
comprising ammonia hydroxide (NH.sub.4OH) to remove any line edge
roughness or pitting which may have developed during the patterning
of the silicon body 416. In an embodiment of the present invention,
a silicon body 416 is exposed for a period of time of between 30
seconds to 2 minutes to an etchant comprising between 0.1-1% of
ammonia hydroxide by volume at a temperature between 20-30 degrees
Celsius in order to provide a semiconductor body 416 with pristine
sidewalls 418 and 420.
[0046] Next, as illustrated in FIG. 4G, a gate dielectric layer 430
is formed on sidewalls 418 and 420 and the top surface of
semiconductor body 416. The gate dielectric layer can be a
deposited dielectric or a grown dielectric. In an embodiment of the
present invention, the gate dielectric layer 426 is a silicon
oxynitride dielectric film grown by a dry/wet oxidation process. In
an embodiment of the present invention, the silicon oxide film is
grown to a thickness between 5-15 .ANG.. In an embodiment of the
present invention, the gate dielectric layer 430 is a deposited
dielectric, such as but not limited to a high dielectric constant
film, such as a metal oxide dielectric, such as tantalum pentaoxide
(Ta.sub.2O.sub.5), titanium oxide (TiO.sub.2), hafnium oxide,
zirconium oxide, and aluminum oxide. Additionally, in an embodiment
of the present invention, gate dielectric layer 430 can be other
high k dielectric films, such as but limited to PZT and BST. Any
well known technique can be utilized to deposit a high k
dielectric, such as but not limited to chemical vapor deposition,
atomic layer deposition and sputtering.
[0047] Next, gate electrode 432 is formed on the gate dielectric
layer 430 formed on the top surface of semiconductor body 416 and
is formed on or adjacent to the gate dielectric layer 430 formed on
or adjacent to sidewalls 418 and 420 as shown in FIG. 4G. The gate
electrode 432 has a top surface opposite a bottom surface formed on
insulating layer 406 and has a pair of laterally opposite sidewalls
434 and 436 which define the gate length of the device. Gate
electrode 432 can be formed by blanket depositing a suitable gate
electrode material over the substrate and then patterning the gate
electrode material with well known photolithograph and etching
techniques to form a gate electrode 432 from the gate electrode
material. In an embodiment of the present invention, the gate
electrode material comprises polycrystalline silicon. In another
embodiment of the present invention, the gate electrode material
comprises a polycrystalline silicon germanium alloy. In yet other
embodiments of the present invention, the gate electrode material
can comprise a metal film, such as but not limited to tungsten,
tantalum and their nitrides. In an embodiment of the present
invention, the photolithography process used to find the gate
electrode 432 utilizes the minimum or smallest dimension
lithography process used to fabricate the nonplanar transistor
(that is, in an embodiment of the present invention, the gate
length (Lg) of the gate electrode 432 has a minimum feature
dimension of the transistor defined by photolithography). In an
embodiment of the present invention, the gate length is less than
or equal to 30 nanometers and ideally less than 20 nanometers. It
is to be appreciated that although the gate dielectric layer and
gate electrode, as illustrated in FIGS. 4G and 4H, are formed with
a "subtractive" process whereby undesired portions are etched away,
the gate electrode can be formed with a replacement gate process
whereby a sacrificial gate electrode is first formed, an interlayer
dielectric formed adjacent thereto, the sacrificial gate electrode
then removed to form an opening in which the gate electrode is then
formed as is well known in the art.
[0048] Next, as shown in FIG. 4H, a source region 440 and a drain
region 442 are then formed in the semiconductor body 416 on
opposite sides of gate electrode 432. For a PMOS transistor, the
semiconductor body are doped to a p type conductivity with a
concentration between 1.times.10.sup.21 to 1.times.10.sup.21
atoms/cm.sup.3. For an NMOS nonplanar transistor, the semiconductor
body 416 is doped with n type conductivity to a concentration
between 1.times.10.sup.20 to 1.times.10.sup.21 atmos/cm.sup.3 to
form the source/drain regions. In an embodiment of the present
invention, the source/drain regions can be formed by ion
implantation. In an embodiment of the present invention, the ion
implantation occurs in a vertical direction (i.e., a direction
perpendicular to the substrate) as shown in FIG. 4H. The gate
electrode 432 is a polysilicon gate electrode and can be doped
during the ion implantation process. The gate electrode 432 acts as
a mask to prevent the ion implantation step from doping the channel
region of the nonplanar transistor. Again, the channel region is a
portion of the semiconductor body 416 located beneath or surrounded
by the gate electrode 432. If the gate electrode 432 is a metal
electrode a dielectric hard mask can be used to block the doping
during ion implantation process. In other embodiments or other
methods, such as solid source diffusion may be used to dope the
semiconductor body to form the source and drain regions. In
embodiments of the present invention, the source/drain regions may
also include subregions, such as source/drain extensions and
source/drain contact regions. In such a case, the semiconductor
body 416 would be doped on either side of the gate electrode 432 to
form the source/drain extensions and then a pair of sidewall
spacers such as illustrated in FIG. 3B would be formed along the
sidewalls of the gate electrode and a second doping step utilized
to form heavily doped source/drain contact region as is well known
in the art. Additionally, if desired at this time, additional
silicon and/or silicide can be formed onto the semiconductor bodies
416 to form raised source/drain regions and reduce the contact
resistance of the device. This completes the fabrication of a
nonplanar device having a semiconductor body with a thinned lower
portion to improve device performance.
* * * * *