U.S. patent application number 11/205185 was filed with the patent office on 2006-02-16 for interconnect line selectively isolated from an underlying contact plug.
Invention is credited to John M. Drynan.
Application Number | 20060033123 11/205185 |
Document ID | / |
Family ID | 24385272 |
Filed Date | 2006-02-16 |
United States Patent
Application |
20060033123 |
Kind Code |
A1 |
Drynan; John M. |
February 16, 2006 |
Interconnect line selectively isolated from an underlying contact
plug
Abstract
The present invention relates to selectively electrically
connecting an electrical interconnect line, such as a bit line of a
memory cell, with an associated contact stud and electrically
isolating the interconnect line from other partially underlying
contact studs for other electrical features, such as capacitor
bottom electrodes. The interconnect line can be formed as initially
partially-connected to all contact studs, thereby allowing the
electrical features to be formed in closer proximity to one another
for higher levels of integration. In subsequent steps of
fabrication, the contact studs associated with memory cell features
other than the interconnect line can be isolated from the
interconnect line by the removal of a silicide cap, or the
selective etching of a portion of these contact studs, and the
formation of an insulating sidewall between the non-selected
contact stud and the interconnect line.
Inventors: |
Drynan; John M.; (Boise,
ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L Street, NW
Washington
DC
20037
US
|
Family ID: |
24385272 |
Appl. No.: |
11/205185 |
Filed: |
August 17, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10863203 |
Jun 9, 2004 |
6969882 |
|
|
11205185 |
Aug 17, 2005 |
|
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|
10214169 |
Aug 8, 2002 |
6781182 |
|
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10863203 |
Jun 9, 2004 |
|
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09595922 |
Jun 16, 2000 |
6511879 |
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10214169 |
Aug 8, 2002 |
|
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Current U.S.
Class: |
257/202 |
Current CPC
Class: |
H01L 27/10814 20130101;
H01L 2924/00 20130101; H01L 27/10888 20130101; H01L 21/76831
20130101; H01L 27/10897 20130101; H01L 2924/0002 20130101; H01L
21/76834 20130101; H01L 2924/0002 20130101; H01L 27/10885 20130101;
H01L 27/10855 20130101; H01L 23/481 20130101; H01L 21/76885
20130101 |
Class at
Publication: |
257/202 |
International
Class: |
H01L 27/10 20060101
H01L027/10 |
Claims
1-71. (canceled)
72. A processor-based system, comprising: a processor; and a memory
circuit connected to said processor, wherein said memory circuit
includes a memory device comprising: a first conductive stud and a
second conductive stud; a bit line over and in electrical contact
with said first conductive stud, wherein said bit line is overlying
a portion of said second conductive stud; and an insulating
material separating said bit line from said portion of said second
conductive stud, wherein said insulating material provides an
insulating sidewall within a contact opening to said second
conductive stud.
73. The processor-based system of claim 72 wherein said first
conductive stud has a silicide cap and said second contact stud
does not have a silicide cap.
74. The processor-based system of claim 72 wherein said sidewall
extends around said contact opening to said second conductive stud
and said contact opening is through an insulating layer which is
over and around said bit line.
75. The processor-based system of claim 72 wherein said contact
opening is filled with a conductive plug.
76. The processor-based system of claim 75 wherein said conductive
plug is a capacitor bottom electrode.
77. The processor-based system of claim 72 wherein said first and
second conductive studs are connected to respective source and
drain regions of a transistor.
78. The processor-based system of claim 77 wherein said first
conductive stud is between wordline gates and said second
conductive stud is between a wordline gate and an isolation
gate.
79. The processor-based system of claim 77 wherein said source and
drain regions are of an access transistor of a memory cell.
80. The processor-based system of claim 72 wherein said second
conductive stud is a capacitor stud of a memory cell.
81. An embedded-memory processor-based system, comprising: a
processor; and a memory circuit formed on a same integrated circuit
as said processor, wherein said memory circuit includes a memory
device comprising: a first conductive stud and a second conductive
stud; a bit line over and in electrical contact with said first
conductive stud, wherein said bit line is overlying a portion of
said second conductive stud; and an insulating material separating
said bit line from said second conductive stud, wherein said
insulating material forms a sidewall surrounding a plug to said
conductive stud.
82. The embedded-memory processor-based system of claim 81 wherein
said first conductive stud has a silicide cap and said second
contact stud does not have a silicide cap.
83. The embedded-memory processor-based system of claim 81 wherein
said sidewalls within a contact opening containing said plug,
wherein said contact opening is through an insulating layer which
is over and around said bit line.
84. The embedded-memory processor-based system of claim 81 wherein
said contact opening is filled with a conductive plug.
85. The embedded-memory processor-based system of claim 84 wherein
said conductive plug is a capacitor bottom electrode.
86. The embedded-memory processor-based system of claim 81 wherein
said first and second conductive studs are connected to respective
source and drain regions of a transistor.
87. The embedded-memory processor-based system of claim 86 wherein
said first conductive stud is between wordline gates and said
second conductive stud is between a wordline gate and an isolation
gate.
88. The embedded-memory processor-based system of claim 86 wherein
said source and drain regions are of an access transistor of a
memory cell.
89. The embedded-memory processor-based system of claim 81 wherein
said second conductive stud is a capacitor stud of a memory cell.
Description
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/863,203, filed Jun. 9, 2004, which is a divisional of
U.S. patent application Ser. No. 10/214,169, now U.S. Pat. No.
6,781,182, filed Aug. 8, 2002, which is a divisional of U.S. patent
application Ser. No. 09/595,922, now U.S. Pat. No. 6,511,879, filed
Jun. 16, 2000. The entirety of each of these applications and
patents is hereby incorporated by reference herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to a semiconductor device and a
method of manufacturing such a device, wherein signal lines (e.g.,
bit lines of a memory device, etc.) may be isolated from adjacent
electrical conductors.
[0004] 2. Discussion of the Related Art
[0005] Modern integrated circuit designers confront problems
related to the need for increasingly smaller size and higher levels
of integration. In the art of integrated circuit fabrication, and
particularly when dealing with modern memory circuits, circuit
manufacturers must design memory cells that are more densely
constructed such that the basic elements making up the cell are
closer together. This increasingly close proximity of the discrete
electrical features within a memory cell, such as dynamic random
access memory (DRAM) cells, becomes problematic in light of the
increasing potential for shorting between adjacent electrical
conductors. This shorting may cause a memory cell to function
improperly or not at all.
[0006] An additional concern in the manufacture of integrated
circuits is the increasing complexity and cost related to the
necessity for diminishing size of the memory devices. The desire to
utilize fewer stages of fabrication has led designers of memory
cells to strive to simultaneously perform, at a given stage of
fabrication, as many necessary steps as possible. An example of
this may be seen in the standard technology of fabricating
capacitor-over-bit-line (COB) type DRAM cells, which typically
employs a process wherein all contacts to the memory cell active
area are formed simultaneously. Thus, both bit line and capacitor
contacts to the semiconductor substrate are formed using a single
layering and etching step (utilizing material such as polysilicon),
which creates contact studs over which the additional features of
the memory cell are fabricated.
[0007] Specifically in a process such as described above, after the
contact studs are formed in the memory cell, a dielectric layer is
deposited and a bit line contact-hole pattern is lithographically
delineated and subsequently etched down to the top of the stud
corresponding to the bit line connection to the active area on the
substrate below. A plug is next formed within each contact-hole,
typically of doped polysilicon, and the conductive layers for the
bit lines (typically silicide, polycide, or tungsten-based
material) are deposited and subsequently delineated using
lithographic-etching techniques. An interlayer dielectric is next
deposited around the bit line and a capacitor contact-hole pattern
is lithographically delineated and etched down between the formed
bit lines to the tops of the studs corresponding to the capacitor
bottom electrode connections to the active area on the substrate
below. This fabrication step is completed when the capacitor
contact-holes are then plugged with doped polysilicon or another
conductor. Then the process of cell fabrication continues on to the
formation of the capacitor features.
[0008] This standard method of fabricating memory cells utilizes
the single-step forming of contact studs for both capacitors and
bit lines, and the forming of bit line contacts and bit lines.
Though this method is useful in reducing the steps required to form
contacts to active areas of a substrate, it is desirable that the
contacts, and subsequently the fully formed features, be located in
a more densely packed array. It is also desirable to have the
electrical features and interconnects, exemplified by bit line and
capacitor features, arranged in such a more densely packed array
without increasing the probability of shorting.
SUMMARY OF THE INVENTION
[0009] The present invention relates to integrated circuit
fabrication and more particularly to selectively electrically
connecting an electrical interconnect line with an associated
contact to an active area and electrically isolating the
interconnect line from other underlying contacts for other
electrical features.
[0010] More specifically, in this invention a first interconnect
line is formed over two underlying contact holes such that it is
electrically connected to a first polysilicon stud but is
electrically isolated from a second stud. The line is essentially
formed over the first stud and partially over the second stud, and
is thereafter electrically isolated from the second studs, thereby
allowing the electrical features to be formed in closer proximity
to one another for higher levels of integration.
[0011] The present invention also provides a method for efficiently
connecting interconnect lines to a plurality of selected contact
studs while maintaining electrical isolation from other
non-selected plugs.
[0012] The above-described and other advantages and features of the
invention will be more clearly understood from the following
detailed description which is provided in connection with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 and FIG. 2 show a semiconductor substrate with
contact studs formed between gate structures and connecting to
active areas within the substrate.
[0014] FIG. 3 and FIG. 4 show the structure depicted in FIG. 1 and
FIG. 2 at a subsequent stage of processing wherein caps have been
formed over the contact studs.
[0015] FIG. 5 and FIG. 6 show the structure depicted in FIG. 3 and
FIG. 4 at a subsequent stage of processing wherein at least one bit
line has been formed over selected contact studs and is thereby
connected to the underlying active areas.
[0016] FIG. 7 and FIG. 8 show the structure depicted in FIG. 5 and
FIG. 6 at a subsequent stage of processing wherein an insulating
layer has been deposited over the bit line and a capacitor hole has
been formed.
[0017] FIG. 9 and FIG. 10 show the structure depicted in FIG. 7 and
FIG. 8 at a subsequent stage of processing wherein caps have been
selectively removed from atop the contact studs.
[0018] FIG. 11 and FIG. 12 show the structure depicted in FIG. 9
and FIG. 10 at a subsequent stage of processing wherein a thin
dielectric layer has been formed over a bit line, a bit line
insulating layer, and inside a contact-hole.
[0019] FIG. 13 and FIG. 14 show the structure depicted in FIG. 11
and FIG. 12 at a subsequent stage of processing wherein a capacitor
hole has been re-etched leaving an insulating sidewall on the
inside of the contact-hole.
[0020] FIG. 15 and FIG. 16 show the structure depicted in FIG. 13
and FIG. 14 at a subsequent stage of processing wherein a
conductive plug has been formed inside the contact-hole.
[0021] FIG. 17 depicts a processor-based system including a
semiconductor device formed in accordance with the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0022] DRAM memory circuits are currently the most popular type of
memory circuits used as the main memory of processor-based systems.
Therefore, the invention will be discussed in connection with DRAM
memory circuits. However, the invention herein disclosed has
broader applicability and is not limited to DRAM memory circuits.
It may be used in any other type of memory circuit, such as an SRAM
(static random access memory), as well as in any other circuit in
which electrical contacts are formed in close proximity to, and
intended to be insulated from, other circuit devices.
[0023] Also, the terms "wafer" and "substrate" are used
interchangeably and are to be understood as including silicon,
silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)
technology, doped and undoped semiconductors, and other
semiconductor structures. Furthermore, references to a "wafer" or
"substrate" in the following description, do not exclude previous
processing steps utilized to form regions or junctions in or on the
base semiconductor structure or foundation.
[0024] No particular order is required for the method steps
described below, with the exception of those logically requiring
the results of prior steps. Accordingly, while many of the steps
discussed below are discussed as being performed in an exemplary
order, this order may be altered.
[0025] The present invention relates to a semiconductor device and
a method of fabricating the same whereby electrical features in
close proximity to one another may be electrically isolated,
thereby reducing the potential for undesirable shorting.
[0026] FIGS. 1 and 2 show a DRAM cell array at an early stage of
cell formation. FIG. 2 is a cross-section view of FIG. 1, through
line II. Active areas 12a and 12b are formed in a substrate 10.
Gate structures, including wordline gates 14 and dummy isolation
gates 16, are formed over the substrate by techniques known in the
art. Though not necessary to the invention herein disclosed, active
areas (e.g., source and drain areas 12a and 12b ) are typically
formed by an ion implantation into the silicon substrate, and the
gate structures 14, 16 are typically formed by depositing onto the
semiconductor substrate a thin gate oxide followed by a conductive
material such as polysilicon, then a lower resistance metal such as
tungsten or a silicide such as WSi or TiSi. The gate pattern is
etched into the multilayer structure down to the substrate to
produce wordline gates 14 and dummy gates 16, after which the
substrate is implanted with various dopants to form the active area
source and drain regions 12a, 12b, for transistors. A dielectric
sidewall spacer and cap (not shown) are also typically formed
around and over the gate stacks to aid in the implantation process
for transistor formation and to separate the gate from the contacts
required to connect the active areas on both sides of the gate. The
gates of access transistors of a DRAM cell are typically laid out
as a wordline gate 14, which is typically located between a bit
line contact and a capacitor contact, and the dummy isolation gate
16 is typically used to assist in certain self-aligned fabrication
processes.
[0027] As depicted in FIGS. 1 and 2, an insulating dielectric layer
18 (e.g., silicon dioxide or BPSG, etc.) is deposited over and
around the gate structures 14 and 16. Next, using standard
photolithography techniques, such as ion plasma dry etching
techniques, holes (not shown) for contact studs 22 are formed down
to the active areas 12a, 12b. This is followed by depositing
polycrystalline silicon by LPCVD (low pressure chemical vapor
deposition) utilizing silane and a dopant such as phosphine (for
N-type studs) to fill the holes to form the contact studs 22.
Excess polysilicon on top of the dielectric layer 18 is removed by
a dry etch-back, a wet etch-back, or CMP technique. Some of the
contact studs 22a, will form electrical contacts with the bit lines
26 (see FIG. 6), while other contact studs 22b will form electrical
contacts (see FIG. 16) for capacitor bottom electrodes; however all
contact studs 22a and 22b are formed simultaneously.
[0028] Referring to FIGS. 3 and 4 (FIG. 4 shows a cross-section
view of FIG. 3 through line IV), after the contact studs 22a, 22b
are formed, silicide caps 24 are formed over the tops of the
contact studs 22a, 22b. These silicide caps 24 are formed by
selective CVD-deposition of Ti to form TiSi.sub.2, or by using a
metal deposition, thermal reaction, unreacted metal removal
process, also commonly used to form TiSi.sub.2. The preferred
material utilized to form the silicide caps 24 includes any metals
in Groups IV, V, VI, VII, and VIII of the periodic table, with Ti,
Co, W, Mo, and Ni being the most common.
[0029] Due to the selective silicide formation, the contact stud
22a, 22b on which the silicide cap 24 is formed must be made of
silicon, either entirely or at least the portion near the top
thereof, in order to provide a silicon layer with which to react a
metal to form the silicide.
[0030] After the forming of the silicide caps 24, bit lines 26 are
next formed over selected contact studs 22a and associated silicide
cap 24 structures. The bit lines 26 are formed by depositing a
conductive layer over the silicide caps 24 and the insulating
dielectric layer 18, by any standard method known in the art such
as PVD or CVD deposition, and then etching the conductive layer to
form bit lines 26. As shown in FIG. 5, the bit lines 26 are not
straight. FIGS. 5 and 6 show the bit lines 26, which are delineated
from the deposited conductive layer and etched by standard
techniques in the art, for example by masking the bit line 26 using
any standard photolithography and dry-etching process (FIG. 6 shows
a cross-section of FIG. 5 though line VI). As a result, bit lines
26 are formed over some of the contact studs 22a and the associated
silicide caps 24 and partially overlying other contact studs 22b
and associated silicide caps 24. When the bit lines 26 are formed
by etching, the contact studs 22b intended to be contacts for the
lower capacitor electrodes are re-exposed.
[0031] After the formation of the bit lines 26, an interlayer
dielectric layer 28 is deposited over and around the bit lines 26.
There is no specific preferred material for this interlayer
dielectric other than those known in the art which can withstand
the selective silicide etch used in subsequent processing steps
(such as silicon nitride or BPSG, etc.). This interlayer dielectric
layer 28 is then patterned with photoresist and etched by ion
plasma dry etching, as shown in FIGS. 7 and 8 (FIG. 8 shows a
cross-section of FIG. 7 through line VIII), to form contact-holes
30 to the silicide caps 24 over the contact studs 22b. These
contact studs 22b are those not positioned directly beneath the now
formed bit lines 26, but may be in partial contact with the bit
lines 26, as shown by area 27 in FIG. 8.
[0032] Contact studs 22b, shown in FIG. 8, may be in partial
contact 27 with the overlying bit lines 26 due to possible overlap
of the bit lines 26 with the silicide caps 24 on contact studs 22b
caused during the bit line deposition and delineation (see FIG. 5
and 6) 22, resulting from the close proximity of these electrical
features.
[0033] This direct electrical connection 27 is next removed as
explained in connection with FIGS. 9 and 10 (FIG. 10 shows a
cross-section of FIG. 9 through line X). The exposed silicide caps
24 over contact studs 22b are selectively etched with a negligible
effect upon the surrounding structures. This selective etch is
accomplished by choosing an etch that can etch the silicide away
without significantly affecting the a bit line 26. For instance, if
the bit line is formed of tungsten and the silicide is TiSi.sub.2,
a dilute HF acid solution can remove the silicide without affecting
the tungsten bit line. A wet etch, and potentially even an
isotropic dry etch, may be used to remove the silicide caps 24 from
the contact studs 22b, portions of which may be below the bit lines
26, as shown in FIG. 10.
[0034] Now that any direct electrical connection between the bit
line 26 and the underlying contact stud 22b has been removed, these
two electrical features must be further insulated to ensure against
undesired potential shorting between them. As shown in FIGS. 11 and
12 (FIG. 12 shows a cross-section of FIG. 11 through line XII), a
thin dielectric layer 32 (such as SiO.sub.2 or Si.sub.3N.sub.4) is
deposited over the interlayer dielectric layer 28 and within the
contact-holes 30. This thin dielectric layer 32 is deposited using
a highly-conformal technique such as CVD to ensure adherence to the
interior sides of the contact-holes 30. A preferred material for
the thin dielectric layer 32 is silicon nitride.
[0035] As shown by FIGS. 13 and 14 (FIG. 14 shows a cross-section
of FIG. 13 through line XIV), the thin dielectric layer 32 is next
etched to re-expose the contact stud 22b and leave an insulating
sidewall 34 inside the contact-hole 30, thereby preventing
unintended electrical connection and shorting between the bit line
26 and the contact stud 22b, or with a conductive plug 36, which
will be deposited in the hole 30. The thin dielectric layer 32 may
be etched by any satisfactory method known in the art.
[0036] The contact-hole 30 is next filled with a conductive
material, such as doped polysilicon or metal, depending upon the
physical characteristics of the future overlying capacitor
(material, type, structure, etc.) to form a conductive plug 36 as
shown in FIGS. 15 and 16 (FIG. 16 shows a cross-section of FIG. 15
through line XVI). If the overlying capacitor is to be polysilicon
based (that is, having a polysilicon bottom electrode) then for
ease in manufacture the capacitor conductive plug 36 should also be
polysilicon. However, if the overlying capacitor is to be
metal-based (a bottom electrode consisting of a metal such as W,
TiN, Pt, Ru, Al, etc.) then the capacitor conductive plug 36 should
also be a metal.
[0037] After the formation of the conductive plug 36, standard
processing as known in the art may be used to complete the memory
device, including conventional capacitor formation and cell
metalization to form a completed memory cell.
[0038] In another embodiment, the invention may also be used if a
silicide cap is not provided over the contact studs 22a, 22b. In
such a configuration, the interconnect lines 26 are connected
directly to selected contact studs 22a and other non-selected
contact studs 22b are isolated from the interconnect lines by the
selective removal of an upper-portion of the non-selected contact
studs 22b, as opposed to the selective removal of the silicide caps
24 described above. The removed upper-portion of the contact studs
should generally conform in thickness to the similarly removed
silicide caps 24 described above with respect to FIG. 8 of the
first embodiment. After removal of the upper-portion of the
non-selected contact studs 22b, the structure shown in FIG. 10 is
attained and the subsequent processing described and illustrated
with respect to FIGS. 11 to 16 is carried out.
[0039] FIG. 17 illustrates a processor-based system (e.g., a
computer system), with which a memory having memory cells
constructed as described above may be used. The processor-based
system comprises a central processing unit (CPU) 102, a memory
circuit 104, and an input/output device (I/O) 100. The memory
circuit 104 contains a DRAM memory circuit including semiconductor
devices constructed in accordance with the present invention. Also,
the CPU 102 may itself be an integrated processor which utilizes
semiconductor devices constructed in accordance with the present
invention, and both the CPU 102 and the memory circuit 104 may be
integrated on a single chip.
[0040] Although the (COB) DRAM structure used in both the example
of the existing related art and in the invention described has a
particular layout and is of 6F.sup.2 design, this does not preclude
application of this invention to any other COB DRAM design, nor to
any other particular semiconductor device, so long as it is
necessary to electrically connect an interconnect line to one
particular underlying contact stud while electrically isolating it
from another closely positioned or partially underlying contact
stud. For other devices, this invention could be applied wherever
an interconnect line needs to be connected to one contact while
remaining isolated from an adjacent contact, especially when the
tight spacing between the contacts will not allow sufficient room
for routing of the line away from the contact to remain
isolated.
[0041] The above description and accompanying drawings are only
illustrative of exemplary embodiments, which can achieve the
features and advantages of the present invention. It is not
intended that the invention be limited to the embodiments shown and
described in detail herein. The invention can be modified to
incorporate any number of variations, alterations, substitutions or
equivalent arrangements not heretofore described, but which are
commensurate with the spirit and scope of the invention. The
invention is only limited by the scope of the following claims.
* * * * *