U.S. patent application number 11/234334 was filed with the patent office on 2006-01-26 for method of depositing polysilicon.
Invention is credited to Yongjun Jeff Hu, Michael Nuttall, Er-Xuan Ping.
Application Number | 20060019475 11/234334 |
Document ID | / |
Family ID | 25289115 |
Filed Date | 2006-01-26 |
United States Patent
Application |
20060019475 |
Kind Code |
A1 |
Nuttall; Michael ; et
al. |
January 26, 2006 |
Method of depositing polysilicon
Abstract
A method of depositing polysilicon includes positioning a
substrate within a chemical vapor deposition reactor. The substrate
has an exposed substantially crystalline region and an exposed
substantially amorphous region. A gaseous precursor comprising
silicon is fed to the chemical vapor deposition reactor to provide
a reactive atmosphere under conditions effective to substantially
selectively deposit polysilicon on the crystalline region relative
to the amorphous region. The reactive atmosphere during the
depositing consists essentially of a gaseous silane precursor.
Inventors: |
Nuttall; Michael; (Meridian,
ID) ; Ping; Er-Xuan; (Boise, ID) ; Hu; Yongjun
Jeff; (Boise, ID) |
Correspondence
Address: |
WELLS ST. JOHN P.S.
601 W. FIRST AVENUE, SUITE 1300
SPOKANE
WA
99201
US
|
Family ID: |
25289115 |
Appl. No.: |
11/234334 |
Filed: |
September 23, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10863046 |
Jun 7, 2004 |
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11234334 |
Sep 23, 2005 |
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10050426 |
Jan 15, 2002 |
6797558 |
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10863046 |
Jun 7, 2004 |
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09843116 |
Apr 24, 2001 |
6458699 |
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10050426 |
Jan 15, 2002 |
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09429236 |
Oct 28, 1999 |
6509239 |
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09843116 |
Apr 24, 2001 |
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09023239 |
Feb 13, 1998 |
6159852 |
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09429236 |
Oct 28, 1999 |
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Current U.S.
Class: |
438/488 ;
257/E21.166; 257/E21.171; 257/E21.295; 257/E21.586; 257/E29.267;
438/674; 438/684 |
Current CPC
Class: |
H01L 21/76879 20130101;
C23C 16/24 20130101; C23C 16/04 20130101; H01L 28/60 20130101; H01L
21/31604 20130101; H01L 29/41775 20130101; H01L 21/28525 20130101;
H01L 29/7834 20130101; H01L 21/32051 20130101; H01L 29/41783
20130101; H01L 21/28562 20130101 |
Class at
Publication: |
438/488 ;
438/684; 438/674 |
International
Class: |
H01L 21/20 20060101
H01L021/20 |
Claims
1-64. (canceled)
65. A method of depositing polysilicon comprising: positioning a
substrate within a chemical vapor deposition reactor, the substrate
having an exposed substantially crystalline region and an exposed
substantially amorphous region; and; feeding a gaseous precursor
comprising silicon to the chemical vapor deposition reactor to
provide a reactive atmosphere under conditions effective to
substantially selectively deposit polysilicon on the crystalline
region relative to the amorphous region, the reactive atmosphere
during the depositing consisting essentially of a gaseous silane
precursor.
66. The method of claim 65 wherein the conditions are void of
plasma.
67. The method of claim 65 wherein the conditions include a time
period effective to deposit no more than about 1500 Angstroms of
polysilicon on the crystalline region.
68. The method of claim 65 wherein the conditions include a time
period effective to deposit no more than about 1000 Angstroms of
polysilicon on the crystalline region.
69. The method of claim 65 wherein the conditions comprise a
pressure greater than 30 mTorr.
70. The method of claim 65 wherein the conditions comprise a
pressure greater than 30 mTorr and a temperature of less than
800.degree. C.
71. The method of claim 65 wherein the conditions are void of
feeding chlorine-containing gas to the reactor.
72. The method of claim 65 wherein the silane comprises a
chlorosilane.
73. The method of claim 65 wherein the conditions comprise a
temperature of from about 650.degree. C. to about 850.degree. C.
and a reactor pressure at less than or equal to about 100
mTorr.
74. The method of claim 65 wherein the substantially amorphous
region comprises SiO.sub.2.
75. The method of claim 65 wherein the substantially amorphous
region comprises Si.sub.3N.sub.4.
76. The method of claim 65 wherein the conditions comprise a
temperature of greater than or equal to about 650.degree. C.
Description
RELATED PATENT DATA
[0001] This patent resulted from a continuation application of U.S.
patent application Ser. No. 10/863,046, filed on Jun. 7, 2004,
entitled "Methods of Forming Capacitors", naming Michael Nuttall,
Er-Xuan Ping and Yongjun Jeff Hu as inventors, the disclosure of
which is incorporated herein by reference; which resulted from a
divisional application of U.S. patent application Ser. No.
10/050,426, filed on Jan. 15, 2002, entitled "Methods of Forming a
Capacitor With Substantially Selective Deposit of Polysilicon on a
Substantially Crystalline Capacitor Dielectric Layer", naming
Michael Nuttall, Er-Xuan Ping, and Yongjun Jeff Hu as inventors,
now U.S. Pat. No. 6,797,558 B2, the disclosure of which is
incorporated herein by reference; which resulted from a divisional
application of U.S. patent application Ser. No. 09/843,116, filed
on Apr. 24, 2001, entitled "Methods of Forming a Contact to a
Substrate", naming Michael Nuttall, Er-Xuan Ping and Yongjun Jeff
Hu as inventors, now U.S. Pat. No. 6,458,699 B1, the disclosure of
which is incorporated herein by reference; which resulted from a
divisional application of U.S. patent application Ser. No.
09/429,236, filed on Oct. 28, 1999, entitled "Methods of
Fabricating a Field Effect Transistor on a Substrate, naming
Michael Nuttall, Er-Xuan Ping and Yongjun Jeff Hu as inventors, now
U.S. Pat. No. 6,509,239 B1, the disclosure of which is incorporated
herein by reference; which resulted from a divisional application
of U.S. patent application Ser. No. 09/023,239, filed on Feb. 13,
1998, entitled "Method of Depositing Polysilicon, Method of
Fabricating a Field Effect Transistor, Method of Forming a Contact
to a Substrate, Method of Forming a Capacitor", naming Michael
Nuttall, Er-Xuan Ping and Yongjun Jeff Hu as inventors, U.S. Pat.
No. 6,159,852; the disclosure of which is incorporated herein by
reference.
TECHNICAL FIELD
[0002] This invention relates to methods of depositing polysilicon,
to methods of fabricating field effect transistors, to methods of
forming contacts to substrates and to methods of forming
capacitors.
BACKGROUND OF THE INVENTION
[0003] Device geometry continues to shrink in semiconductor
circuitry fabrication. For example, field effect transistor gate
width is now commonly below one micron and source/drain junction
depth 1000 Angstroms or less. A challenge in such constructions is
to reduce parasitic source/drain serial resistance while
maintaining low source/drain diode leakage. Such resistance can be
reduced by providing a thicker silicide over the source/drain. Such
is typically provided by depositing a metal layer on the
source/drain which typically comprises monocrystalline silicon. A
subsequent anneal causes a reaction which consumes a portion of the
silicon to form the silicide. However, large consumption of silicon
to form the desired thicker silicide results in the
silicide/junction interface being very close to the base of the
junction. This causes source/drain diode leakage current to the
substrate to increase.
[0004] Raised or elevated source/drain constructions in field
effect transistors can be utilized to minimize or reduce the amount
of silicon consumed in forming a silicide portion of a substrate
contact. Further, raised source/drain constructions can provide
desired field effect transistor constructions independent of the
silicide contact which is typically formed. For example, raised
source/drain transistors are commonly used in logic device
applications where device speed is an important factor.
[0005] Elevated source/drain constructions are typically formed in
the prior art by selectively growing epitaxial monocrystalline
silicon atop the silicon junction regions. Such is typically
accomplished in costly epitaxial reactors operating under ultra
high vacuum (UHV), for example at vacuum pressures of the order of
0.001 mTorr. Violette et al., "Low temperature selective silicon
epitaxy by ultra high vacuum rapid thermal chemical vapor
deposition using Si.sub.2H.sub.6, H.sub.2 and Cl.sub.2", Applied
Physics Letter 68(1), pp. 66-68, Jan. 1, 1996 disclose a selective
epi silicon deposition process occurring at 800.degree. C. and 30
mTorr or less.
[0006] It would be desirable to improve upon these and other prior
art processes of selectively forming silicon over silicon
substrates. Although motivated from this objective, the artisan
will appreciate other applicability of the disclosed technology,
with the invention only being limited by the accompanying claims
appropriately interpreted in accordance with the Doctrine Of
Equivalents.
SUMMARY OF THE INVENTION
[0007] In but one aspect of the invention, a method of depositing
polysilicon comprises providing a substrate within a chemical vapor
deposition reactor, with the substrate having an exposed
substantially crystalline region and an exposed substantially
amorphous region. A gaseous precursor comprising silicon is fed to
the chemical vapor deposition reactor under conditions effective to
substantially selectively deposit polysilicon on the crystalline
region and not the amorphous region.
[0008] In another aspect a method of fabricating a field effect
transistor on a substrate comprises forming a gate dielectric layer
and a gate over semiconductive material. Doped source/drain regions
are formed within semiconductive material laterally proximate the
gate. Substantially amorphous insulating material is formed over
and laterally proximate the gate. The substrate is provided within
a chemical vapor deposition reactor. A gaseous precursor comprising
silicon is fed to the chemical vapor deposition reactor under
conditions effective to substantially selectively deposit
polysilicon on the source/drain regions and not on substantially
amorphous material, and forming elevated source/drains on the doped
source/drain regions.
[0009] In but another aspect, a method of forming a contact to a
substrate comprises forming substantially amorphous insulating
material over a substrate node location. A contact opening is
etched through the amorphous insulating material over the node
location. The node location is provided to comprise an outwardly
exposed substantially crystalline surface. The substrate with
outwardly exposed substantially crystalline node location surface
is provided within a chemical vapor deposition reactor. A gaseous
precursor comprising silicon is fed to the chemical vapor
deposition reactor under conditions effective to substantially
selectively deposit polysilicon on the outwardly exposed
crystalline node location surface and not on the insulating
material.
[0010] An aspect of the invention also comprises forming a
capacitor. In one implementation, a substrate is provided within a
chemical vapor deposition reactor. The substrate has an exposed
substantially crystalline region and an exposed substantially
amorphous region. A gaseous precursor comprising silicon is fed to
the chemical vapor deposition reactor under conditions effective to
substantially selectively deposit polysilicon on the crystalline
region and not the amorphous region, and the polysilicon is formed
into a first capacitor electrode. A capacitor dielectric layer is
formed over the polysilicon. A second capacitor electrode is formed
over the capacitor dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0012] FIG. 1 is a diagrammatic view of a semiconductor wafer
fragment at one process in accordance with the invention.
[0013] FIG. 2 is a view of the FIG. 1 wafer fragment at a
processing step subsequent to that depicted by FIG. 1.
[0014] FIG. 3 is an alternate view of the FIG. 1 wafer fragment at
an alternate processing step subsequent to that depicted by FIG.
1.
[0015] FIG. 4 is a diagrammatic view of an alternate embodiment
semiconductor wafer fragment at a processing step in accordance
with an aspect of the invention.
[0016] FIG. 5 is a view of the FIG. 4 wafer fragment at a
processing step subsequent to that shown by FIG. 4.
[0017] FIG. 6 is a diagrammatic sectional view of yet another
alternate embodiment wafer fragment at a processing step in
accordance with an aspect of the invention.
[0018] FIG. 7 is a diagrammatic sectional view of still another
alternate embodiment wafer fragment at a processing step in
accordance with an aspect of the invention.
[0019] FIG. 8 is a view of the FIG. 7 wafer fragment at a
processing step subsequent to that shown by FIG. 7.
[0020] FIG. 9 is yet another view of an alternate embodiment
semiconductor wafer fragment at a processing step in accordance
with an aspect of the invention.
[0021] FIG. 10 is a view of the FIG. 9 wafer fragment at a
processing step subsequent to that depicted by FIG. 9.
[0022] FIG. 11 is a view of the FIG. 9 wafer fragment at a
processing step subsequent to that depicted by FIG. 10.
[0023] FIG. 12 is a view of the FIG. 9 wafer fragment at a
processing step subsequent to that depicted by FIG. 11.
[0024] FIG. 13 is still another view of an alternate embodiment
semiconductor wafer fragment at a processing step in accordance
with an aspect of the invention.
[0025] FIG. 14 is a view of the FIG. 13 wafer fragment at a
processing step subsequent to that depicted by FIG. 13.
[0026] FIG. 15 is a view of the FIG. 13 wafer fragment at a
processing step subsequent to that depicted by FIG. 14.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0027] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0028] In the prior art, polysilicon is typically deposited by
chemical vapor deposition utilizing precursor gases, such as
silane. Typical deposition temperatures are from 500.degree. C. to
625.degree. C. at a pressure ranging from 50 mTorr to 1 Torr.
Deposition temperatures less than about 550.degree. C. result in an
amorphous deposition while deposition temperatures greater than
550.degree. C. result in a polycrystalline deposition. Regardless,
the deposition typically results in a uniform, conformal layer of
silicon atop the semiconductor substrate.
[0029] Referring to FIG. 1, a semiconductor wafer in process is
indicated generally with reference numeral 10. Such comprises, for
example, a bulk monocrystalline silicon substrate 12 having an
exposed insulating dielectric layer or region 14 associated
therewith, such as SiO.sub.2 or Si.sub.3N.sub.4. Monocrystalline
silicon 12 presents an exposed substantially crystalline region 16,
while all of the illustrated dielectric material 14 constitutes an
exposed substantially amorphous dielectric material region as
depicted in FIG. 1. In the context of this document, "substantially
crystalline" and "substantially amorphous" refer to the respective
attributes at greater than 90% of the exposed material at its
exposed surface. For example, an exposed substantially crystalline
region will have its exposed surface having at least 90%
crystallinity, while an exposed substantially amorphous region will
have its exposed surface being at least 90% amorphous. Also in the
context of this document, "predominately" means greater than
50%.
[0030] Further in the context of this document, the term
"semiconductive substrate" is defined to mean any construction
comprising semiconductive material, including, but not limited to,
bulk semiconductive materials such as a semiconductive wafer
(either alone or in assemblies comprising other materials thereon),
and semiconductive material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above.
[0031] Referring to FIG. 2, wafer 10 is provided within a chemical
vapor deposition reactor. Preferably, the wafer has been subjected
to a native oxide strip, such as by using an HF dip, immediately
prior to placement with the reactor. A gaseous precursor comprising
silicon is fed to the reactor under conditions effective to
substantially selectively deposit a polysilicon layer 18 on
crystalline region 16 and not on amorphous region 14. In the
context of this document, "substantially selective" or
"substantially selectively" denotes deposition over one region as
compared to another to a thickness ratio of greater than 5:1. An
example and preferred reactor is a hot wall low pressure chemical
vapor deposition reactor, with the processing conditions being void
of plasma generation. Alternately, plasma can be utilized.
Exemplary and suitable conditions within the reactor comprise a
temperature of greater than or equal to about 650.degree. C. and a
pressure less than or equal to about 100 mTorr. A preferred upper
temperature limit is 850.degree. C. Also preferably, pressure is
greater than 30 mTorr and temperature is less than 800.degree. C.
during deposition, thus overcoming the extreme low pressure/high
temperature environments (and thus costs associated therewith) of
the prior art epitaxial silicon deposition processes. Accordingly
in one implementation, the invention enables use of conventional,
lower cost deposition furnaces instead of the ultra high vacuum
rapid thermal epi reactors.
[0032] Example preferred silicon precursors include silanes,
including chlorosilanes. Specific examples include SiH.sub.4,
Si.sub.2H.sub.6, and SiCl.sub.2H.sub.2. However most preferably,
the deposition conditions are void of feeding chlorine containing
gas to the reactor thus eliminating any tendency of the substrate
being etched during the selective deposition. The invention was
reduced to practice utilizing a vertical hot wall LPCVD reactor
holding 100 wafers. The feed gas was SiH.sub.4 at 50 sccm, with the
atmosphere within the reactor during processing consisting entirely
or essentially of such gaseous silane precursor. Temperature during
processing was 700.degree. C., with pressure being substantially
maintained at 70 mTorr. An exemplary broader range for gas flow is
from about 20 sccm to about 1000 sccm. Under such conditions, near
100% selectivity in the deposition was achieved (i.e., essentially
no deposition over region 14) during deposition of the first 1500
Angstroms of polysilicon. Above this thickness, polysilicon began
to deposit on region 14, which comprised undoped SiO.sub.2.
Modifying process conditions by one or both of raising temperature
and lowering pressure will have greater improvement on selectivity
as a function of thickness. Regardless, such reduction-to-practice
example conditions in the subject reactor do have significant
utility, as present and future generations of semiconductor wafer
fabrication comprises deposition of polysilicon layers to less than
1000 Angstroms.
[0033] Alternate exposed crystalline surfaces, by way of example
only, utilizable in the context of the invention include silicides
(such as TiSi.sub.x and WSi.sub.4), crystalline dielectrics (such
as barium strontium titanate and Ta.sub.2O.sub.5), aluminum,
copper, aluminum-copper alloys, tungsten, and other crystalline
metals or metal-like materials. Selectivity in the deposition is
expected to be greatest where the reactor atmosphere during the
time period of deposition is substantially void of a gas comprising
a conductivity enhancing dopant, or other gases, although
conductivity enhancing gases (such as B.sub.2H.sub.6) are expected
to provide functional selectivity in accordance with the
invention.
[0034] An alternate considered embodiment is described with
reference to FIG. 3 which illustrates a semiconductor wafer
fragment 10a. Like numerals from the first described embodiment are
utilized where appropriate, with differences being indicated with
the suffix "a" or with different numerals. In this example,
materials 12a (and correspondingly exposed region 16a) and 14a can
be considered as presenting exposed predominately crystalline and
predominately amorphous regions, respectively. Such regions could
also constitute exposed substantially crystalline and substantially
amorphous regions, respectively. Within a chemical vapor deposition
reactor, a gaseous silicon precursor is fed under conditions
effective to deposit a polysilicon layer 18a on both the exposed
crystalline and amorphous regions. Polysilicon layer 18a has a
region 19 within the previously exposed at least predominately
crystalline region 16a and a region 20 over the exposed at least
predominately amorphous region. Deposited polysilicon region 19 has
a greater thickness than deposited polysilicon region 20. Region 20
can be subsequently removed if desired.
[0035] In accordance with the reduction to practice example, such
was achieved with a silane flow rate at 50 sccm with reactor
temperature and pressure during processing being maintained at
700.degree. C. and 70 mTorr, respectively, when the thickness of
region 18a reached about 1500 Angstroms. In such
reduction-to-practice example, exposed region 16a was substantially
crystalline and region 14a was substantially amorphous. Modifying
deposition conditions by one or both of lowering temperature and
raising pressure will result in lowering of the threshold thickness
upon which appreciable deposition begins relative to the exposed
amorphous region. Further, modifying crystalline/amorphous content
of the exposed surface(s) by reducing the degree of crystallinity
below 90% in region 16a and reducing amorphous content to below 90%
in region 14a would further impact by lowering the threshold
thickness limit where appreciable polysilicon begins to develop on
the exposed predominately amorphous region.
[0036] The invention can have applicability, for example, in
fabrication of field effect transistors, such as will now be
described with reference to FIGS. 4 and 5. FIG. 4 illustrates a
semiconductor wafer fragment 24 comprised of a bulk monocrystalline
silicon substrate 26 having isolation regions 28 formed therein.
Agate construction 30 is provided centrally between isolation
regions 28. Such comprises a gate dielectric layer 32 and a gate 34
provided thereover. Gate 34 preferably comprises a silicide layer
over a polysilicon layer. Substantially amorphous insulating
material, such as Si.sub.3N.sub.4 in the illustrated form of
anisotropically etched sidewall spacers 36 and cap 38, is provided
over and laterally proximate gate 34, with the illustrated gate
construction 30 being provided over semiconductive material 26.
Doped source/drain regions 40 and 42 are formed within
semiconductive material 26 laterally proximate the illustrated
gate.
[0037] Referring to FIG. 5, wafer 24 has been provided within a
chemical vapor deposition reactor and processed as described above
effectively to substantially selectively deposit polysilicon on
source/drain regions 40 and 42, and not on the substantially
amorphous material of regions 28, 36 and 38. Elevated source/drain
regions 44 and 46 are formed on doped source/drain regions 40 and
42, respectively. An example and preferred thickness for the
entirety of each region 40/44, and 42/46 is 500 Angstroms. As an
alternate example, doping to fully form regions 40 and 42 could
occur after provisions of elevated regions 44 and 46.
[0038] FIG. 6 illustrates exemplary alternate processing relative
to a wafer fragment 24a. Like numerals from the FIGS. 4 and 5
embodiment are utilized where appropriate, with differences being
indicated with a suffix "a", or with different numerals. Wafer
fragment 24a is the same as that depicted in FIG. 4, and
additionally includes formation of a substantially amorphous
insulating material layer 48 (for example such as SiO.sub.2, doped
or undoped, or Si.sub.3N.sub.4) thereover. Openings 50 and 52 have
been etched through amorphous insulating material layer 48 over the
illustrated source/drain regions to expose such regions, while
leaving the gate protectively covered with amorphous insulating
material. Processing would then continue as described above with
respect to FIG. 5, with the elevated source/drain regions forming
as described above (not shown in FIG. 6). Such processing might be
desired where other portions of the wafer are desired to be masked
during the substantially selective polysilicon deposition, or where
polysilicon growth is desired on less than all of the exposed
source/drain regions or other crystalline material regions which
would be exposed but for provision of layer 48.
[0039] Further exemplary processing is next described with
reference to FIGS. 7 and 8 relative to a wafer fragment 60. Such
comprises a crystalline substrate 62 having a conductive diffusion
region 64 formed therein. In this example, the crystalline silicon
is monocrystalline silicon, but other substrates could be utilized
where the node location of interest is polycrystalline silicon.
Region 64 constitutes a substrate node location to which electrical
contact is desired. A substantially amorphous insulating material
layer 66 is formed over substrate node location 64, and a contact
opening 68 is etched through such material over node location 64,
and in this example, all the way to the crystalline silicon of node
location 64.
[0040] Referring to FIG. 8, substrate 60 has been provided within a
chemical vapor deposition reactor and processing conducted, as for
example as described above, effectively to substantially
selectively deposit polysilicon 70 within contact opening 68 on
crystalline silicon of node location 64, and not on insulating
material 66.
[0041] Further alternate processing is described with reference to
FIGS. 9-12 with respect to a semiconductor wafer fragment 72. Like
numerals from the first described embodiment have been utilized
where appropriate with differences being indicated with the suffix
"a" or with different numerals. Wafer fragment 72 appears as wafer
fragment 60 of FIG. 7 at a processing step immediately subsequent
thereto. Specifically, wafer fragment 72 includes a deposited metal
layer 74, such as Ti or W.
[0042] Referring to FIGS. 10 and 11, wafer fragment 72 has been
subjected to, for example, conventional SALACIDE processing to form
a silicide region 76 at the base of contact opening 68. Metal layer
74 is thereafter stripped (FIG. 11) to leave silicide region 76 at
the base of contact 68. Such provides a node location at the base
of contact 68 which, in this example, comprises an outwardly
exposed substantially crystalline surface in the form of a
silicide.
[0043] Referring to FIG. 12, wafer fragment 72 has been provided
within a chemical vapor deposition reactor and conditions provided
to be effective to substantially selectively deposit polysilicon 80
on the outwardly exposed silicide node location surface and not on
insulating material 66.
[0044] Further alternate processing is next described with
reference to FIGS. 13-15 regarding methods of forming a capacitor.
FIG. 13 illustrates a semiconductor wafer fragment 81 comprised of
bulk monocrystalline silicon 82 having a diffusion region 83 formed
therein. A layer of amorphous silicon dioxide 84 is formed
thereover. A contact opening 86 is etched through layer 84 to
diffusion region 83. Opening 86 is plugged with a crystalline
material 87, such as conductive polysilicon, and planarized
relative to layer 84.
[0045] Referring to FIG. 14, substrate 81 has been placed within a
chemical vapor deposition reactor and processed as described above
to selectively deposit polysilicon 88 over crystalline material 87.
Polysilicon 88 can be further processed, such as by patterning, to
form a desired first capacitor electrode shape if the initial
deposition is not as desired.
[0046] Referring to FIG. 15, a capacitor dielectric layer 89 is
deposited followed by deposition of a second capacitor electrode
layer 90 to form a capacitor 93. Such can be formed by conventional
or other processing. For example, techniques of the invention as
described above can be utilized to selectively deposit second
capacitor electrode layer 90 on dielectric layer 89 where such is
fabricated to be crystalline. For example, barium strontium
titanate and Ta.sub.2O.sub.5 are exemplary crystalline capacitor
dielectric layer materials. Such material can be deposited over
first capacitor electrode 88, patterned if desired to provide
exposed amorphous material and the crystalline material 89 where
desired, and a selective deposition as described above then
conducted.
[0047] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *