U.S. patent application number 10/327702 was filed with the patent office on 2006-01-26 for process for manufacturing an soi wafer by annealing and oxidation of buried channels.
This patent application is currently assigned to STMicroelectronics S.r.I.. Invention is credited to Gabriele Barlocchi, Pietro Corona, Flavio Villa.
Application Number | 20060017131 10/327702 |
Document ID | / |
Family ID | 39049874 |
Filed Date | 2006-01-26 |
United States Patent
Application |
20060017131 |
Kind Code |
A9 |
Villa; Flavio ; et
al. |
January 26, 2006 |
Process for manufacturing an SOI wafer by annealing and oxidation
of buried channels
Abstract
A process for manufacturing an SOI wafer, including the steps
of: forming, in a wafer of semiconductor material, cavities
delimiting structures of semiconductor material; thinning out the
structures through a thermal process; and completely oxidizing the
structures.
Inventors: |
Villa; Flavio; (Milano,
IT) ; Barlocchi; Gabriele; (Cornaredo, IT) ;
Corona; Pietro; (Roma, IT) |
Correspondence
Address: |
GRAYBEAL JACKSON HALEY LLP;Suite 350
155-108th Avenue N.E.
Bellevue
WA
98004-5973
US
|
Assignee: |
STMicroelectronics S.r.I.
|
Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 20030168711 A1 |
September 11, 2003 |
|
|
Family ID: |
39049874 |
Appl. No.: |
10/327702 |
Filed: |
December 20, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09625112 |
Jul 25, 2000 |
6518147 |
|
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10327702 |
Dec 20, 2002 |
|
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Current U.S.
Class: |
257/506 |
Current CPC
Class: |
H01L 21/76283 20130101;
H01L 29/0649 20130101; H01L 21/764 20130101; H01L 21/76289
20130101; Y10S 438/967 20130101; H01L 21/3003 20130101; H01L
21/3247 20130101 |
Class at
Publication: |
257/506 |
International
Class: |
H01L 29/00 20060101
H01L029/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 28, 2001 |
EP |
01830820.5 |
Claims
1. A process for manufacturing an SOI wafer, comprising the steps
of: forming, in a wafer of semiconductor material, cavities which
delimit structures of said semiconductor material; and oxidizing
completely said structures; characterized by performing, before
said step of oxidizing, a step of thinning out said structures
through a thermal process.
2. The process according to claim 1, characterized in that said
step of thinning out comprises modifying the surface distribution
of said semiconductor material around said cavities.
3. The process according to claim 2, characterized in that said
step of modifying comprises annealing said wafer in a deoxidizing
atmosphere.
4. The process according to claim 1, characterized in that said
thermal process has a controlled duration.
5. The process according to claim 1, characterized in that said
step of forming cavities comprises embedding said cavities within
said wafer.
6. The process according to claim 5, characterized in that said
step of embedding comprises entrapping hydrogen inside said
cavities.
7. The process according to claim 1, characterized in that said
step of forming cavities comprises the steps of: opening first
trenches in a substrate of said wafer; and performing an epitaxial
growth, so as to upwardly close said first trenches with said
semiconductor material.
8. The process according to claim 7, characterized in that said
structures comprise walls arranged side-by-side and separated from
each other by said first trenches.
9. The process according to claim 8, characterized in that said
first trenches are substantially rectilinear and have a height and
a width smaller than said height, and in that the ratio between
said height and said width is not smaller than 5.
10. The process according to claim 8, characterized in that said
width is substantially equal to a width of said walls.
11. The process according to claim 8, characterized in that, at the
end of said step of thinning out, said cavities have a
substantially circular cross-section.
12. The process according to claim 7, characterized in that said
structures comprise columns.
13. The process according to claim 1, characterized in that, before
said step of oxidizing, at least one second trench having a depth
reaching said cavities is opened.
14. The process according to claim 12, characterized in that said
second trench extends along a closed line and delimits an insulated
region.
15. The process according to claim 1, characterized in forming,
inside said cavities, a filling region of a dielectric
material.
16. The process according to claim 15, characterized in that said
dielectric material is TEOS oxide.
17. A method, comprising: forming in a semiconductor material
cavities separated by walls; thermally annealing the semiconductor
material after forming the cavities; and converting the walls into
insulators after thermally annealing the semiconductor
material.
18. The method of claim 17 wherein forming the cavities comprises:
forming trenches in a first region of the semiconductor material;
and forming a second region of the semiconductor material over the
first region after forming the trenches.
19. The method of claim 17 wherein forming the cavities comprises
forming the cavities such that they hold a deoxidizing
atmosphere.
20. The method of claim 17 wherein: each of the cavities has a
cross-sectional shape; and thermally annealing the semiconductor
material changes the cross-sectional shape of at least one of the
cavities.
21. The method of claim 17, further comprising filling the cavities
with an insulator after converting the walls to insulators.
22. The method of claim 17 wherein converting the walls into
insulators comprises: forming a cavity opening around a surface
region of the semiconductor material; and oxidizing the walls via
the cavity opening.
23. The method of claim 17, further comprising: wherein converting
the walls into insulators comprises, forming a cavity opening
around a surface region of the semiconductor material, and
oxidizing the walls via the cavity opening; and filling the
cavities with an insulator after oxidizing the walls.
24. The method of claim 17 wherein thermally annealing the
semiconductor material comprises heating the semiconductor
materially at substantially 1150.degree. C. for substantially five
hours.
25. A semiconductor structure, comprising: a first semiconductor
region; a second semiconductor region disposed on the first
semiconductor region; and a dielectric region disposed between the
first and second semiconductor regions and including, a first
insulator material, at least one cavity disposed within the first
insulator material, and a second insulator material that is
different than the first insulator material and that is disposed
within the at least one cavity.
26. The semiconductor structure of claim 25 wherein the first and
second semiconductor regions comprise silicon.
27. The semiconductor structure of claim 25, further comprising a
semiconductor device disposed in the second semiconductor
region.
28. The semiconductor structure of claim 25 wherein: the first
semiconductor region comprises an inner periphery; the second
semiconductor region comprises an outer periphery and is disposed
within the inner perhiphery of the first semiconductor region; and
a portion of the dielectric region is disposed between the inner
periphery of the first semiconductor region and the outer periphery
of the second semiconductor region.
29. The semiconductor structure of claim 25 wherein: the first
semiconductor region comprises an inner periphery; the second
semiconductor region comprises an outer periphery and is disposed
within the inner perhiphery of the first semiconductor region; and
a portion of the dielectric region is disposed between the inner
periphery of the first semiconductor region and the outer periphery
of the second semiconductor region, the portion including an inner
region that intersects the at least one cavity and that is filled
with the second insulator material and including an outer region
that is filled with the first insulator material.
30. The semiconductor structure of claim 25 wherein the dielectric
region further comprises a trench that extends between a surface of
the dielectric region and the at least one cavity and that is
filled with the second insulator material.
31. The semiconductor structure of claim 25 wherein: the first
insulator material comprises silicon dioxide; and the second
insulator material comprises tetraethylorthosilicate (TEOS).
32. The semiconductor structure of claim 25 wherein the at least
one cavity has a substantially circular cross section.
Description
PRIORITY CLAIM
[0001] This application claims priority from European patent
application No. 01830820.5, filed Dec. 28, 2001, which is
incorporated herein by reference.
TECHNICAL FIELD
[0002] The present invention relates generally to semiconductor
processing, and more particularly to a process for manufacturing an
SOI wafer annealing and oxidation of buried channels.
BACKGROUND
[0003] As is known, according to a solution that is currently very
widespread in the sector of the microelectronics industry, the
substrate of integrated devices is obtained from monocrystalline
silicon wafers. In recent years, as an alternative to wafers made
of silicon alone, composite wafers have been proposed, namely the
so called silicon-on-insulator (SOI) wafers, consisting of two
silicon layers, one of which is thinner than the other, separated
by a silicon dioxide layer.
[0004] However, manufacturing of SOI wafers entails some problems,
especially as regards the complexity and cost of the process and
the quality of the thinner silicon layer. In fact, this layer is
designed to house both high-power and low-power electronic devices,
and the presence of crystallographic defects may irreparably impair
the efficiency of the devices.
[0005] One method for manufacturing SOI wafers that partially
tackles the above problems is described in EP-A1 073 112, filed on
Jul. 26, 1999 in the name of the present applicant and incorporated
by reference.
[0006] This method envisages initially forming, in a substrate of
semiconductor material, for example monocrystalline silicon, a
plurality of trenches which are substantially parallel and are
separated from one another by silicon partition walls. In order to
open the trenches, the substrate is anisotropically etched using a
hard mask, which comprises, for example, a pad oxide layer and a
silicon nitride layer.
[0007] Subsequently, by isotropically etching silicon, the trenches
are widened so as to thin out the partition walls and form cavities
which extend beneath the surface of the substrate, which, at this
stage, is still protected by the hard mask.
[0008] The cavities are then lined with an inhibiting silicon
dioxide layer, and the hard mask is removed, thus leaving the
surface of the substrate uncovered.
[0009] Next, an epitaxial growth is carried out. In this step, the
silicon grows on top of the substrate and expands laterally so as
to form a uniform epitaxial layer that covers the entrance of the
cavities. However, the inhibiting layer prevents silicon from
growing inside the cavities, which thus are not filled and form
buried channels.
[0010] Using a second anisotropic etch, connection trenches are
opened, which have a depth such as to reach the cavities. Through
the connection trenches, a thermal oxidation step is then
performed, so that the partition walls separating the cavities are
completely oxidized and the cavities are filled with silicon
dioxide. Thereby, a continuous insulating region is formed, which
separates the substrate and the epitaxial layer.
[0011] The process taught in the above mentioned patent application
yields high quality SOI wafers, above all as regards
crystallographic properties of the epitaxial layer, but has some
limitations.
[0012] In fact, the processing steps required for forming the
insulating region are numerous and complex and render the
manufacturing of the wafers costly. First, during isotropic etching
for widening the trenches and forming the cavities, the surface of
the substrate must be protected, in particular with the hard mask.
The formation of this mask, however, requires at least one
oxidation step, one silicon nitride layer deposition step, and one
definition step using a further resist mask. The hard mask must
moreover be removed through further special steps.
[0013] Second, before carrying out the epitaxial growth, the
cavities must be lined with the inhibiting layer; otherwise, in
fact, the partition walls would get thicker and subsequently could
no longer be oxidized completely. In addition, it is necessary to
calibrate with precision the width of the inhibiting layer, which
is partially removed during removal of the hard mask.
SUMMARY
[0014] Therefore, an embodiment of the present invention is a
process that overcomes the drawbacks of the manufacturing process
described above.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] For a better understanding of the present invention, a
preferred embodiment thereof is now described, purely as a
non-limiting example, with reference to the attached drawings,
wherein:
[0016] FIGS. 1-4 are cross-sectional views of a wafer of
semiconductor material in successive manufacturing steps, according
to an embodiment of the present invention;
[0017] FIG. 5 is a top plan view of the wafer of FIG. 4;
[0018] FIG. 6 is a cross-sectional view of the wafer of FIG. 5
according to line VI-VI;
[0019] FIGS. 7-10 are a cross-sectional views of the wafer of FIG.
5 according to line VII-VII, in successive manufacturing steps;
[0020] FIG. 11 is a top plan view of a wafer of semiconductor
material in an initial manufacturing step according to a different
embodiment of the invention;
[0021] FIGS. 12 and 13 are cross-sectional views of the wafer of
FIG. 11 according to lines XII-XII and XIII-XIII, respectively;
and
[0022] FIG. 14 presents the same view as in FIG. 12 in a subsequent
manufacturing step of the wafer.
DETAILED DESCRIPTION
[0023] The following discussion is presented to enable a person
skilled in the art to make and use the invention. Various
modifications to the embodiments will be readily apparent to those
skilled in the art, and the generic principles herein may be
applied to other embodiments and applications without departing
from the spirit and scope of the present invention as defined by
the appended claims. Thus, the present invention is not intended to
be limited to the embodiments shown, but is to be accorded the
widest scope consistent with the principles and features disclosed
herein.
[0024] In FIG. 1, a wafer of semiconductor material, for example
monocrystalline silicon, is designated by 1 and comprises a
substrate 2. In an initial step of the process according to an
embodiment of the invention, a resist layer is deposited directly
on top of a face 3 of wafer 1 and is defined to form a mask 4.
[0025] Next, the substrate 2 is etched anisotropically, for example
through an STS etch, and deep trenches 5 are opened at the regions
left uncovered by the mask 4, as shown in FIG. 2. In greater
detail, the deep trenches 5 are substantially rectilinear and
extend parallel to each other in a direction perpendicular to the
drawing plane. All the deep trenches 5 have a initial height H and
a same initial width W, and are separated from one another by a
wall 7 having an initial width S. The initial width W of the deep
trenches 5 is substantially equal to the initial width S of the
walls 7 (for example, 1 .mu.m), while the initial depth H is much
greater; preferably the ratio between the initial depth H and the
initial width W is not smaller than 5.
[0026] Next, mask 4 is removed, and an epitaxial growth is
performed (FIG. 3). The silicon grows by a controlled amount on top
of the face 3 of the wafer 1 and expands laterally until it closes
the entrances of the deep trenches 5, thus practically forming
buried channels 8 embedded in the wafer 1 and completely surrounded
by silicon. In an initial stage of the epitaxial growth, silicon
grows also inside the deep trenches 5, before the latter are closed
at the top. Consequently, the buried channels 8 have cross sections
that are substantially oval and elongated in a direction
perpendicular to the surface 3' of the wafer 1. In particular, the
buried channels 8 have an intermediate width W' and an intermediate
height H', which are respectively smaller than the initial width
Wand the initial height S of the deep trenches 5. The intermediate
width S' of the walls 7 is instead increased with respect to the
initial width S (for example, the buried channels 8 have an
intermediate width W' of 0.5 .mu.m and an intermediate height H' of
3 .mu.m, and the partition walls 7 have an intermediate width S' of
1.5 .mu.m). In addition, the buried channels 8 house the same
atmosphere in which the wafer 1 is immersed when the epitaxial
growth is performed. In particular, this atmosphere has a high
hydrogen concentration and is deoxidizing.
[0027] As shown in FIG. 4, the cross section of the buried channels
8 is subsequently modified by a thermal annealing process having a
controlled duration. For example, the wafer 1 is heated to
1150.degree. C. for 5 hours. In this step there is no removal of
silicon. In practice, when the wafer 1 is heated in a deoxidizing
atmosphere, the superficial silicon atoms around the buried
channels 8 migrate and tend to assume minimum energy distributions,
as explained in the article "A New Substrate Engineering for the
Formation of Empty Space in Silicon (ESS) Induced by Silicon
Surface Migration" by T. Sato, N. Aoki, I. Mizushima, and Y.
Tsunashima, IEDM 1999, pp. 517-520. In greater detail, the buried
channels 8, which initially have an oval cross section, tend to
assume a substantially circular cross section. At the end of the
annealing step, then, the buried channels 8 have a final height H''
and a final width W'' which are approximately equal to one another
(for example, 1.5 .mu.m), and the partition walls 7 are thinned out
to reach a final width S'' smaller than the initial width S (for
example, 0.5 .mu.m).
[0028] After annealing, a second masked trench etching is performed
to open in the wafer 1 at least one connection trench 10 having a
depth such as to reach all the buried channels 8 and a width
greater than the final width S'' of the partition walls 7 (for
example, 1 .mu.m). Preferably, the connection trench 10 extends
along a closed line and delimits an insulated monocrystalline
silicon region 11, intended to subsequently form an active area for
accommodating integrated components (FIGS. 5-7).
[0029] Next, thermal oxidation of the partition walls 7 and of the
walls of the connection trench 10 is carried out so as to form a
silicon dioxide insulating region 12. The oxygen required is fed to
the buried channels 8 through the connection trench 10. In this
step, the oxide regions gradually grow at the expense of the
silicon regions that form the partition walls 7 and the walls of
the connection trench 10. In particular, the partition walls 7 are
completely oxidized, by virtue of the width reduction caused by the
previous annealing step. As shown in FIG. 8, the insulating region
12 surrounds the insulated region 11 laterally and at the bottom,
electrically insulating it from the substrate 2. Instead, the
buried channels 8 and the connection trench 10 are partly filled
with thermal oxide, but remain partially open.
[0030] Next (FIG. 9), on the surface 3' of the wafer 1 there is
deposited a layer 13 of dielectric material, for example
tetraethylorthosilicate (TEOS) oxide, which penetrates through the
connection trench 10 and fills the buried channels 8 and the
connection trench 10, preferably completely. In practice, the
deposited dielectric material forms a filling area 14 within the
insulating region 12. Consequently, the insulating region 12 and
the filling region 14 form an insulating structure which is compact
and substantially without any cavities inside it. However, regions
of very small diameter may remain unfilled, but do not
significantly alter the properties of the insulating structure. In
particular, in addition to electrical insulation, the substantial
continuity of the insulating region 12 and of the filling region 14
ensure thermal conductivity between the insulated region 11 and the
substrate 2, and thus dispersion of the heat generated in the
devices made in the wafer 1. The layer 13 of dielectric material is
then removed.
[0031] The wafer 1 of FIG. 10 is thus obtained, wherein the
SOI-type structure can be clearly recognized. In particular, FIG.
10 shows the insulated region 11 and the substrate 2 separated from
one another by the insulating region 12 and the filling region 14.
The substrate 2, which has a larger width, mainly performs the
functions of support and heat dissipation, while inside the
insulated region 11, which is thin, it is possible to form active
and passive integrated devices according to any known process.
[0032] According to a different embodiment of the invention, shown
in FIGS. 11-14, silicon columns 17 are initially formed in a
substrate 16 of a semiconductor wafer 15, the silicon columns 17
preferably having a hexagonal shape in plan view and being
organized in honeycomb fashion to obtain maximum packing. To this
aim, silicon is selectively removed by trench etching, and
communicating trenches 18 are formed, which delimit the columns 17.
In practice, the communicating trenches 18 are connected together
so as to form a hollow region having a complex shape, in which the
columns 17 extend.
[0033] Next, epitaxial growth and annealing are carried out, as
above described. In particular, during the epitaxial growth, the
deep trenches 18 are closed, and a deep cavity 19 is formed, while
during annealing, the columns 17 are thinned out in a central
portion, thus assuming an hourglass shape (FIG. 13).
[0034] The process is then completed as previously described. In
particular, a connection trench 20 is opened, the columns 17 are
completely oxidized so as to form an insulating region 21 which
delimits an insulated silicon region 22, and the buried cavity 19
is filled with TEOS oxide, thus forming filling regions 23.
[0035] The process described herein is extremely simple, at the
same time it enables manufacturing of SOI wafers that are free from
crystallographic defects. In fact, the required processing steps
are not so numerous as in known processes and can be easily
included in standard processes for manufacturing integrated
devices.
[0036] Particularly advantageous is the use of the annealing step,
which, according to the described embodiments of the invention, is
performed instead of isotropic etching previously used for widening
the trenches. The formation of structures, such as walls or
columns, delimited by cavities and embedded in the silicon is in
itself simple, in so far as it requires only one masked trench etch
and one epitaxial growth. The subsequent annealing step allows the
surfaces of the buried cavities (buried channels 8 and buried
cavity 19) to be modified, widening the latter and reducing the
width of the silicon structures (partition walls 7 and columns 17),
so that the silicon structures can then be oxidized. The surface of
the wafer is not, however, involved and thus does not have to be
protected; consequently, all the steps for forming and removing
hard masks are eliminated. Also the need for the inhibiting layer
is overcome: since the annealing follows epitaxial growth, forming
silicon inside the deep trenches 5 (or the communicating trenches
18) is within bearable limits, provided that these deep trenches
are not filled completely.
[0037] In addition, the atmosphere entrapped inside the buried
cavities is the same as used for the epitaxial growth, namely an
atmosphere with a high hydrogen concentration. In practice, the
annealing step, which normally requires the use of a hydrogen oven,
can be performed using a standard thermal process. Furthermore,
with a single thermal process it is possible to carry out both
annealing and other manufacturing steps that are normally envisaged
for manufacturing components and/or integrated circuits; for
example, annealing could be carried out simultaneously with the
diffusion of a previously implanted doping species.
[0038] Finally, it is clear that numerous modifications and
variations may be made to the process described and illustrated
herein, all falling within the scope of the invention, as defined
in the attached claims.
[0039] In particular, the process can be used for selectively
insulating portions of the wafer. Alternatively, the insulating
region may extend throughout the wafer.
[0040] Annealing could be carried out even before epitaxial growth.
In this case, however, it would be necessary to use a hydrogen
oven.
[0041] Furthermore, the initial shape of the trenches may be
different from the shapes shown herein.
* * * * *