U.S. patent application number 11/224863 was filed with the patent office on 2006-01-19 for wafer processing apparatus & methods for depositing cobalt silicide.
Invention is credited to David Lee, Water Lur, Kuang-Chih Wang.
Application Number | 20060014388 11/224863 |
Document ID | / |
Family ID | 29710637 |
Filed Date | 2006-01-19 |
United States Patent
Application |
20060014388 |
Kind Code |
A1 |
Lur; Water ; et al. |
January 19, 2006 |
Wafer processing apparatus & methods for depositing cobalt
silicide
Abstract
A cluster tool and a number of different processes for making a
cobalt-silicide material are disclosed. Combinations of alloyed
layers of Co--Ti--along with layers of Co--are arranged and heat
treated so as to effectuate a silicide reaction. The resulting
structures have extremely low resistance, and show little line
width dependence, thus making them particularly attractive for use
in semiconductor processing. A cluster tool is configured with
appropriate sputter targets/heat assemblies to implement many of
the needed operations for the silicide reactions, thus resulting in
higher savings, productivity, etc.
Inventors: |
Lur; Water; (Taipei, TW)
; Lee; David; (Hsinchu, TW) ; Wang;
Kuang-Chih; (Taichung, TW) |
Correspondence
Address: |
J. NICHOLAS GROSS, ATTORNEY
2030 ADDISON ST.
SUITE 610
BERKELEY
CA
94704
US
|
Family ID: |
29710637 |
Appl. No.: |
11/224863 |
Filed: |
September 12, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10640779 |
Aug 13, 2003 |
6943110 |
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11224863 |
Sep 12, 2005 |
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10166307 |
Jun 10, 2002 |
6743721 |
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10640779 |
Aug 13, 2003 |
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Current U.S.
Class: |
438/683 ;
257/E21.165; 257/E21.438; 257/E29.266; 438/592; 438/664;
438/682 |
Current CPC
Class: |
H01L 29/7833 20130101;
H01L 21/28518 20130101; H01L 29/665 20130101; H01L 29/6656
20130101; H01L 21/28052 20130101; H01L 29/6659 20130101; H01L
21/67167 20130101; H01L 21/67184 20130101 |
Class at
Publication: |
438/683 ;
438/592; 438/664; 438/682 |
International
Class: |
H01L 21/44 20060101
H01L021/44; H01L 21/4763 20060101 H01L021/4763 |
Claims
1-23. (canceled)
24. A cluster tool for performing semiconductor processing
operations on a wafer, the cluster tool comprising: (a) a load lock
chamber for receiving the wafer; and (b) a sputter chamber coupled
to the load lock chamber so that the wafer can be transported
without breaking vacuum, said sputter chamber being equipped with a
cobalt alloy target for sputtering a target material on the wafer;
said sputter chamber being further configured such that it can be
purged of oxygen and nitrogen prior to a sputtering operation; (c)
a heat annealing apparatus for heating the wafer at a rate and
temperature sufficient to cause a silicide reaction between the
sputtered target material and the wafer; wherein the heat annealing
apparatus is coupled to the sputter chamber so that the wafer is
not exposed to a contaminant containing ambient between steps (b)
and (c).
25. The cluster tool of claim 24, wherein said load lock chamber is
used for outgassing of the wafer.
26. The cluster tool of claim 20, wherein said sputter chamber and
said heat annealing apparatus are integrated in a single processing
station.
27. The cluster tool of claim 20, further including a second
sputter chamber equipped with a second target including cobalt for
sputtering a second target material on the wafer.
28. The cluster tool of claim 20, further including a cleaning
station for performing a cleaning operation on the wafer prior to
any sputter operation.
29. The cluster tool of claim 20, wherein a target for said sputter
chamber is adjustable in situ so that two different target
materials can be deposited on the wafer without changing
locations.
30-32. (canceled)
33. A cluster tool for performing semiconductor processing
operations on a wafer, the cluster tool comprising: (a) a cleaning
chamber adapted to remove oxide from the wafer; (b) a first sputter
chamber equipped with a cobalt target for sputtering a first target
material on the wafer; (c) a second sputter chamber equipped with a
cobalt and refractory metal alloy target for sputtering a second
target material on the wafer; (d) a wafer handler for transporting
the wafer so that it is not exposed to air at least between the
first sputter chamber and second sputter chamber; (e) a heat
annealing apparatus integrated within the cluster tool for heating
the wafer at a rate and temperature sufficient to cause a silicide
reaction on the wafer; wherein the heat annealing apparatus is
adapted within the cluster tool so that the wafer is not exposed to
a contaminant containing ambient between steps (d) and (e).
34. The cluster tool of claim 33, wherein the cleaning chamber uses
a sputtering operation.
35. The cluster tool of claim 33, wherein the first target material
includes between about 80-100 Angstroms of Cobalt.
36. The cluster tool of claim 33, wherein the refractory metal
includes one or more of: Ti, Ta, W, Mo, Zr, Hf and/or Nb.
37. The cluster tool of claim 33 wherein the heat annealing
apparatus is integrated as part of said second sputter chamber.
38. The cluster tool of claim 33 wherein the heat annealing
apparatus is located within a separate anneal chamber.
39. The cluster tool of claim 33, wherein a ternary target is used
in said second sputter chamber to form an additional layer on said
second target material.
40. The cluster tool of claim 33, wherein a ternary target is used
in said second sputter chamber to form an additional layer on said
second target material.
41. A cluster tool for performing semiconductor processing
operations on a wafer, the cluster tool comprising: (a) a cleaning
chamber adapted to remove oxide from the wafer; (b) a first sputter
chamber equipped with a first metal target including cobalt and a
refractory metal and configured to sputter a first target material
on the wafer; (c) a second sputter chamber equipped with a second
metal target and configured to sputter a second target material on
said first target material, which second target material has a
higher concentration of cobalt than a layer formed on the wafer by
said first target material; wherein the second sputter chamber
includes an integrated heater to facilitate formation of Co2Si
and/or CoSi during sputtering; (d) a wafer handler for transporting
the wafer so that it is not exposed to air at least between the
first sputter chamber and second sputter chamber.
42. The cluster tool of claim 41, wherein said first target
material is used to form a layer of about 5 to 15 nm on the
wafer.
43. The cluster tool of claim 41, wherein said second metal target
includes only Cobalt.
44. The cluster tool of claim 41, wherein said first metal target
includes a concentration of said refractory metal in excess of 50
atomic percent.
45. The cluster tool of claim 41, further including a heat
annealing apparatus integrated within the cluster tool for heating
the wafer at a rate and temperature sufficient to cause a silicide
reaction on the wafer.
46. The cluster tool of claim 45 wherein the heat annealing
apparatus is adapted within the cluster tool so that the wafer is
not exposed to a contaminant containing ambient.
Description
FIELD OF THE INVENTION
[0001] This invention relates to a process and system for making a
cobalt silicide material suitable for a semiconductor manufacturing
process.
BACKGROUND OF THE INVENTION
[0002] Deep submicron (DSM) complementary metal oxide semiconductor
(CMOS) circuits make extensive use of interconnects and contacts,
and these latter features must be scaleable as well to ensure
smooth migrations to smaller geometries. Connections to and between
active CMOS FET devices are typically created with so-called
"silicide" contacts, in which a portion of a source/drain region is
converted during a thermal treatment into a metallic low resistance
region. Solicitation reactions are well-known, and state of the art
manufacturing processes in the 0.18 micron realm typically utilize
some form of TiSi2 material as a gate and active region contact.
However TiSi2 has several limitations, including
linewidth-dependent sheet resistance, low thermal stability, and
the fact that titanium can consume an unpredictable amount of
silicon during the salicidation reaction. Such characteristics
severely handicap the potential for TiSi2 in next generation
technologies.
[0003] Cobalt silicide (CoSi2) has recently been advocated as a
replacement for TiSi2.
[0004] One example of a prior art technique disclosing the making
and use of CoSi2 is Goto et. al. "Optimization of Salicide Process
for sub 0.1 um CMOS Devices" 1994 Symposium on VLSI Technology
Digest of Technical Papers, page 119. Cobalt, however, is not
without its limitations and problems as well. For instance, Cobalt
is sensitive to oxygen and water. Even using very high purity inert
gas for the heat treatment, the resulting cobalt salicide is often
oxygen contaminated and a sheet resistance of the cobalt salicide
thus increases. To prevent such oxidization of the cobalt layer,
Goto discloses a cobalt salicide process using a Ti or TiN cap
layer on top of the cobalt layer. Thus, a cobalt layer is deposited
on a wafer having a top surface comprised of a mixture of exposed
surfaces, including dielectric (typically sidewall and isolation)
surfaces and silicon surfaces (typically gate and source/drain
regions). A Ti or TiN cap layer is deposited on the cobalt layer
without exposing the cobalt layer to air. The wafer is then
subjected to a first anneal. During the first anneal cobalt reacts
with silicon at the surface of the wafer where silicon contacts
with cobalt After the first anneal the wafer is etched in a NH4OH,
H2O2, H2O solution and then with a HCl, H2O2, H2O solution. This
two-step wet process etches away any metals which are not
silicided, that is, Co, Ti, TiN and mixtures thereof. The wafer is
then subjected to a second annealing process. In this process
conventional semiconductor process quality N2 can be used during
the first annealing. After this first anneal the Ti or TiN cap
prevents residual oxygen from reacting with Co; therefore the
resistance of the produced cobalt salicide does not increase due to
an oxygen contamination problem.
[0005] As mentioned earlier, to prevent oxidation during
silicidation, Ti and TiN are most widely used for capping a Co
layer in the Co salicide process. The two materials have different
strengths and weaknesses in this regard. For instance, TiN is more
stable and does not react much with the Co layer. Nonetheless, Ti
is more favored at this time, in large part because Ti is more
reactive toward oxygen, and therefore is a potentially a better cap
for preventing oxidation of Co. A Ti cap is also known to produce a
more thermally stable Co salicide film. This fact is disclosed in
Sohn et al. "Effects of Ti-capping on formation and stability of Co
silicide" Journal of The Electrochemical Society 147 (1) page
373-380, 2000.
[0006] The use of Ti capping on Co however results in a complicated
silicidation reaction. As Sohn points out, during the first anneal,
Si reacts with Co to form a CoSix layer, consisting of primarily
CoSi and CoSi2; Ti diffuses into the Co layer as Co reacts with Si;
the Co and Ti form a layer of intermetallic mixture and the Ti
layer experiences some nitridation. All these reactions take place
in the same time causing complex process control consequences. This
phenomenon is illustrated generally in FIG. 14.
[0007] In addition, for a Ti capped Cobalt silicide process, the
first anneal temperature typically needs to be higher than for a
comparable TiN capped process. This is a result of the effect of Ti
diffusion into the Co layer and the resulting mediation of the
silicidation reaction by Ti. In other words, in a Ti-mediated
cobalt silicidation process, the presence of Ti retards the Co--Si
reaction so that higher anneal temperatures are needed to complete
the total reaction. According to Sohn, Ti diffuses into the Si
interface and silicide grain boundary, thus stabilizing the final
CoSi2 film,. Not all deposited Co reacts to form silicide because
some Co reacts with the Ti and is converted into a Co--Ti
intermetallic mixture layer. Usually in conventional processes, a
Ti cap of 1 to 2 times the thickness of Co is used. Using such a
large amount of Ti in turn affects the amount of Co that can
ultimately react with silicon. All of these effects are hard to
predict and control, and this makes the task of process engineering
with cobalt silicide quite complicated. For instance, the final
thickness of Cobalt silicide needs to be precisely controlled for
more advanced generation of process because of the scaling down of
source and drain junction depth.
[0008] Thus, although the conventional Co salicide process
generally meets the requirement of advanced process of less than
0.1 um feature size, there is need to further improve the Co
salicide process, and to ensure that it will be useable even below
such feature size. There is a substantial need in the industry to
have an extremely small feature size/line width Co silicide process
that achieves such scaled down thicknesses yet has good thermal
stability to withstand anneal temperature near 800 to 900 degrees
centigrade without agglomeration. Furthermore, there is a need to
be able to control the process with a better process margin,
especially as pertains to the thickness and the sheet resistance of
the Co silicide film. Finally, there is an additional pressing need
for a basic process flow and process tool for forming Co salicide
that achieves a higher productivity in conventional semiconductor
manufacturing.
SUMMARY OF THE INVENTION
[0009] A primary object of the present invention therefore is to
provide a solution to many of the aforementioned problems
associated with the manufacturing of cobalt silicide.
[0010] A related object is to provide a high performance, easily
manufacturable contact material suitable for a variety of
semiconductor applications, including in self-aligned silicide
(SALICIDE) applications;
[0011] Another object of the present invention is to provide an
improved integrated deposition system that is capable of depositing
and treating various semiconductor layers, including high
performance silicides such as cobalt silicide;
[0012] Yet another object of the present invention is to provide
cost effective, reliable Co silicide processes suitable for mass
implementation of next generation IC technologies in conventional
semiconductor fabrication facilities.
[0013] A first aspect of the invention therefore concerns a method
of forming silicide materials on a silicon based substrate in which
a combination of Co an Co--Ti is used. This includes generally the
steps of: depositing a first metal layer on the silicon based
substrate, the first metal layer including Cobalt (Co); and
depositing a second metal layer on at least selected portions of
the first metal layer, the second metal layer including an alloy of
Cobalt and a refractory metal; and performing a first heat
treatment so as to convert at least part of the first metal layer
and the silicon based substrate into a first silicide composition
having one Or more cobalt silicide phases, the one or more cobalt
silicide phases being characterized by a first resistitivity; and
performing a second heat treatment so as to convert the first
composition, including the one or more cobalt silicide phases, into
a second silicide composition containing primarily a lower
resistivity cobalt silicide phase, the lower resistivity cobalt
silicide phase having a resistivity substantially less than the
first resistivity.
[0014] In a preferred approach for this aspect of the invention,
the alloy is a composition including 20 to 80 percent atomic
Titanium. In addition, a further step of removing any non-silicides
after step (c) is also performed in most instances. Further in a
preferred approach, an additional step of: cleaning the silicon
substrate so as to substantially remove any non-native oxides is
done prior to step (a). In addition, the alloy is preferably a
ternary composition of Cobalt, Titanium, and one additional
refractory metal and/or carbon.
[0015] Further in a preferred approach of this aspect of the
invention, steps (a) through (c) are performed in a single
semiconductor wafer processing cluster tool, and without exposing a
wafer to ambient between such steps. This further increases
reliability, productivity and throughput.
[0016] Another aspect of the invention concerns forming Co based
silicide materials on a silicon based substrate within a cluster
tool, and comprising the steps of: depositing a first metal layer
on at least selected portions of the silicon based substrate within
a first processing chamber of a semiconductor process cluster tool,
the first metal layer including an alloy of Cobalt and a refractory
metal (preferably Ti). The alloy includes a percentage of
refractory metal in the range of 1 to approximately 10 percent. A
first heat treatment is performed within the semiconductor process
duster tool so as to convert at least part of the first metal layer
and the silicon based substrate into a first silicide composition
having one or more cobalt silicide phases, the one or more cobalt
silicide phases being characterized by a first resistitivity. After
this, a purge treatment within the semiconductor process cluster
tool is performed using a noble gas so as to remove contaminants
and reactive gasses at least prior to steps (a) and/or (b). Then, a
second heat treatment converts the first composition, including the
one or more cobalt silicide phases, into a second silicide
composition containing primarily a lower resistivity cobalt
silicide phase, the lower resistivity cobalt silicide phase having
a resistivity substantially less than the first resistivity.
[0017] In a preferred approach, the first heat treatment is
performed as an in-situ anneal while the first metal layer is being
deposited. Because a small amount of titanium is used in the target
the resulting silicide contains trace amounts of the same.
[0018] A related aspect of the invention pertains to a method of
forming silicide materials in which both sputtering and heat
processing operations are performed, to effectuate a type of high
temperature sputtering of an alloy layer containing an alloy of
Cobalt (Co) and a second refractory metal onto a silicon based
substrate. The Co is present in the alloy layer in an amount
sufficient for forming a low resistivity salicide contact with the
silicon based substrate. While the sputtering is taking place, the
silicon based substrate is heated in-situ (by a heating lamp) at a
temperature and time sufficient to cause at least partial
salicidation of the silicon based substrate and the alloy layer.
The final salicidation is achieved during a subsequent heating
step, which is at a higher temperature, and which can also be
performed in-situ at the same processing station of a cluster
chamber.
[0019] Yet another aspect of the invention is directed to a method
of forming silicide materials on a silicon based substrate using
two different layers of cobalt. This process generally include the
following steps: (a) depositing a first metal layer on the silicon
based substrate, the first metal layer including including an alloy
of Cobalt and a refractory metal; and (b) depositing a second metal
layer on the silicon based substrate, the second metal layer
including a concentration of Cobalt exceeding that of the first
metal layer; and (c) performing a first heat treatment
substantially contemporaneously with step (b) so as to convert at
least part of the first metal layer, the second metal layer and the
silicon based substrate into a first silicide composition having
one or more cobalt silicide phases, the one or more cobalt silicide
phases being characterized by a first resistitivity; and (d)
performing a second heat treatment so as to convert the first
composition, including the one or more cobalt silicide phases, into
a second silicide composition containing primarily a lower
resistivity cobalt silicide phase, the lower resistivity cobalt
silicide phase having a resistivity substantially less than the
first resistivity.
[0020] In a preferred approach, the alloy includes about 20 to 80
atomic percent of Ti, and the second metal layer includes a second
alloy of Cobalt and a refractory metal. As before, steps (a), (b)
and (c) preferably occur within a single semiconductor wafer
processing cluster tool.
[0021] Yet another aspect of the invention concerns a method of
operating a cluster tool to effectuate the aforementioned Co
silicide processes and reactions. One representative example uses
the following steps: (a) cleaning the silicon based wafer to remove
any native oxides and/or contaminants; and (b) out-gassing the
silicon based wafer. At this point, the silicon based wafer is
substantially water-mark free. Thereafter in step (c) a first metal
layer is sputtered on the silicon based wafer using an alloy target
comprising cobalt (Co) and at least one refractory metal. Then a
step (d) annealing the silicon based wafer in a first anneal
treatment to cause the cobalt to react with silicon located on the
silicon based wafer is performed. To enhance reliabiltity and
productivity, steps (b) through (e) are performed in a single
semiconductor wafer processing cluster tool.
[0022] Since many cluster tools do not include wet etching, such
steps are performed on the silicon based wafer at a processing
station separate from the single semiconductor wafer processing
cluster tool to remove metals other than silicides. Furthermore,
the outgassing step can also occur in a loadlock chamber of the
single semiconductor wafer processing cluster tool.
[0023] Still another aspect of the invention is directed to a
cluster tool for performing semiconductor processing operations on
a wafer. The cluster tool is adapted to have: (a) a load lock
chamber for receiving the wafer; and (b) a sputter chamber equipped
with a cobalt alloy target for sputtering a target material on the
wafer; and (c) a heat annealing apparatus for heating the wafer at
a rate and temperature sufficient to cause a silicide reaction
between the sputtered target material and the wafer.
[0024] The load lock chamber is preferably used for outgassing of
the wafer. The sputter chamber and the heat annealing apparatus are
preferably integrated in a single processing station to effectuate
an in-situ; high temperature sputtering operation. A second sputter
chamber is also equipped with a second target including cobalt for
sputtering a second target material on the wafer. Furthermore, a
cleaning station is adapted for performing a cleaning operation on
the wafer prior to any sputter operation. Finally, in another
variation, a target for the sputter chamber is adjustable in situ
so that two different target materials can be deposited on the
wafer without changing locations.
[0025] Other aspects of the present invention are directed to
structures, compositions and semiconductor devices that are formed
as a result of the aforementioned Co silicide reactions and
processes, and using the cluster tools as described.
[0026] These and other aspects of the invention are now described
in detail with reference to the attached drawings and other
supporting materials provided herein.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIGS. 1 to 6 are cross sectional views generally
illustrating an overall manufacturing method for making a layer of
cobalt silicide, and a semiconductor device employing the same in
accordance with a first embodiment of the present invention;
[0028] FIGS. 7 to 9 are cross sectional views generally
illustrating an overall manufacturing method for making a layer of
cobalt silicide, and a semiconductor device employing the same in
accordance with a second embodiment of the present invention;
[0029] FIGS. 10 to 13 are cross sectional views generally
illustrating an overall manufacturing method for making a layer of
cobalt silicide, and a semiconductor device employing the same in
accordance with a third embodiment of the present invention;
[0030] FIG. 14 depicts a cross section of a prior art scheme for
forming cobalt silicide, including intermediate reactions results
generated by an anneal step;
[0031] FIG. 15 depicts some of the intermediate reactions results
generated by a cobalt silicide process of the present invention
during an anneal step;
[0032] FIG. 16 generally illustrates a preferred embodiment of a
deposition/reaction system configured in accordance with the
teachings of the present invention for depositing and forming
silicide materials.
DETAILED DESCRIPTION OF THE INVENTION
[0033] The following detailed description is meant to be
illustrative only of particular embodiments of the invention. Other
embodiments of the invention and variations of those disclosed will
be obvious to those skilled in the art in view of the following
description.
First Embodiment
[0034] A preferred method employed by a first embodiment of the
invention is depicted collectively in FIGS. 1 to 6. In FIG. 1, a
cross-section of a semiconductor wafer 100 shows a conventional
semiconductor device 105 formed in a lightly doped (n or p type)
substrate 101, and which device typically has a doped (n or p type)
polysilicon based gate electrode 110, a gate insulating film 115,
dielectric (SiN) sidewall spacers 120, 121, shallow doped (n or p
type) source/drain regions 130, 131 and deep doped (also n or p)
source/drain regions 135, 136. Device 100 typically is also
bordered by one or more isolation regions 138, consisting of
various insulating films such as SiO2. The materials and
manufacturing techniques used to create such starting structures
are well-known in the art, so in the interests of brevity and
clarity they are not reproduced here. While the present invention
is preferably used with a polysilicon based gate electrode 110, and
silicon-based source/drain regions 135, 136, it will be apparent to
those skilled in the art that the present teachings can be used
with any suitable base material that can be controllably reacted
with cobalt.
[0035] The exposed silicon surface portions (i.e., gate electrode
110, source/drain regions 135, 136) typically comprise both n type
and p type doped regions for both polysilicon and substrate areas
across wafer 100. The silicon substrate areas 135.136 and
polysilicon gate 110 are generally doped by P, As, B and Ge ion
implanted impurities, and are usually covered with a thin native
oxide (not shown) as noted earlier. This native oxide must be
removed prior to the silicidation process to ensure proper contact
formation.
[0036] To do this, wafer 100 is processed using any number of
conventional techniques known in the art for removing or reducing
native oxide on a silicon surface. In a preferred method, wafer 100
is processed with a HF dip preferably using deoxygenated water.
Isopropyl alcohol drying of the wafer prevents water marks. HF dip
and Isopropyl alcohol drying can be performed in a batch process as
well as a single wafer process. Another approach is to use a HF
vapor treatment to remove the native oxide. Another approach is to
physically sputter wafer 100 to remove any native oxide. These
latter two approaches are easily integrated in a cluster tool
system, so that the oxide-removal treatment can be performed in one
chamber and wafer 100 is then transferred to another chamber for
metal sputter without being exposed to air in between steps.
[0037] In some applications an out-gassing step may also be
included. Thus, an overall typical process for native oxide
reduction includes the following sequence of steps: a HF dip, IPA
drying and an out-gassing step. While out-gassing is usually
performed in a reaction chamber, in some applications it can be
performed in a load lock location as well
[0038] In any event, the cross section in FIG. 1 depicts wafer 100
after such native oxide reduction steps. Next, as shown in FIG. 2,
wafer 100 is placed in a first sputter deposition chamber where a
Cobalt (Co) layer 140 of about 10 nm is deposited over the entire
wafer using a substantially pure cobalt target in a noble gas
plasma environment. In a preferred approach, the first sputter
deposition chamber is part of a cluster tool described in more
detail with reference to FIG. 16 below.
[0039] As seen in FIG. 3, the wafer is then moved to a second
chamber to deposit a Co--Ti alloy cap layer 150 of about 15 nm
using a Co--Ti target also in a noble gas plasma environment. The
Co--Ti target is adapted to have a Ti content from about 20 to 80
atomic percent, preferably about 50 atomic percent. Of course, in
some reactors it may be possible to change targets without removing
wafer 100 from the first reaction chamber so that both the Co and
Co--Ti cap layer are formed in the same chamber.
[0040] While Ti is used in this preferred embodiment, it will be
apparent to those skilled in the art that other elements could be
used depending on the desired film qualities, compatibility with
subsequent deposition materials, etc., and provided such elements
can provide the same degree of protection from oxygen. For example,
any number of refractor metals may be suitable for a particular
application. Refractory metals such as Ta, W, Mo, Zr, Hf, Nb are
also known to mediate cobalt silicidation to form high quality
cobalt silicide films just as Ti does. In this regard, it should be
noted that the term "refractory metal" is not intended to limit the
invention to these metals, and those skilled in the art will
appreciate that other metals (positioned near these refractory
metals on a periodic table) are also entirely suitable for the
present invention.
[0041] After the Co--Ti capping, the wafer is transferred to an
anneal chamber. This anneal chamber can be integrated to the same
cluster tool that includes the aforementioned first and second
reaction chambers, or it can be located elsewhere because of the
protection afforded by Co--Ti cap layer 150. In those cases where
the anneal chamber is not integrated to the same cluster tool, cap
layer 150 is preferably formed as an amorphous layer. This can be
achieved using conventional mechanisms by controlling the
temperature of wafer 100 while depositing cap layer 150. As a
further refinement, a ternary target with a small addition of a
second refractory metal or a light element such as carbon can also
be used to improve the quality of cap layer 150.
[0042] As shown in FIG. 4, a first anneal is performed for a
relatively short period of time (about 60 seconds) and at about 500
to 650 degree centigrade in a nitrogen or an argon environment,
using a conventional heat lamp apparatus. The actual times and
temperatures will vary, of course, from heater to heater and for
any particular combination of materials/thicknesses can be easily
determined and optimized using routine skill. This first anneal
operation causes a number of reactions, both within Co--Ti layer
150, Co layer 140, and at interfaces with the underlying silicon
layers. For instance, Co layer 140 and silicon materials in the
underlying silicon areas (gate electrode 110 and Source/Drain
regions 135, 136) react to form certain compounds within layer 140,
as well as at an interface 160 therebetween, including CoSi and
Co2Si which represent high resistivity phase silicides.
[0043] In some environments and in certain process windows it is
conceivable that Titanium from Co--Ti layer 150 may be abstracted
by nitrogen to the surface, where it can react to form a Ti/TiN
layer (not shown). Since CoTi silicidation is a competing reaction
against such abstraction, however, this additional type of layer is
not expected to be a significant factor in embodiments of the
present invention.
[0044] Wafer 100 is then selectively etched as illustrated in FIG.
5 to remove metals and mixtures other than the silicides formed in
the prior step. Again, the various chemicals and procedures
required for this step are well-known in the art, and the present
invention is by no means limited in this respect.
[0045] As seen in FIG. 6, wafer 100 is then subjected to a second
anneal at about 750 to 900 degrees centigrade (in the same manner
as before) and with a time sufficient to complete the silicidation
process, that is, to transform the high resistance Co2Si and/or
CoSi phase materials to a lower resistance CoSi2 phase material. As
before, the optimal actual times and temperatures will vary, of
course, depending on the specific materials, thicknesses, etc. of
the deposited layers. This completes the formation of the cobalt
silicide layer 170. Thereafter, wafer 100 may undergo any number of
additional well-known processing steps (not shown) to provide
interlayer dielectrics, contacts, interconnects, etc., to device
105, and to complete fabrication of such device.
[0046] A cross sectional view of the result of the first anneal
treatment is shown in FIG. 15, which can be contrasted with the
result of the prior art at a similar stage shown in FIG. 14. As
seen in FIG. 5, the intermediate reaction products of the present
invention are similar, but the present invention instead
advanteageously initially deposits what is an end-result (Co--Ti)
of the prior art process. This means that the present process is
more predictable, because for a given amount of Co, a process
engineer can better determine how much intermediate product (CoSi
and Co2Si) will be formed.
[0047] While the Co--Ti alloy is less reactive to N2 than Ti, it is
nonetheless still sufficiently reactive to oxygen and moisture to
prevent any contamination problems. Thus, it performs well enough
to prevent any performance issues with the tesulting cobalt
silicide layer.
[0048] Moreover, like the Ti cap used in the prior art, the Co--Ti
layer 150 of the present invention can act as a source for some Ti
diffusion into the underlying Co layer 140. The presence of Ti
mediates the silicidation reaction, which raises the temperature
required to convert to the lower resistance CoSi2 phase, but it
nonetheless enhances the thermal stability of the resulting cobalt
silicide layer 170. At the same time, the Co--Ti cap layer 150 is
less reactive than a pure Ti cap on Co; this means that there is
less interaction between the cap layer and underlying Co films to
adversely affect the amount of Co that is available for the
silicidation reaction. This fact, in turn, means that process
control is improved because the final thickness of the resulting
silicide film is more easily controlled.
[0049] Furthermore, the resulting thickness can be very thin as
compared to a prior art process, because less Ti has to be involved
in the overall process. This also increases productivity, reduces
cycle time, etc. In the present approach, only about 80 to 100
Angstroms of Cobalt are required to react with 350 Angstroms of
silicon, resulting in an extremely dense combined silicide layer of
approximately 330 Angstroms after final silicidation.
Second Embodiment
[0050] A preferred method employed by a second embodiment of the
invention is depicted collectively in FIGS. 7 to 9. Unless
otherwise noted, like numerals for the second embodiment are
intended to refer to like structures as previously discussed in the
first embodiment above.
[0051] As before with the first embodiment, a wafer 100 having
dielectric surface and silicon surface is prepared. As before,
wafer 100 is processed using any number of well-known techniques to
remove or reduce native oxide.
[0052] As shown in FIG. 7, wafer 100 is then moved to a sputter
chamber to deposit a Co--Ti layer 150 using a Co--Ti alloy target
having a Ti content about 1 to 50 atomic percent (and preferably 1
to 10 percent) under an noble gas plasma environment, in this case,
preferably argon.
[0053] A first anneal is performed at about 500 to 650 degree
centigrade preferably in situ as seen in FIG. 8. This can be
achieved by integrating a heating apparatus to the sputter chamber,
such as a hot plate or a lamp. Thus, in this approach, an in-situ
salicidation is performed during sputtering, in what can be
considered a high temperature sputtering operation.
[0054] Alternatively, the first anneal could be performed in
another chamber within the cluster tool in a similar manner (i.e.,
with a hot plate or heating lamp). Since the Si surface is free of
oxide, and the ambient is free of N2, there is less tendency for Ti
to migrate to the surface in this embodiment.
[0055] Unlike the first embodiment, no additional first layer of Co
is deposited, because it is not necessary to do so. By carefully
controlling the amount of Ti in the Co--Ti alloy target, it is
possible to deposit a mixture that: (1) has sufficient Cobalt to
react effectively with the underlying silicon; (2) and yet also has
sufficient Ti to prevent contamination to the Cobalt from oxygen
and other reactants.
[0056] To minimize this second effect, the cluster tool in this
embodiment uses a noble gas such as argon for sputtering and
purging any vacuum systems prior to critical operations such as a
deposition operation. The point of using a noble gas purifier is
that it can be used to remove trace reactive gasses such as oxygen,
moisture and N2 before sputtering operations. In other words, it
cuts down significantly on the number of reactive products that can
adversely affect the underlying Co, so that less Ti is actually
needed for controlling oxygen and moisture contamination. For this
reason, in this embodiment, a target comprising 1-10 atomic percent
of Ti can be used preferably.
[0057] At the same time, the resulting Co--Ti alloy layer 150 is
sufficiently rich in Cobalt that it can react effectively to
silicide later with the underlying silicon areas. Accordingly, the
low percentage Ti alloy target provides enough Ti for forming a
Ti--mediated cobalt silicide film yet does not consume too much
cobalt by forming an Co--Ti intermetallic mixture. The Ti migrates
during the various reactions, however, and in the end resulting
silicide film, some residual Ti can be found in the cobalt
silicide.
[0058] Finally, because the initial layer 150 is not purely Cobalt,
it tends to react less with any initial residual oxide that may be
on the surface of wafer 100, or later contaminants. This means that
the overall process yield can be improved, because the operating
environment and starting conditions do not need to be quite so
strict or rigid.
[0059] After the first anneal wafer 100 is removed from the cluster
tool and subjected to selective etch (as before) to remove metals
other than silicide. The wafer is then rinsed, dried and subjected
to a second anneal (as before) to convert the high resistance Co2Si
and CoSi phase to low resistance CoSi2 phase as before, resulting
in the structure shown in FIG. 9. This structure is otherwise
identical in most respects to the resulting structure shown in FIG.
6.
[0060] The advantage of this second embodiment is the simplicity of
the number of steps, and their sequence, enhances the productivity
of the cluster tool. The cluster tool (FIG. 16) can process wafer
100 for many steps such as native oxide removal, Co--Ti alloy
sputtering and the first anneal without exposing to air. The Co--Ti
alloy layer 150 provides a Ti--mediated cobalt silicide layer 170
that has good thermal stability against agglomeration of the CoSi2
film under high temperature. In addition, the Co--Ti alloy layer
150 also provides some process margin such that neither native
oxide removal nor the chamber environments need to be perfect.
[0061] Because the above embodiment uses an in-situ salicidation
approach (in the form of high temperature sputtering--in this case,
sputtering with lamp heating) it also has great potential to reduce
leakage current of very shallow source/dtain junctions required in
next generation technologies.
Third Embodiment
[0062] A preferred method employed by a third embodiment of the
invention is depicted collectively in FIGS. 10 to 13. Unless
otherwise noted, like numerals for the second embodiment are
intended to refer to like structures as previously discussed in the
first embodiment above.
[0063] As above, wafer 100 is subjected to any number of procedures
to remove or reduce native oxide. Next, as shown in FIG. 10, the
wafer is moved to a sputter chamber to deposit a first layer 150
consisting of about 5 to 15 nm of a Co--Ti alloy, using a Co--Ti
alloy target including about 20 to 80 atomic percent of Ti.
[0064] Next, in FIG. 11, wafer 100 is then moved to a second
sputter chamber (preferably in the same cluster tool) to deposit
either a Co layer 151, or a Co--Ti alloy layer 151 having a richer
(higher percentage) Co content than the first Co--Ti layer 150.
Both layers 150, 151 are deposited under noble gas environment
plasma. In the second deposition wafer 100 is heated to about 500
to 650 degree centigrade, that is, an in situ anneal is performed
within the sputtering chamber. The first Co--Ti alloy target is
preferred to have a Ti content near or higher than 50 atomic
percent so as to reduce an effective amount of Co available to form
a silicide when heated in the second chamber. The second sputtering
operation supplies additional Co to the wafer surface allowing
Co2Si or CoSi to be formed during the process since heat is also
provided. In this way, the final thickness of layers 150, 151 is
easier to control.
[0065] As before, wafer 100 is treated with a selective etch to
remove metals other than silicide. The wafer is then rinsed, dried
and annealed for the second time as shown in FIG. 12 to convert the
Co2Si and CoSi phase materials to the lower resistance CoSi2 phase.
The resulting layer 170 of FIG. 13 is substantially the same as
that shown already in FIGS. 6 and 9.
Cluster Tool Embodiment
[0066] An improved semiconductor processing system 1000 is depicted
generally in FIG. 16, which is based generally on a conventional
cluster tool system such as the Endura.RTM. HP PVD System sold by
Applied Materials. As seen generally in this figure, system 1000
includes a set of loadlock chambers 1010 and 1020 for
receiving/pre-processing incoming wafers and/or outputting finished
wafers. For example, outgassing operations can typically be
performed in such loadlock chambers. A variety of processing
chambers 1030-1080, and wafer handling stations 1100 and 1200 are
also part of the system. To accommodate the processes of the
present invention, system 1000 includes one or more modified
sputter chambers 1040, in which a Co--Ti target is used (in lieu of
a conventional sputtering target) or a combination of separate
stations using both a Co-based target and a Co--Ti alloy target are
used for depositing separate Co and Co--Ti layers.
[0067] The Endura.RTM. system also already includes a precleaning
station, where one or more of the aforementioned wafer cleaning
operations can be performed. In addition, one or more sputter
chambers 1050 (or 1060 or 1070) also include some form of heating
assembly, so that heating operations, including in-situ anneals,
can be performed directly on wafers 100 without having to remove
the wafers from the cluster tool. When sputter chamber 1040 (with
an alloy target) includes an integrated heating lamp, for example,
a high temperature sputtering operation noted earlier can be
conveniently performed for in-situ salicidation. Wafer handling
stations 1100 and 1200 ensure that the wafers move smoothly from
station to station without breaking vacuum, and so as to avoid
contamination.
[0068] While this invention has been described with reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. It will be clearly understood by
those skilled in the art that foregoing description is merely by
way of example and is not a limitation on the scope of the
invention, which may be utilized in many types of integrated
circuits made with conventional processing technologies. Various
modifications and combinations of the illustrative embodiments, as
well as other embodiments of the invention, will be apparent to
persons skilled in the art upon reference to the description. Such
modifications and combinations, of course, may use other features
that are already known in lieu of or in addition to what is
disclosed herein. It is therefore intended that the appended claims
encompass any such modifications or embodiments. While such claims
have been formulated based on the particular embodiments described
herein, it should be apparent the scope of the disclosure herein
also applies to any novel and non-obvious feature (or combination
thereof disclosed explicitly or implicitly to one of skill in the
art, regardless of whether such relates to the claims as provided
below, and whether or not it solves and/or mitigates all of the
same technical problems described above. Finally, the applicants
further reserve the right to pursue new and/or additional claims
directed to any such novel and non-obvious features during the
prosecution of the present application (and/or any related
applications).
* * * * *