U.S. patent application number 11/172783 was filed with the patent office on 2006-01-19 for semiconductor device, semiconductor device module and method of manufacturing the semiconductor device.
This patent application is currently assigned to NEC ELECTRONICS CORPORATION. Invention is credited to Takuo Funaya, Takashi Miyazaki.
Application Number | 20060012038 11/172783 |
Document ID | / |
Family ID | 35598606 |
Filed Date | 2006-01-19 |
United States Patent
Application |
20060012038 |
Kind Code |
A1 |
Miyazaki; Takashi ; et
al. |
January 19, 2006 |
Semiconductor device, semiconductor device module and method of
manufacturing the semiconductor device
Abstract
A reliable semiconductor device including support bumps so as to
adequately seal the region between the chips is to be provided. The
semiconductor device includes a semiconductor chip; a bump formed
on an upper face of the semiconductor chip; and a plurality of
support bumps formed along a circumference of the region where the
bump is provided, formed on the upper face of the semiconductor
chip; and a flow path for a sealing resin is provided between the
plurality of support bumps, so as to connect the region where the
bump is provided and a periphery region of the semiconductor
chip.
Inventors: |
Miyazaki; Takashi;
(Kanagawa, JP) ; Funaya; Takuo; (Tokyo,
JP) |
Correspondence
Address: |
YOUNG & THOMPSON
745 SOUTH 23RD STREET
2ND FLOOR
ARLINGTON
VA
22202
US
|
Assignee: |
NEC ELECTRONICS CORPORATION
KANAGAWA
JP
NEC CORPORATION
TOKYO
JP
|
Family ID: |
35598606 |
Appl. No.: |
11/172783 |
Filed: |
July 5, 2005 |
Current U.S.
Class: |
257/737 ;
257/786; 257/E21.503; 257/E23.021; 257/E25.013; 438/612;
438/613 |
Current CPC
Class: |
H01L 21/563 20130101;
H01L 2224/32145 20130101; H01L 24/10 20130101; H01L 2224/73104
20130101; H01L 2225/06593 20130101; H01L 2224/92125 20130101; H01L
24/32 20130101; H01L 2224/83102 20130101; H01L 2225/06582 20130101;
H01L 2224/13 20130101; H01L 24/29 20130101; H01L 2924/01005
20130101; H01L 2224/16145 20130101; H01L 2225/06513 20130101; H01L
2224/05624 20130101; H01L 24/91 20130101; H01L 2224/04042 20130101;
H01L 2224/83193 20130101; H01L 2924/01029 20130101; H01L 2924/01033
20130101; H01L 2224/48227 20130101; H01L 25/0657 20130101; H01L
2224/16225 20130101; H01L 2224/29111 20130101; H01L 2224/73103
20130101; H01L 2224/73204 20130101; H01L 2924/0105 20130101; H01L
24/16 20130101; H01L 2924/01082 20130101; H01L 2224/0401 20130101;
H01L 24/28 20130101; H01L 2224/81141 20130101; H01L 2224/81193
20130101; H01L 2924/01027 20130101; H01L 2224/06051 20130101; H01L
2224/29144 20130101; H01L 24/83 20130101; H01L 2224/13099 20130101;
H01L 2224/30155 20130101; H01L 2924/01078 20130101; H01L 2924/01079
20130101; H01L 2924/0132 20130101; H01L 24/06 20130101; H01L
2224/73215 20130101; H01L 2924/15311 20130101; H01L 2224/29076
20130101; H01L 2224/83191 20130101; H01L 2224/13111 20130101; H01L
2225/0651 20130101; H01L 2924/01047 20130101; H01L 2924/014
20130101; H01L 2224/0615 20130101; H01L 2224/1415 20130101; H01L
2924/01013 20130101; H01L 24/13 20130101; H01L 24/14 20130101; H01L
24/81 20130101; H01L 2924/01006 20130101; H01L 2224/0603 20130101;
H01L 2224/1411 20130101; H01L 2224/29011 20130101; H01L 2224/48091
20130101; H01L 2224/73207 20130101; H01L 2224/04026 20130101; H01L
2224/2919 20130101; H01L 2224/73203 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2924/0132 20130101; H01L
2924/01047 20130101; H01L 2924/0105 20130101; H01L 2224/13111
20130101; H01L 2924/01047 20130101; H01L 2924/00014 20130101; H01L
2224/2919 20130101; H01L 2924/00014 20130101; H01L 2224/13
20130101; H01L 2924/00 20130101; H01L 2224/73204 20130101; H01L
2224/16145 20130101; H01L 2224/32145 20130101; H01L 2924/00
20130101; H01L 2224/05624 20130101; H01L 2924/00014 20130101; H01L
2224/29144 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/737 ;
438/613; 257/786; 438/612 |
International
Class: |
H01L 21/44 20060101
H01L021/44; H01L 23/52 20060101 H01L023/52 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 8, 2004 |
JP |
2004-201648 |
Claims
1. A semiconductor device comprising: a semiconductor chip; a bump
formed on an upper face of said semiconductor chip; a plurality of
support bumps formed along a circumference of a region where said
bump is provided, formed on said upper face of said semiconductor
chip; and a flow path for a sealing resin provided between said
plurality of support bumps so as to connect said region where said
bump is provided and a periphery region of said semiconductor
chip.
2. The semiconductor device according to claim 1, wherein said bump
is electrically connected to said semiconductor chip; and said
support bumps are not electrically connected to said semiconductor
chip.
3. The semiconductor device according to claim 1, wherein said
support bumps are made of a metal film.
4. The semiconductor device according to claim 1, further
comprising an external electrode provided on said semiconductor
chip; and wherein said flow path for said sealing resin is provided
in a region other than a region where said external electrode is
provided.
5. The semiconductor device according to claim 1, wherein said
semiconductor chip is a DRAM; and said bump is provided on a region
where a memory cell of said DRAM is not provided.
6. The semiconductor device according to claim 1, wherein said
semiconductor chip is a logic chip including DRAM; and said bump is
provided in a region where a memory cell of said logic chip
including DRAM is not provided.
7. The semiconductor device according to claim 1, wherein said
sealing resin is a photosensitive sealing resin.
8. The semiconductor device according to claim 1, wherein said
support bumps are made of a fusible metal.
9. The semiconductor device according to claim 8, wherein said
fusible metal is a solder.
10. The semiconductor device according to claim 1, wherein each of
said support bumps comprises group of fine bumps.
11. The semiconductor device according to claim 1, wherein an area
of said support bumps is larger than an area of said bump.
12. The semiconductor device according to claim 1, wherein said
support bumps are disposed along each side of a rectangular-shaped
region where said bump is provided.
13. The semiconductor device according to claim 1, wherein said
bump is provided in a rectangular-shaped region formed on an upper
face of said semiconductor chip; and said flow path for said
sealing resin is radially disposed from said rectangular-shaped
region.
14. The semiconductor device according to claim 1, wherein a
material that constitutes said bump and a material that constitutes
said plurality of support bumps are different.
15. A semiconductor device module comprising two or more
semiconductor devices according to claim 1 formed in multilayer,
wherein, in at least a pair of semiconductor devices among said
semiconductor devices, said bump provided on one of said pair of
semiconductor devices and said bump provided on the other of said
pair are in contact with each other.
16. The semiconductor device module according to claim 15, wherein
said semiconductor chip provided in said one of said pair of
semiconductor devices is a logic chip.
17. A method for manufacturing a semiconductor device, comprising:
preparing a first semiconductor chip; forming a first bump on an
upper face of said first semiconductor chip and forming a plurality
of first support bumps along a circumference of a region where said
first bump is provided, on said upper face of said first
semiconductor chip, and forming a flow path for a sealing resin
between said first support bumps, so as to connect a region where
said first bump is provided and a periphery region of said first
semiconductor chip; introducing a sealing resin on said first
semiconductor chip; preparing a second semiconductor chip; forming
a second bump on an upper face of said second semiconductor chip
and forming a plurality of second support bumps along a
circumference of a region where said second bump is provided, on
said upper face of said second semiconductor chip, and forming a
flow path for a sealing resin between said plurality of second
support bumps, so as to connect a region where said second bump is
provided and a periphery region of said second semiconductor chip;
and sealing said first semiconductor chip and said second
semiconductor chip with said sealing resin, with said first bump
and said second bump disposed in contact with each other and with
said plurality of first support bumps and said plurality of second
support bumps respectively disposed in contact with each other.
18. The method according to claim 17, wherein said sealing includes
a step in which a portion of said sealing resin is moved toward
outside of said region where said first bump is provided through
said flow path for said sealing resin toward said periphery region
of said first semiconductor chip and said periphery region of said
second semiconductor chip.
19. The method according to claim 17, wherein said sealing resin is
a photosensitive sealing resin.
20. The method according to claim 19, further comprising:
patterning said photosensitive sealing resin by exposure and
development of the photosensitive sealing resin.
Description
[0001] This application is based on Japanese patent application No.
2004-201648, the content of which is incorporated hereinto by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device, a
semiconductor device module and a method of manufacturing the
semiconductor device.
[0004] 2. Related Art
[0005] In accordance with the ongoing reduction in dimensions and
weight of electronic devices, demand for micronization of the
electronic components to be employed is continuously increasing. On
the other hand, the demand for higher performance, such as a high
speed operation and larger memory capacity, has also been
increasing. Accordingly, an SiP (System in Package) in which a
plurality of semiconductor chips electrically connected to one
another is integrated has been developed, as a method for system
integration at the device level that can satisfy both of the
micronization in dimensions and higher performance.
[0006] A primary part of the SiP technique is a Chip-On-Chip
combination technique, which includes disposing so as to oppose
each main face of devices having a different optimum designing
parameter in a wafer process, such as a CMOS logic and a DRAM, or
devices that are difficult to integrate in a wafer process, such as
a silicon device and a compound semiconductor device, and
electrically connecting the devices via bump electrodes in a
shortest distance. Such a Chip-On-Chip technique is expected to
achieve a SiP that offers a higher performance and a higher
operation speed.
[0007] However, some issues to be addressed have already been
discovered in such a technique, such as deterioration in strength
of each individual bump due to a reduction in size, or difficulty
in injecting a sealing resin required for protection from an
external environment, which are supposed to come up when still
further micronization and improvement in performance are required
in future and the bump electrode are compelled to be made
smaller.
[0008] Therefore, a related art such as JP-A No. 2002-26238
proposes employing a bump for preventing a chip from bending
backward, to thereby protect an electrode bump formed according to
the chip-on-chip technique. In JP-A No. 2002-26238, an upper chip
includes upper bumps arranged along a periphery region of an
interconnect forming surface, and a lower chip has lower bumps
located at positions corresponding to the upper bumps.
[0009] In addition, the lower chip and the upper chip both include,
apart from the lower bumps and the upper bumps, a reaction force
blocking lower bump and a reaction force blocking upper bump
respectively, designed to sustain a reaction force generated by the
chip in a direction of bending backward, located at a central
portion of the chip or inside the periphery region thereof. When
stacking the lower bumps and the upper bumps so as to put the bumps
in contact, the reaction force blocking lower bump and the reaction
force blocking upper bump are also put into mutual contact.
SUMMARY OF THE INVENTION
[0010] However, it has now been discovered that the conventional
techniques, including the technique according to the above
literature, has a room for improvement in the following
aspects.
[0011] Firstly referring to FIG. 9, the structure and dimension
size of a reaction force receiver bump 7 are restricted, in the
case of providing a sealing resin 4 between bumps (upper bumps 2
and lower bumps 6) and between chips (a upper chip 1 and a lower
chip 5), after combining them. Usually, a capillary effect is
utilized to introduce the sealing resin 4 into a space among the
bumps and chips from one of the sides of the upper chip 1, when
subsequently injecting the sealing resin 4. However, in case that,
the structure and size of the bumps are not uniform, the moving
speed of the sealing resin 4 is uneven depending on locations in
the region to be sealed, and resultantly a void may be left
inside.
[0012] Secondly, such restriction on the structure and size of the
reaction force receiver bump 7 due to above reason results in
vulnerability of the reaction force receiver bump 7 against an
external deforming force.
[0013] Thirdly, a position to arrange the bumps may be restricted,
depending on the type of the chip to be combined by the
chip-on-chip technique. For example, in order to form the bumps on
a memory cell, a rerouting process has to be performed in addition
to an established process. Therefore, the pad electrodes are often
disposed in a region other than a region of a memory cell, which
generates a restriction that, as in a DRAM chip 8 shown in FIG. 10,
bumps 2 can only be located in a central portion of the DRAM chip
8, since memory cell regions 9 are formed along a periphery region
thereof. When the bumps 2 are thus concentrated in a central region
of the DRAM chip 8, supporting members that sustain a peripheral
portion of an upper chip are unavailable when performing the
chip-on-chip combination technique by a flip chip method.
Consequently, the upper chip may be inclined and thereby damaged,
during the chip-on-chip technique process.
[0014] Further, in a logic chip including DRAM in recent year,
arrangement of an internal interconnect on a memory cell is
restricted. Accordingly, such a chip is not free from the foregoing
problem either.
[0015] For supporting an upper chip, a technique of providing a
dummy bump that supports the chip has been proposed, for example in
JP-A No. 2002-26238 described above. However, when the position
that the bumps are formed is restricted in a central region of the
chip, simply applying the technique of JP-A No. 2002-26238 makes it
difficult to introduce a sealing resin after the flip chip bonding,
since the dummy bumps are disposed around the bumps.
[0016] According to the present invention, there is provided a
semiconductor device comprising: a semiconductor chip; a bump
formed on an upper face of the semiconductor chip; a plurality of
support bumps formed along a circumference of a region where the
bump is provided, formed on the upper face of the semiconductor
chip; and a flow path for a sealing resin provided between the
plurality of support bumps so as to connect the region where the
bump is provided and a periphery region of the semiconductor
chip.
[0017] In the present invention, the support bump herein refers to
a bump that serves as a support member for another bump, when
bonding semiconductor chips via the bumps.
[0018] In the semiconductor device thus constructed, the support
bump can be provided even when the bumps are provided around a
central region of the semiconductor chip. Also, by providing the
flow path for a sealing resin between the region where the bumps
are provided and the periphery region of the semiconductor chip, it
is possible to introduce the sealing resin uniformly and thereby to
suppress generation of a void in the sealing resin. Consequently, a
semiconductor device with higher reliability can be provided.
[0019] According to the present invention, there is provided a
semiconductor device module comprising two or more semiconductor
devices according to the present invention formed in multilayer,
wherein, in at least a pair of semiconductor devices among the
semiconductor devices, the bump provided on one of the pair of
semiconductor devices and the bump provided on the other of the
pair are in contact with each other.
[0020] The semiconductor device thus constructed, in which at least
two semiconductor devices having a bump are formed such that the
bumps contact each other, achieves a combination of the
semiconductor devices that have the above characteristics.
[0021] According to the present invention, there is provided a
method for manufacturing a semiconductor device, comprising:
preparing a first semiconductor chip; forming a first bump on an
upper face of the first semiconductor chip and forming a plurality
of first support bumps along a circumference of a region where the
first bump is provided, on the upper face of the first
semiconductor chip, and forming a flow path for a sealing resin
between the first support bumps, so as to connect a region where
the first bump is provided and a periphery region of the first
semiconductor chip; introducing a sealing resin on the first
semiconductor chip; preparing a second semiconductor chip; forming
a second bump on an upper face of the second semiconductor chip and
forming a plurality of second support bumps along a circumference
of a region where the second bump is provided, on the upper face of
the second semiconductor chip, and forming a flow path for a
sealing resin between the plurality of second support bumps, so as
to connect a region where the second bump is provided and a
periphery region of the second semiconductor chip; and sealing the
first semiconductor chip and the second semiconductor chip with the
sealing resin, with the first bump and the second bump disposed in
contact with each other and with the plurality of first support
bumps and the plurality of second support bumps respectively
disposed in contact with each other.
[0022] According to such method, the support bump can be provided
even when the first bumps are provided around a central region of
the first semiconductor chip. Also, by providing the flow path for
a sealing resin between the region where the first bumps are
provided and the periphery region of the first semiconductor chip,
it is possible to introduce the sealing resin uniformly and thereby
to suppress generation of a void in the sealing resin. Further, the
first semiconductor ship and the second semiconductor can be sealed
with the first bump and the second bump contacting each other, and
with the plurality of first support bumps and the plurality of
second support bumps respectively contacting each other.
Consequently, a semiconductor device with higher reliability can be
provided.
[0023] According to the present invention, a semiconductor chip
with high reliability including a structure of support bumps so as
to adequately seal the region between the chips using sealing rejin
can be obtained.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other objects, advantages and features of the
present invention will be more apparent from the following
description taken in conjunction with the accompanying drawings, in
which:
[0025] FIG. 1A is a schematic plan view showing a structure of an
unbonded upper chip, in a semiconductor device according to an
embodiment of the present invention;
[0026] FIG. 1B is a cross-sectional view taken along the line A-A'
of FIG. 1A;
[0027] FIG. 2A is a schematic plan view showing a structure of an
unbonded lower chip, in the semiconductor device according to the
embodiment;
[0028] FIG. 2B is a cross-sectional view taken along the line A-A'
of FIG. 2A;
[0029] FIG. 3 is a schematic cross-sectional view showing the upper
chip and the lower chip bonded, in the semiconductor device
according to the embodiment;
[0030] FIG. 4 is a schematic plan view showing the upper chip and
the lower chip bonded, in the semiconductor device according to the
embodiment;
[0031] FIGS. 5A to 5D are schematic cross-sectional views for
explaining a method of manufacturing the semiconductor device
according to the embodiment;
[0032] FIGS. 6E to 6G are schematic cross-sectional views for
explaining a method of manufacturing the semiconductor device
according to the embodiment;
[0033] FIG. 7 is a schematic plan view showing the semiconductor
device according to the embodiment;
[0034] FIG. 8 is a schematic plan view showing the semiconductor
device according to the embodiment;
[0035] FIG. 9 is a schematic cross-sectional view showing a
structure of a conventional semiconductor device;
[0036] FIG. 10 is a schematic plan view showing a structure of a
conventional semiconductor device;
[0037] FIG. 11 is a schematic plan view showing a semiconductor
device according to another embodiment of the present invention;
and
[0038] FIG. 12 is a schematic plan view showing a semiconductor
device according to another embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0039] The present invention will be now described herein with
reference to illustrative embodiments. Those skilled in the art
will recognize that many alternative embodiments can be
accomplished using the teachings of the present invention and that
the invention is not limited to the embodiments illustrated for
explanatory purposed.
[0040] Hereunder, an embodiment of the present invention will be
described referring to the accompanying drawings. Throughout the
drawings, similar constituents are given an identical numeral, and
detailed description thereof will be not presented where
appropriate.
[0041] A semiconductor device shown in FIGS. 1A and 1B includes a
semiconductor chip (upper chip 101); a bump (upper bump 102) formed
on an upper face of the semiconductor chip; a plurality of support
bumps (support upper bumps 103) formed along a circumference of a
region where the bump is provided, formed on the upper face of the
semiconductor chip; and a flow path for a sealing resin (sealing
resin flow path 108) provided between the plurality of support
bumps so as to connect the region where the bump is provided and a
periphery region of the semiconductor chip.
[0042] A semiconductor device shown in FIGS. 2A and 2B includes a
semiconductor chip (lower chip 105); a bump (lower bump 106) formed
on an upper face of the semiconductor chip; a plurality of support
bumps (support lower bumps 107) formed along a circumference of a
region where the bump is provided, formed on the upper face of the
semiconductor chip; and a flow path for a sealing resin (sealing
resin flow path 108) provided between the plurality of support
bumps so as to connect the region where the bump is provided and a
periphery region of the semiconductor chip.
[0043] In a multi-layered chip 100 shown in FIG. 3, in at least a
pair of semiconductor devices among the semiconductor devices that
at least two semiconductor devices (upper chip 101 and lower chip
105) are formed, the bump (upper bump 102) provided on one (upper
chip 101) of the pair of semiconductor devices and the bump (lower
bump 106) provided on the other (lower chip 105) of the pair are in
contact with each other.
[0044] A method for manufacturing the multi-layered chip 100 shown
in FIGS. 5A to 6G includes preparing a first semiconductor chip
(upper chip 101); forming a first bump (upper bump 102) on an upper
face of the first semiconductor chip and forming a plurality of
first support bumps (support upper bumps 103) along a circumference
of a region where the first bump is provided, on the upper face of
the first semiconductor chip, and forming a flow path for a sealing
resin (sealing resin flow path 108) between the first support
bumps, so as to connect a region where the first bump is provided
and a periphery region of the first semiconductor chip; introducing
a sealing resin 104 on the first semiconductor chip; preparing a
second semiconductor chip (lower chip 105); forming a second bump
(lower bump 106) on an upper face of the second semiconductor chip
and forming a plurality of second support bumps (support lower
bumps 107) along a circumference of a region where the second bump
is provided, on the upper face of the second semiconductor chip,
and forming a flow path for a sealing resin (sealing resin flow
path 108) between the plurality of second support bumps, so as to
connect a region where the second bump is provided and a periphery
region of the second semiconductor chip; and sealing the first
semiconductor chip and the second semiconductor chip with the
sealing resin 104, with the first bump and the second bump disposed
in contact with each other and with the plurality of first support
bumps and the plurality of second support bumps respectively
disposed in contact with each other.
[0045] FIGS. 1A, 1B and FIGS. 2A, 2B illustrate a structure of the
semiconductor device according to this embodiment. In the present
embodiment, a photosensitive resin is employed as the sealing resin
104.
[0046] FIGS. 1A and 1B are views showing a structure of the upper
chip 101, which is a semiconductor chip. FIG. 1A is a plan view of
the upper chip 101, while FIG. 1B is a cross-sectional view of the
upper chip 101 taken along the line A-A' of FIG. 1A. In a central
portion of the upper chip 101, a plurality of upper bumps 102
constituted of for example gold is arranged in contact with pad
electrodes 109 provided on a chip wafer 110, and the support upper
bumps 103 are provided in a region along a periphery of the
rectangular region where the upper bumps 102 are provided, such as
a region between the area where the upper bumps 102 are provided
and a periphery region of the upper chip 101. For example, as shown
in FIG. 1A, the support upper bump 103, representing a support bump
constituted of a metal film such as gold, is disposed in four
separate portions along each side of the rectangular region where
the upper bumps 102 are provided. In FIG. 1A, the cross-sectional
area of the support upper bump 103 taken parallel to the face of
the upper chip 101 is larger than the cross-sectional area of the
upper bump 102 taken parallel to the face of the upper chip 101
(that is the area of the support upper bump 103 is larger than that
of the upper bump 102). In the present embodiment, since the
support upper bump 103 is in contact with the pad electrode 109,
the support upper bump 103 serves for electrical connection between
the upper chip 101 and another chip. Further, the support upper
bump 103 may be in no contact with the pad electrode 109. In other
words, the support upper bump 103 may serve nothing for electrical
connection between the upper chip 101 and another chip. As examples
of the upper chip 101, a logic chip, a DRAM, or a logic chip
including DRAM, in vicinity of periphery region of which a memory
cell is often provided, is employed.
[0047] On the upper chip 101, flow paths for the sealing resin 104
are radially disposed from a central portion where the upper bumps
102 are provided, so as to connect between the rectangular-shaped
region where the upper bumps 102 are provided and the pepiphery
region of the upper chip 101. In other words, a region (space) in
which the sealing resin 104 can be disposed is provided, between
the rectangular-shaped region where the upper bumps 102 are
provided in the vicinity of the central portion of the upper chip
101 and the periphery region of the upper chip 101. Accordingly,
the sealing resin 104 patterned through an exposure and developing
process is selectively disposed between the upper bump 102, between
the support upper bump 103, between the upper bumps 102 and the
support upper bumps 103, and in a portion of a circumference of the
support upper bumps 103 (that is, the periphery region of the upper
chip 101). Also, in the present embodiment, the sealing resin 104
is provided on the chip wafer 110 in a greater thickness than the
thickness of the upper bumps 102 and the support upper bumps 103.
Also, in the present embodiment, the sealing resin 104 is a
photosensitive resin.
[0048] FIGS. 2A and 2B are views showing a structure of the lower
chip 105, which is a semiconductor chip. FIG. 2A is a plan view of
the lower chip 105, while FIG. 2B is a cross-sectional view of the
lower chip 105 taken along the line A-A' of FIG. 2A. In a central
portion of the lower chip 105, a plurality of lower bumps 106
constituted of for example gold is arranged in contact with pad
electrodes 109 provided on a chip wafer 110, and the support lower
bumps 107 are provided in a region along a periphery of the
rectangular-shaped region where the lower bumps 106 are provided,
such as a region between the area where the lower bumps 106 are
provided and a periphery region of the lower chip 105. For example,
as shown in FIG. 2A, the support lower bump 107, representing a
support bump constituted of a metal film such as gold, is disposed
in four separate portions along each side of the rectangular-shaped
region where the lower bumps 106 are provided. In FIG. 2A, the
cross-sectional area of the support lower bump 107 taken parallel
to the face of the lower chip 105 is larger than the
cross-sectional area of the lower bump 106 taken parallel to the
face of the lower chip 105 (the area of the support lower bump 107
is larger than that of the lower bump 106). Also, the lower bumps
106 and the support lower bumps 107 are disposed at positions
respectively corresponding to the upper bumps 102 and the support
upper bumps 103 provided on the upper chip 101. In the present
embodiment, since the support lower bump 107 is in contact with the
pad electrode 109, the support lower bump 107 serves for electrical
connection between the lower chip 105 and another chip. Further,
the support lower bump 107 may be in no contact with the pad
electrode 109. In other words, the support lower bump 107 may serve
nothing for electrical connection between the lower chip 105 and
another chip. As examples of the lower chip 105, a logic chip, a
DRAM, or a logic chip including DRAM, in vicinity of periphery
region of which a memory cell is often provided, is employed.
[0049] FIG. 3 is a cross-sectional view showing a multi-layered
chip 100 connected electrically the upper chip 101 and the lower
chip 105. The upper chip 101 and the lower chip 105 is electrically
connected by disposing the upper bumps 102 provided on the upper
chip 101 and the lower bumps 106 provided on the lower chip 105 so
as to contact each other. Also, the support upper bumps 103
provided on the upper chip 101 and the support lower bumps 107
provided on the lower chip 105 are disposed in contact with each
other. Also, in the present embodiment, the support upper bumps 103
and the support lower bumps 107 are disposed in contact with the
pad electrode 109, thus to serve for the electrical connection
between the upper chip 101 and the lower chip 105, while an
embodiment wherein the support bumps are not in contact with the
pad electrode 109, and hence not contributing for the electrical
connection between the upper chip 101 and the lower chip 105, is
also effective according to the present invention. Further, when
disposing the upper bump 102 and the lower bump 106 in contact with
each other, as well as the support upper bump 103 and the support
lower bump 107 in contact with each other, the region around the
upper bumps 102, the region around the lower bumps 106, the region
around the support upper bumps 103, the region around the support
lower bumps 107, and the region between the upper chip 101 and the
lower chip 105 are sealed at a time by the sealing resin 104
provided in advance, the region between the upper bumps 102, the
region between the support upper bumps 103, the region between the
upper bumps 102 and the support upper bumps 103, and a portion of a
circumference of the support upper bumps 103 (that is, the
periphery region of the upper chip 101) on the side of the upper
chip 101.
[0050] Here, the sealing resin 104 provided in advance on the upper
chip 101 is supplied with a thickness greater than a distance
between the lower face of the upper chip 101 and the upper face of
the lower chip 105, determined when the upper chip 101 and the
lower chip 105 are bonded as shown in FIG. 3. Accordingly, the
multi-layered chip 100 has a structure that, when the upper chip
101 and the lower chip 105 are bonded, the sealing resin 104 is
moved, and a surplus portion of the sealing resin 104 is moved
toward the outside of the upper chip 101 and the lower chip 105
through the sealing resin flow path 108, that is a flow path of the
sealing resin 104 provided between the support upper bump 103 and
the support lower bump 107.
[0051] FIG. 4 is a perspective plan view from the side of the upper
chip 101, showing the structure of the multi-layered chip 100 of
FIG. 3, which is a chip-on-chip type semiconductor device bonded
the upper chip 101 disposed the upper bumps 102, support upper
bumps 103 and the photosensitive sealing resin 104, with the lower
chip 105 disposed the lower bumps 106, and the support lower bumps
107. As shown in FIGS. 3 and 4, the upper chip 101 and the lower
chip 105 are electrically connected, by being connected between the
upper bump 102 and the lower bump 106 in contact with each
other.
[0052] Hereunder, a manufacturing process of the multi-layered chip
100 according to the present embodiment will be described referring
to FIGS. 5A to 5D and 6E to 6G. In the present embodiment, it is
referred to a case of manufacturing two upper chips 101 as shown in
FIGS. 5A to 5D, while one upper chip 101 may be manufactured, or
three or more of the upper chips may be manufactured.
[0053] Firstly, referring to FIG. 5A, an upper chip wafer 110
having a pad electrode 109 made of aluminum or the like is
prepared.
[0054] Then, referring to FIG. 5B, an upper bump 102 and a support
upper bump 103 are formed on the pad electrode 109 on the upper
chip wafer 110, by plating or the like. Here, the support upper
bump 103 is provided in a region along a circumstance of a region
of for a rectangular-shaped region where the upper bump 102 is
provided, such as a region between the area where the upper bump
102 is provided and a periphery region of the upper chip wafer 110
or the like. Also, the upper bump 102 and the support upper bump
103 can be simultaneously formed by a plating technique. In the
present embodiment, since the support upper bump 103 is formed on
the pad electrode 109, the support upper bump 103 serves to achieve
electrical connection between the upper chip 101 (FIG. 1) and
another chip. Further, the support upper bump 103 may be in no
contact with the pad electrode 109. In other words, the support
upper bump 103 may serve nothing for electrical connection between
the upper chip 101 and another chip.
[0055] Next, as shown in FIG. 5C, a photosensitive sealing resin
104 is supplied on the chip wafer 110. The sealing resin 104 is
supplied so as to cover the upper bump 102 and the support upper
bump 103. Here, on the upper chip 101 shown in FIG. 1, a flow path
108 for the sealing resin 104 is provided, so as to connect the
region where the upper bump 102 is provided and a periphery region
of the upper chip 101. In other words, a region (space) for
disposing the sealing resin 104 is provided, in a region between a
vicinity of a central portion of the upper chip 101 where the upper
bump 102 is provided and a periphery region of the upper chip 101
or the like. Accordingly, the sealing resin 104 can be supplied on
a region between the upper bumps 102, a region between the support
upper bumps 103, a region between the upper bump 102 and the
support upper bump 103, and a portion of the circumference of the
support upper bump 103 (periphery region of the upper chip 101). As
methods of supplying the sealing resin 104, a spin coating process
and a resin sheet forming process is employed.
[0056] Next, as shown in FIG. 5D, a predetermined patterning is
performed by exposure and development of the photosensitive sealing
resin 104.
[0057] Next, referring to FIG. 6E, a lower chip 105 is prepared.
The lower chip 105 is provided with a lower bump 106 and a support
lower bump 107, at the respective positions corresponding to the
upper bump 102 and the support upper bump 103 on the upper chip
101. The manufacturing process of the bumps on the lower chip 105
is the approximately same as the process for the upper chip 101
described referring to FIGS. 5A and 5B, except that the sealing
resin 104 is not supplied.
[0058] Next, as shown in FIG. 6F, the lower chip 105 and the upper
chip 101, which is divided into a single piece by dicing, are
bonded via the upper bump 102, the support upper bump 103, the
lower bump 106 and the support lower bump 107, and the lower chip
105 and the upper chip 101 are electrically connected. Also, with
the sealing resin 104 provided on the side of the upper chip 101,
the space between the upper chip 101 and the lower chip 105, the
space between the upper bump 102 and the lower bump 106, and the
space between the support upper bump 103 and the support lower bump
107 are sealed at a time. More specifically, with the sealing resin
104 provided in advance in a region between the upper bumps 102, a
region between the support upper bumps 103, a region between the
upper bump 102 and the support upper bump 103, and a portion of a
circumference of the support upper bump 103 (periphery region of
the upper chip 101), a region around the upper bump 102, a region
around the lower bump 106, a region around the support upper bump
103, a region around the support lower bump 107, and a region
between the upper chip 101 and the lower chip 105 are
simultaneously sealed. Also, when bonding the upper chip 101 and
the lower chip 105, the sealing resin 104 is moved so that a
surplus portion thereof is moved toward a periphery region of the
upper chip 101 and the lower chip 105, through the sealing resin
flow path 108 provided for the sealing resin 104 to flow through,
between the support upper bumps 103 and between the support lower
bumps 107. The surplus portion of the sealing resin 104 then flows
toward the outside of the upper chip 101 and the lower chip
105.
[0059] Through the above process, the multi-layered chip 100, which
is a chip-on-chip type semiconductor device, can be
manufactured.
[0060] Next, as shown in FIG. 6G, an external electrode 111
provided on a periphery of the lower chip 105 and a substrate
electrode 113 provided on the substrate 112 are connected by wire
bonding or the like, for packaging.
[0061] Hereinafter, there will be described effects of the upper
chip 101, the lower chip 105 and the multi-layered chip 100.
[0062] In the conventional techniques represented by JP-A No.
2002-26238, there is a problem that the structure and dimensions of
a reaction force receiver bump are restricted, in the case of
supplying a sealing resin between bumps and between chips, after
bonding them. That is, the sealing resin is introduced into a space
among the bumps and among the chips from one of the sides of the
upper chip by a capillary effect, when subsequently introducing the
sealing resin 4. However, if, in this process, the structure and
size of the bumps are not uniform, the flow speed of the sealing
resin is uneven depending on positions in the region to be sealed,
and resultantly a void may be left inside the sealing resin. On the
contrary, in the case of the upper chip 101 and the lower chip 105
according to the present embodiment, since the flow path for the
sealing resin 104 is provided in a region along a circumference of
the section where the upper bumps 102 are provided, such as a
region between the section where the upper bump 102 is provided and
a periphery region of the upper chip 101, the flow rate of the
sealing resin can be substantially at a uniform speed. Therefore,
it is possible to suppress generation of a void in the sealing
resin 104.
[0063] Also, even in the case where it is preferable to provide the
bump in a vicinity of a central region on the chip, it is possible
to provide the support bump on the chip for the reason that a
memory cell is provided in a region vicinity of a periphery region
of the chip, as typically seen in a DRAM or a logic chip including
DRAM, by providing the support upper bump 103 and the support lower
bump 107 between the bumps and a periphery region of the chips.
Therefore, it is possible to enlarge a designing margin with
respect to the structure and size of the support bump. Also, it is
possible to design the structure and size of the support upper bump
103 and the support lower bump 107 comparatively freely.
Consequently, the structure and size of the support bump can be
designed so as to be strong enough to stand an external deforming
force that may be imposed on the multi-layered chip 100, after
bonding the upper chip 101 and the lower chip 105.
[0064] In the present embodiment, the photosensitive sealing resin
104 is supplied in advance in a region between the upper bumps 102
on the upper chip 101, between the support upper bumps 103 on the
upper chip 101, and between the upper bump 102 and the support
upper bump 103 on the upper chip 101, so as to cover the upper bump
and the support upper bump, and then patterned by exposure and
development. Accordingly, when bonding the upper chip 101 and the
lower chip 105, since the space between the support upper bumps on
the multi-layered chip 100 and between the support lower bumps on
the multi-layered chip 100 is filled with the sealing resin 104
which is moved toward in bonding them, generation of a void can be
further suppressed.
[0065] Further, the sealing resin 104 is supplied on the upper chip
101; the support upper bump 103 is provided in a region along a
circumference of the area where the upper bumps 102 are provided,
such as a region between the area where the upper bump 102 is
provided and a periphery region of the upper chip 101; and the
support lower bump 107 is provided in a region along a circumstance
of the area where the lower bumps 106 are provided, such as a
region between the area where the lower bump 106 is provided and a
periphery region of the lower chip 105. Accordingly, when bonding
the upper chip 101 and the lower chip 105, the sealing resin 104
flows along the sealing resin flow path 108 provided between the
support bumps. Therefore, it is possible to control a route on
which the sealing resin 104 is to flow and an amount thereof to be
moved toward outside of the chip. As a result, as shown in FIG. 7,
the sealing resin 104 can be prevented from flowing toward a region
where a pad such as the external electrode 111 is provided, on the
lower chip 105 bonded with the upper chip 101, therefore, it is
further possible to widen designing margin of a position where the
external electrode 111 or other pads is provided on a chip such as
the lower chip 105.
[0066] Although the present invention has been described based on
the embodiment shown in the drawings, it is to be understood that
they are only exemplary and that various other structure may be
employed.
[0067] For example, in the above embodiment, the embodiment which
four each of support bumps whose area is larger than an area of the
bumps are provided in a region between the upper bumps 102 and a
periphery region of the upper chip 101, and between the lower bumps
106 and a periphery region of the lower chip 105 is exemplified. As
shown in FIGS. 11 and 12, it is suitable that the support upper
bump 103 and the support lower bump 107 may be a group of fine
bumps 115. Since the support upper-bump 103 and the support lower
bump 107 has a structure that is constituted of a group of fine
bumps 115, the interface area between the support upper bump 103
and the support lower bump 107 can be reduced, therefore, a load
imposed on the upper chip 101 and the lower chip 105 when bonding
these chips can be reduced.
[0068] Also, as shown in FIG. 8, two support upper bumps 103 may be
provided in a region between a rectangular-shaped section where the
upper bumps 102 are provided and a periphery region of the upper
chip 101, on the respective sides of the rectangular section where
the upper bumps 102 is provided. As well as the upper chip 101,
also in the lower chip 105, two such support bumps may be provided.
Further, the upper chip 101 and the lower chip 105 may have three
or more support bumps.
[0069] While the upper bump 102 and the support upper bump 103 are
constituted of a same material in the above embodiment, the upper
bump 102 and the support upper bump 103 may be constituted of a
different material, such as gold for the upper bump 102 and copper
for the support upper bump 107. Also, while the lower bump 106 and
the support lower bump 103 are constituted of a same material in
the above embodiment, the lower bump 106 and the support lower bump
107 may be constituted of a different material, such as gold for
the lower bump 106 and copper for the support lower bump 107.
[0070] Further, while in the above embodiment, the support upper
bump 103 and the support lower bump 107 made of a metal film such
as copper is employed, a fusible metal bump may be employed to
constitute the support upper bump 103 and the support lower bump
107. A fusible metal bump is constituted of a metal material such
as a thermofusible solder such as Sn--Ag or Sn (for instance, a
lead-free solder), and by employing the fusible metal bump, the
adhesive characteristics between the support upper bump 103 and the
support lower bump 107 can be increased. Having such configuration,
it is further possible to reduce a load imposed on the upper chip
101 and the lower chip 105 when bonding these chips. Consequently,
a support bump having a larger area can be bonded with a lower
load.
[0071] Further, while the support upper bump 103 and the support
lower bump 107 are in contact with the pad electrode 109, thereby
serving to achieve electrical connection between the upper chip 101
and another chip, as well as between the lower chip 105 and another
chip in the above embodiment, it is not always necessary that the
support upper bump 103 and the pad electrode 109, and the support
lower bump 107 and the pad electrode 109 are contact with each
other respectively. In this case, the support upper bump 103 does
not contribute for the electrical connection between the upper chip
101 and another chip, and the support lower bump 107 does not
contribute for the electrical connection between the lower chip 105
and another chip. Also, the support upper bump 103 may be in
contact with the pad electrode 109 and the support lower bump 107
may not be in contact with the pad electrode 109, or the support
upper bump 103 may not be in contact with the pad electrode 109 and
the support lower bump 107 may be in contact with the pad electrode
109.
[0072] In addition, when the support upper bump 103 and the support
lower bump 107 are not provided on the pad electrode 109, the
support upper bump 103 and the support lower bump 107 may be
provided on an insulating layer made of a polyimide or the like,
applied on the chip wafer 110.
[0073] Further, while a photosensitive resin is employed as the
sealing resin 104 in the above embodiment, a sealing resin, which
does not have photosensitive characteristics, may be employed.
[0074] Still further, while the upper bump 102 and the lower bump
106 are formed in a rectangular-shaped region in the above
embodiment, the upper bump 102 and the lower bump 106 may be
disposed in a differently shaped region, such as a circular region,
other than the rectangular-shaped region.
[0075] Still further, while a surplus region is provided in a
circumference of the support upper bump 103 and the support lower
bump 107 in the above embodiment, the outer periphery of the
support upper bump 103 and the support lower bump 107 may be
contact with an outermost periphery portion of the upper chip 101
and the lower chip 105.
[0076] Still further, while the multi-layered chip 100 includes the
upper chip 101 and the lower chip 105 bonded as shown in FIG. 3 in
the above embodiment, even if three or more chips may be formed, at
least a pair of chips among three or more chips may be in contact
with each other to oppose them, thus to be bonded them. For
example, three chips may be formed on a substrate, among which a
pair of chips constitutes a chip-on-chip type multi-layered chip
bonded by being in contact with bumps each other, and the remaining
chip may be connected to a substrate such as a printed circuit
board by wire bonding. In such a case also, the effects of the
multi-layered chip 100 can be equally obtained.
[0077] It is apparent that the present invention is not limited to
the above embodiment, that may be modified and changed without
departing from the scope and spirit of the invention.
* * * * *