U.S. patent application number 11/012965 was filed with the patent office on 2005-12-15 for plating chemistry and method of single-step electroplating of copper on a barrier metal.
Invention is credited to He, Renren, Kovarsky, Nicolay, Sun, Zhi-Wen, Wang, You.
Application Number | 20050274622 11/012965 |
Document ID | / |
Family ID | 35459360 |
Filed Date | 2005-12-15 |
United States Patent
Application |
20050274622 |
Kind Code |
A1 |
Sun, Zhi-Wen ; et
al. |
December 15, 2005 |
Plating chemistry and method of single-step electroplating of
copper on a barrier metal
Abstract
Embodiments of a method of copper plating a substrate surface
with a group VIII metal layer have been described. In one
embodiment, a method of plating copper on a substrate surface with
a group VIII metal layer comprises pre-treating the substrate
surface by removing a group VIII metal surface oxide layer and/or
surface contaminants and plating the substrate in a copper plating
solution comprising about 50 g/l to about 300 g/l of sulfuric acid
at an initial plating current higher than the critical current
density to deposit a continuous copper layer on the substrate
surface. The Pre-treating the substrate can be accomplished by
annealing the substrate in an environment with a
hydrogen-containing gas environment and/or a non-reactive gas(es)
to Ru, by a cathodic treatment in an acid-containing bath, or by
immersing the substrate in an acid-containing bath.
Inventors: |
Sun, Zhi-Wen; (San Jose,
CA) ; He, Renren; (Sunnyvale, CA) ; Kovarsky,
Nicolay; (Sunnyvale, CA) ; Wang, You;
(Cupertino, CA) |
Correspondence
Address: |
PATTERSON & SHERIDAN, LLP
3040 POST OAK BOULEVARD, SUITE 1500
HOUSTON
TX
77056
US
|
Family ID: |
35459360 |
Appl. No.: |
11/012965 |
Filed: |
December 15, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60579129 |
Jun 10, 2004 |
|
|
|
60621215 |
Oct 21, 2004 |
|
|
|
Current U.S.
Class: |
205/209 ;
205/210; 205/291; 257/E21.175 |
Current CPC
Class: |
C25D 7/123 20130101;
H01L 21/2885 20130101; C25D 5/18 20130101; C25D 5/34 20130101; H01L
21/76864 20130101; H01L 21/76873 20130101; C25D 3/38 20130101; H01L
21/76843 20130101 |
Class at
Publication: |
205/209 ;
205/291; 205/210 |
International
Class: |
C25D 003/00; C25D
005/34 |
Claims
What is claimed is:
1. A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into an acidic
copper plating solution; and applying a first electrical bias to
the substrate surface after the substrate surface is immersed in
the copper plating solution to assist copper nucleation on the
substrate surface, the first electrical bias being configured to
generate a first current density across the substrate surface
greater than a critical current density.
2. The method of claim 1, further comprising: applying a second
electrical bias to the substrate surface to deposit a gap-fill
layer, wherein the second electrical bias is configured to generate
a second current density across the substrate surface that is lower
than the first current density.
3. The method of claim 1, wherein the acidity in the acidic copper
plating solution comes from sulfuric acid, whose concentration is
in the range between about 50 g/l to about 300 g/l.
4. The method of claim 2, further comprising: applying a final
electrical bias to the substrate surface to deposit a bulk-fill
layer, wherein the final electrical bias is configured to generate
a final current density across the substrate surface that is higher
than the second current density.
5. The method of claim 1, wherein the copper plating solution
further comprises a copper concentration of between about 20 g/l to
about 60 g/l, and a chlorine concentration of between about 20 ppm
to about 100 ppm.
6. The method of claim 4, wherein the copper plating solution
further comprising adding a suppressor at a concentration of
between about 100 ppm to about 1000 ppm, an accelerator at a
concentration of between 2 ppm to about 30 ppm, and a leveler at a
concentration of between about 1 ml/l and about 12 ml/l.
7. The method of claim 1, wherein the copper plating solution is
maintained at a temperature between 10.degree. C. to about
30.degree. C.
8. The method of claim 1, wherein the substrate is rotated at
between about 10 rpm and about 200 rpm while the substrate surface
contacts the copper plating solution.
9. The method of claim 3, wherein the first current density is
between about 5 mA/cm.sup.2 to about 60 mA/cm.sup.2.
10. The method of claim 8, wherein the first current is applied for
a duration between about 0.1 second to about 5 seconds.
11. The method of claim 2, wherein the second current is between
about 2 mA/cm.sup.2 to about 10 mA/cm.sup.2 and the second current
is applied for a duration between about 3 seconds to about 20
seconds.
12. The method of claim 4, wherein the final current is between
about 40 mA/cm.sup.2 to about 60 mA/cm.sup.2 and the final current
is applied for a duration between about 10 seconds to about 60
seconds.
13. The method of claim 4, further comprises: applying a third
electrical bias, before applying the final electrical bias, to the
substrate surface to deposit a transitional layer, wherein the
third electrical bias is configured to generate a third current
density across the substrate surface that is higher than the second
current density and lower than the final current density.
14. The method of claim 13, wherein the third current is between
about 10 mA/cm.sup.2 to about 30 mA/cm.sup.2 and the third current
is applied for a duration between about 0 second to about 10
seconds.
15. The method of claim 1, wherein the group VIII metal is selected
from the group of ruthenium (Ru), rhodium (Rh), palladium (Pd),
osmium (Os), iridium (Ir), and platinum (Pt).
16. The method of claim 1, wherein the group VIII metal is
ruthenium (Ru).
17. The method of claim 1, wherein the copper plating is performed
within 4 hours after the pre-treatment.
18. The method of claim 1, wherein pre-treating the substrate
surface is accomplished by annealing the substrate in an
environment with a hydrogen-containing gas and/or a gas(es)
non-reactive to the group VIII metal.
19. The method of claim 18, wherein the annealing gas is a forming
gas that contains about 4% hydrogen and about 96% nitrogen.
20. The method of claim 18, wherein the annealing gas flow rate is
between about 1 sccm to about 20 .mu.m.
21. The method of claim 18, wherein the annealing temperature is
between about 100.degree. C. to about 400.degree. C.
22. The method of claim 18, wherein annealing duration is between
about 2 seconds to about 5 hours.
23 A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into an acidic
copper plating solution; applying a first electrical bias to the
substrate surface after the substrate surface is immersed in the
copper plating solution to assist copper nucleation on the
substrate surface, the first electrical bias being configured to
generate a first current density across the substrate surface
greater than a critical current density; and applying a second
electrical bias to the substrate surface to deposit a gap-fill
layer, wherein the second electrical bias is configured to generate
a second current density across the substrate surface that is lower
than the first current density.
24. A method of plating copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into a copper
plating solution, wherein the copper plating solution comprises
about 50 g/l to about 300 g/l of sulfuric acid; and applying a
first electrical bias to the substrate surface after the substrate
surface is immersed in the copper plating solution to assist copper
deposit nucleation on the substrate surface, the first electrical
bias being configured to generate a first current density across
the substrate surface greater than a critical current density.
25. The method of claim 24, further comprising: applying a second
electrical bias to the substrate surface to deposit a gap-fill
layer, wherein the second electrical bias is configured to generate
a second current density across the substrate surface that is lower
than the first current density.
26. The method of claim 25, further comprises: applying a final
electrical bias to the substrate surface to deposit a bulk-fill
layer, wherein the final electrical bias is configured to generate
a final current density across the substrate surface that is higher
than the second current density.
27. The method of claim 24, wherein the copper plating solution
further comprises a copper concentration of between about 20 g/l to
about 60 g/l, and a chlorine concentration of between about 20 ppm
to about 100 ppm.
28. The method of claim 27, wherein the copper plating solution
further comprising adding a suppressor at a concentration of
between about 100 ppm to about 1000 ppm, an accelerator at a
concentration of between 2 ppm to about 30 ppm, and a leveler at a
concentration of between about 1 ml/l and about 12 ml/l.
29. The method of claim 24, wherein the copper plating solution is
maintained at a temperature between 10.degree. C. to about
30.degree. C.
30. The method of claim 24, wherein the substrate is rotated at
between about 10 rpm and about 200 rpm while the substrate surface
contacts the copper plating solution.
31. The method of claim 24, wherein the first current density is
between about 5 mA/cm.sup.2 to about 60 mA/cm.sup.2.
32. The method of claim 24, wherein the first current is applied
for a duration between about 0.1 second to about 5 seconds.
33. The method of claim 24, wherein the second current is between
about 2 mA/cm.sup.2 to about 10 mA/cm.sup.2 and the second current
is applied for a duration between about 3 seconds to about 20
seconds.
34. The method of claim 25, wherein the final current is between
about 40 mA/cm.sup.2 to about 60 mA/cm.sup.2 and the final current
is applied for a duration between about 10 seconds to about 60
seconds.
35. The method of claim 25, further comprises: applying a third
electrical bias, before applying the final electrical bias, to the
substrate surface to deposit a transitional layer, wherein the
third electrical bias is configured to generate a third current
density across the substrate surface that is higher than the second
current density and lower than the final current density.
36. The method of claim 35, wherein the third current is between
about 10 mA/cm.sup.2 to about 30 mA/cm.sup.2 and the third current
is applied for a duration between about 0 second to about 10
seconds.
37. The method of claim 24, wherein the group VIII metal is
selected from the group of ruthenium (Ru), rhodium (Rh), palladium
(Pd), osmium (Os), iridium (Ir), and platinum (Pt).
38. The method of claim 24, wherein the group VIII metal is
ruthenium (Ru).
39. The method of claim 24, wherein the copper plating is performed
within 4 hours after the pre-treatment.
40. The method of claim 24, wherein pre-treating the substrate
surface is accomplished by annealing the substrate in an
environment with a hydrogen-containing gas and/or a gas(es)
non-reactive to the group VIII metal.
41. A method of plating copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into a copper
plating solution, wherein the copper plating solution comprises
about 50 g/l to about 300 g/l of sulfuric acid; applying a first
electrical bias to the substrate surface after the substrate
surface is immersed in the copper plating solution to assist copper
deposit nucleation on the substrate surface, the first electrical
bias being configured to generate a first current density across
the substrate surface greater than a critical current density; and
applying a second electrical bias to the substrate surface to
deposit a gap-fill layer, wherein the second electrical bias is
configured to generate a second current density across the
substrate surface that is lower than the first current density.
42. A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into an acidic
copper plating solution; and applying a first electrical bias
voltage to the substrate surface after the substrate surface is
immersed in the copper plating solution to assist copper nucleation
on the substrate surface, the first electrical bias voltage being
configured to generate a current density across the substrate
surface greater than a critical current density.
43. A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into an acidic
copper plating solution; applying a first electrical bias voltage
to the substrate surface after the substrate surface is immersed in
the copper plating solution to assist copper nucleation on the
substrate surface, the first electrical bias voltage being
configured to generate a current density across the substrate
surface greater than a critical current density; and applying a
second electrical bias voltage to the substrate surface to deposit
a gap-fill layer, wherein the second electrical bias voltage is
lower than the first electrical bias voltage.
44. A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into a copper
plating solution, wherein the copper plating solution comprises
about 50 g/l to about 300 g/l of sulfuric acid; and applying a
first electrical bias voltage to the substrate surface after the
substrate surface is immersed in the copper plating solution to
assist copper nucleation on the substrate surface, the first
electrical bias voltage being configured to generate a current
density across the substrate surface greater than a critical
current density.
45. A method of plating a copper layer onto a substrate surface,
wherein the substrate surface comprises a group VIII metal layer,
comprising: pre-treating the substrate surface to remove a surface
oxide layer and/or surface contaminants from the group VIII metal
layer surface; immersing the substrate surface into a copper
plating solution, wherein the copper plating solution comprises
about 50 g/l to about 300 g/l of sulfuric acid; applying a first
electrical bias voltage to the substrate surface after the
substrate surface is immersed in the copper plating solution to
assist copper nucleation on the substrate surface, the first
electrical bias voltage being configured to generate a current
density across the substrate surface greater than a critical
current density; and applying a second electrical bias voltage to
the substrate surface to deposit a gap-fill layer, wherein the
second electrical bias voltage is lower than the first electrical
bias voltage.
46. The method of claim 1, wherein the first electrical bias is a
bias current.
47. The method of claim 46, wherein the first electrical bias
current is pulsed.
48. The method of claim 46, wherein the first electrical bias
current is a ramp-down current.
49. The method of claim 42, wherein the first electrical bias
voltage is pulsed.
50. The method of claim 42, wherein the electrical bias voltage is
a ramp-down voltage.
Description
CROSS-REFERENCE TO OTHER APPLICATIONS
[0001] This application claims the benefit of U.S. provisional
patent application Ser. No. 60/579,129, entitled "Method Of Barrier
Layer Surface Treatment To Enable Direct Copper Plating", filed on
Jun. 10, 2004, and U.S. provisional patent application Ser. No.
60/621,215, entitled "Plating Chemistry And Method Of Single-Step
Electroplating Of Copper On A Barrier Metal", filed on Oct. 21,
2004, which is incorporated herein by reference.
BACKGROUND OF THE DISCLOSURE
[0002] 1. Field of the Invention
[0003] Embodiments of the invention generally relate to a plating
chemistry and a method of electroplating of copper directly on a
barrier metal.
[0004] 2. Description of the Background Art
[0005] Sub-quarter micron, multi-level metallization is one of the
key technologies for the next generation of very large scale
integration (VLSI) and ultra large scale integration (ULSI)
semiconductor devices. The multilevel interconnects that lie at the
heart of this technology require the filling of contacts, vias,
lines, and other features formed in high aspect ratio apertures.
Reliable formation of these features is very important to the
success of both VLSI and ULSI as well as to the continued effort to
increase circuit density and quality on individual substrates and
die.
[0006] As circuit densities increase, the widths of contacts, vias,
lines and other features, as well as the dielectric materials
between them, may be decreased to less than about 65 nm, whereas
the thickness of the dielectric layers remains substantially
constant with the result that the aspect ratios for the features,
i.e., their height divided by width, increase. Many conventional
deposition processes do not consistently fill structures in which
the aspect ratio exceeds 6:1, and particularly when the aspect
ratio exceeds 10:1. As such, there is a great amount of ongoing
effort being directed at the formation of void-free,
nanometer-sized structures having high aspect ratios wherein the
ratio of feature height to feature width is 6:1 or higher.
[0007] Additionally, as the feature widths decrease, the device
current typically remains constant or increases, which results in
an increased current density for such features. Elemental aluminum
and aluminum alloys have been the traditional metals used to form
vias and lines in semiconductor devices because aluminum has a
perceived low electrical resistivity, superior adhesion to most
dielectric materials, and ease of patterning, and the aluminum in a
highly pure form is readily available. However, aluminum has a
higher electrical resistivity than other more conductive metals,
such as copper (Cu). Aluminum can also suffer from
electromigration, leading to the formation of voids in the
conductor.
[0008] Copper and copper alloys have lower resistivities than
aluminum, as well as a significantly higher electromigration
resistance compared to aluminum. These characteristics are
important for supporting the higher current densities experienced
at high levels of integration and increased device speed. Copper
also has good thermal conductivity. Therefore, copper is becoming a
choice metal for filling sub-quarter micron, high aspect ratio
interconnect features on semiconductor substrates.
[0009] Conventionally, deposition techniques such as chemical vapor
deposition (CVD) and physical vapor deposition (PVD) have been used
to fill these interconnect features. However, as the interconnect
sizes decrease and aspect ratios increase, void-free interconnect
feature fill by conventional metallization techniques becomes
increasingly difficult using CVD and/or PVD. As a result thereof,
plating techniques, such as electrochemical plating (ECP), have
emerged as viable processes for filling sub-quarter micron sized
high aspect ratio interconnect features in integrated circuit
manufacturing processes.
[0010] Most ECP processes are generally two-stage processes,
wherein a seed layer is first formed over the surface of features
on the substrate (this process may be performed in a separate
system), and then the surface of the features is exposed to an
electrolyte solution while an electrical bias is simultaneously
applied between the substrate surface and an anode positioned
within the electrolyte solution.
[0011] Conventional plating practices include depositing a copper
seed layer by physical vapor deposition (PVD), chemical vapor
deposition (CVD), or atomic layer deposition (ALD) onto a diffusion
barrier layer (e.g., tantalum or tantalum nitride). However, as the
feature sizes become smaller, it becomes difficult to have adequate
seed step coverage with PVD techniques, as discontinuous islands of
copper agglomerates are often obtained in the feature side walls
close to the feature bottom. When using a CVD or ALD deposition
process in place of PVD to deposit a continuous sidewall layer
throughout the depth of the high aspect ratio features, a thick
copper layer is formed over the field. The thick copper layer on
the field can cause the throat of the feature to close before the
feature sidewalls are completely covered. When the deposition
thickness on the field is reduced to prevent throat closure, ALD
and CVD techniques are also prone to generate discontinuities in
the seed layer. These discontinuities in the seed layer have been
shown to cause plating defects in the layers plated over the seed
layer. In addition, copper tends to oxidize readily in the
atmosphere and copper oxide readily dissolves in the plating
solution. To prevent complete dissolution of copper in the
features, the copper seed layer is usually made relatively thick
(as high as 800 .ANG.), which can inhibit the plating process from
filling the features. Therefore, it is desirable to have a copper
plating process that allows direct electroplating of copper on thin
barrier layer(s) without a copper seed layer.
[0012] Therefore, there is a need for a copper plating process that
can fill features and does not require a copper seed layer.
SUMMARY OF THE INVENTION
[0013] The invention comprises embodiments of a method of plating
copper layer onto a substrate surface coated with a group VIII
metal layer. In one embodiment, a method of plating a copper layer
onto a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove a surface oxide layer and/or surface contaminants from
the group VIII metal layer surface, immersing the substrate surface
into an acidic copper plating solution, and applying a first
electrical bias to the substrate surface after the substrate
surface is immersed in the copper plating solution to assist copper
nucleation on the substrate surface, the first electrical bias
being configured to generate a first current density across the
substrate surface greater than a critical current density.
[0014] In another embodiment, a method of plating a copper layer
onto a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove a surface oxide layer and/or surface contaminants from
the group VIII metal layer surface, immersing the substrate surface
into an acidic copper plating solution, applying a first electrical
bias to the substrate surface after the substrate surface is
immersed in the copper plating solution to assist copper nucleation
on the substrate surface, the first electrical bias being
configured to generate a first current density across the substrate
surface greater than a critical current density, and applying a
second electrical bias to the substrate surface to deposit a
gap-fill layer, wherein the second electrical bias is configured to
generate a second current density across the substrate surface that
is lower than the first current density.
[0015] In another embodiment, a method of plating copper layer onto
a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove surface oxide layer and/or surface contaminants from the
group VIII metal layer surface, immersing the substrate surface
into a copper plating solution, wherein the copper plating solution
comprises about 50 g/l to about 300 g/l of sulfuric acid, and
applying a first electrical bias to the substrate surface after the
substrate surface is immersed in the copper plating solution to
assist copper deposit nucleation on the substrate surface, the
first electrical bias being configured to generate a first current
density across the substrate surface greater than a critical
current density.
[0016] In another embodiment, a method of plating copper layer onto
a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove surface oxide layer and/or surface contaminants from the
group VIII metal layer surface, immersing the substrate surface
into a copper plating solution, wherein the copper plating solution
comprises about 50 g/l to about 300 g/l of sulfuric acid, applying
a first electrical bias to the substrate surface after the
substrate surface is immersed in the copper plating solution to
assist copper deposit nucleation on the substrate surface, the
first electrical bias being configured to generate a first current
density across the substrate surface greater than a critical
current density, and applying a second electrical bias to the
substrate surface to deposit a gap-fill layer, wherein the second
electrical bias is configured to generate a second current density
across the substrate surface that is lower than the first current
density.
[0017] In another embodiment, a method of plating a copper layer
onto a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove a surface oxide layer and/or surface contaminants from
the group VIII metal layer surface, immersing the substrate surface
into an acidic copper plating solution, and applying a first
electrical bias voltage to the substrate surface after the
substrate surface is immersed in the copper plating solution to
assist copper nucleation on the substrate surface, the first
electrical bias voltage being configured to generate a current
density across the substrate surface greater than a critical
current density.
[0018] In another embodiment, a method of plating a copper layer
onto a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove a surface oxide layer and/or surface contaminants from
the group VIII metal layer surface, immersing the substrate surface
into an acidic copper plating solution, applying a first electrical
bias voltage to the substrate surface after the substrate surface
is immersed in the copper plating solution to assist copper
nucleation on the substrate surface, the first electrical bias
voltage being configured to generate a current density across the
substrate surface greater than a critical current density, and
applying a second electrical bias voltage to the substrate surface
to deposit a gap-fill layer, wherein the second electrical bias
voltage is lower than the first electrical bias voltage.
[0019] In another embodiment, a method of plating a copper layer
onto a substrate surface, wherein the substrate surface comprises a
group VIII metal layer comprises pre-treating the substrate surface
to remove a surface oxide layer and/or surface contaminants from
the group VIII metal layer surface, immersing the substrate surface
into a copper plating solution, wherein the copper plating solution
comprises about 50 g/l to about 300 g/l of sulfuric acid, and
applying a first electrical bias voltage to the substrate surface
after the substrate surface is immersed in the copper plating
solution to assist copper nucleation on the substrate surface, the
first electrical bias voltage being configured to generate a
current density across the substrate surface greater than a
critical current density.
[0020] In yet another embodiment, a method of plating a copper
layer onto a substrate surface, wherein the substrate surface
comprises a group VIII metal layer comprises pre-treating the
substrate surface to remove a surface oxide layer and/or surface
contaminants from the group VIII metal layer surface, immersing the
substrate surface into a copper plating solution, wherein the
copper plating solution comprises about 50 g/l to about 300 g/l of
sulfuric acid, applying a first electrical bias voltage to the
substrate surface after the substrate surface is immersed in the
copper plating solution to assist copper nucleation on the
substrate surface, the first electrical bias voltage being
configured to generate a current density across the substrate
surface greater than a critical current density, and applying a
second electrical bias voltage to the substrate surface to deposit
a gap-fill layer, wherein the second electrical bias voltage is
lower than the first electrical bias voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The teachings of the present invention can be readily
understood by considering the following detailed description in
conjunction with the accompanying drawings, in which:
[0022] FIGS. 1A-1C illustrate schematic cross-sectional views of an
integrated circuit fabrication sequence.
[0023] FIG. 2 shows the critical current density as a function of
sulfuric acid concentration.
[0024] FIG. 3 shows the process flow of pre-treating a substrate
surface before copper plating.
[0025] FIG. 4A shows the critical current density as a function of
sulfuric acid concentration for as-deposited and annealed Ru
substrates.
[0026] FIG. 4B shows the copper film resistivity as a function of
plating bath acidity.
[0027] FIG. 5 is a top plan view of one embodiment of an
electrochemical plating system.
[0028] FIG. 6 illustrates an exemplary embodiment of a plating cell
used in the electrochemical plating cell of the invention.
[0029] FIG. 7A is a drawing of controlled cathodic current versus
plating time.
[0030] FIG. 7B is a drawing of cathodic voltage versus plating time
corresponding to FIG. 7A.
[0031] FIG. 8A is a drawing of controlled cathodic voltage versus
plating time.
[0032] FIG. 8B is a drawing of cathodic current versus plating time
corresponding to FIG. 8A.
[0033] FIG. 9A is a drawing of pulsed controlled cathodic current
or voltage between the nucleation period (t.sub.1 to t.sub.2 or
t.sub.11 to t.sub.12).
[0034] FIG. 9B is a drawing of ramp-down controlled cathodic
current or voltage between the nucleation period (t.sub.1 to
t.sub.2 or t.sub.11 to t.sub.12).
[0035] FIG. 10 shows the SEM of copper plated on annealed Ru
surface in 0.14 .mu.m.times.0.8 .mu.m trenches.
[0036] To facilitate understanding, identical reference numerals
have been used, where possible, to designate identical elements
that are common to the figures. The drawings are not to scale.
DETAILED DESCRIPTION
[0037] Ruthenium (Ru) thin films, deposited by CVD, ALD or PVD, can
be a potential candidate for a seedless diffusion barrier between
intermetal dielectric (IMD) and copper interconnect for .ltoreq.45
nm technology. Ruthenium is a group VIII metal that has low
electrical resistivity (resistivity .about.7 .mu..OMEGA.-cm) and
high thermal stability (high melting point .about.2300.degree. C.).
It is relatively stable even in the presence of oxygen and water at
ambient temperature. The thermal and electrical conductivities of
Ru are twice those of Tantalum (Ta). Ruthenium also does not form
an alloy with copper below 900.degree. C. and shows good adhesion
to copper. Therefore, the semiconductor industry has shown an
interest in using Ru as a copper barrier layer. The low resistivity
of Ru can be an advantage when trying to fill ruthenium coated
features with copper without a seed layer.
[0038] FIGS. 1A-1C illustrate cross-sectional views of a substrate
at different stages of a copper interconnect fabrication sequence
incorporating a group VIII metal barrier layer of the present
invention. FIG. 1A, for example, illustrates a cross-sectional view
of a substrate 100 having metal contacts 104 and a dielectric layer
102 formed thereon. The substrate 100 may comprise a semiconductor
material such as, for example, silicon, germanium, or gallium
arsenide. The dielectric layer 102 may comprise an insulating
material such as, silicon dioxide, silicon nitride, silicon
oxynitride and/or carbon-doped silicon oxides, such as
SiO.sub.xC.sub.y, for example, BLACK DIAMOND.TM. low-k dielectric,
available from Applied Materials, Inc., located in Santa Clara,
Calif. The metal contacts 104 may comprise for example, copper,
among others. Apertures 120 may be defined in the dielectric layer
102 to provide openings over the metal contacts 104. The apertures
120 may be defined in the dielectric layer 102 using conventional
lithography and etching techniques. The width of apertures 120
could be equal to or less than about 900 .ANG.. The thickness of
dielectric layer 102 could be in the range between about 1000 .ANG.
to about 10000 .ANG..
[0039] In one embodiment, a barrier layer 106 may be formed in the
apertures 120 defined in the dielectric layer 102. The optional
barrier layer 106 may include one or more refractory
metal-containing layers used as a copper-barrier material such as,
for example, titanium, titanium nitride, titanium silicon nitride,
tantalum, tantalum nitride, tantalum silicon nitride, tungsten and
tungsten nitride, among others. The optional barrier layer 106 may
be formed using a suitable deposition process, such as ALD,
chemical vapor deposition (CVD) or physical vapor deposition (PVD).
For example, titanium nitride may be deposited using a CVD process
or an ALD process wherein titanium tetrachloride and ammonia are
reacted. In one embodiment, tantalum and/or tantalum nitride is
deposited as a barrier layer by an ALD process as described in
commonly assigned U.S. Patent Publication 20030121608, published
Jul. 3, 2003, and is herein incorporated by reference. The
thickness of the optional barrier layer is between about 5 .ANG. to
about 150 .ANG. and preferably less than 100 .ANG..
[0040] In one embodiment, a thin film of group VIII metal, such as
ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium
(Ir), and platinum (Pt), may be used as an underlayer (or barrier
layer) for the copper vias and lines. Such group VIII metal, which
is resistant to corrosion and oxidation, may provide a surface upon
which a copper layer is subsequently deposited using an
electrochemical plating (ECP) process. The group VIII metal acts as
a copper-barrier layer. The group VIII metal can also be deposited
on the conventional barrier layer, such as Ta (tantalum) and/or TaN
(tantalum nitride), to serve as a glue layer between the
conventional barrier layer and copper. The group VIII metal is
typically deposited using a chemical vapor deposition (CVD)
process, atomic layer deposition (ALD) or a physical vapor
deposition (PVD) process.
[0041] Referring to FIG. 1B, a group VIII barrier metal layer 108,
such as ruthenium (Ru), is formed on the substrate, and in this
example on the optional barrier layer 106. The thickness for the
group VIII metal layer 108 often depends on the device structure to
be fabricated. Typically, the thickness of the group VIII metal
layer 108, such as ruthenium (Ru), is less than about 1,000 .ANG.,
preferably between about 5 .ANG. to about 200 .ANG.. In one
embodiment, the group VIII metal layer 108 is a ruthenium layer
having a thickness less than about 100 .ANG., for example, about 50
.ANG..
[0042] Thereafter, referring to FIG. 1C, the apertures 120 may be
filled with copper 110 to complete the copper interconnect. In one
embodiment, the noble or transitional metal layer, such as
ruthenium layer, serves as a seed layer to which a copper is
directly deposited using an ECP or other copper plating techniques.
The electrochemical plating solution for ECP generally includes a
copper source, an acid source, a chlorine ion source, and at least
one plating solution additive, i.e., levelers, suppressors,
accelerators, antifoaming agents, etc. For example, the plating
solution may contain between about 30 g/l and about 60 g/l of Cu,
between about 10 g/l to about 50 g/l of sulfuric acid, between
about 20 and about 100 ppm of Cl ions, between about 5 and about 30
ppm of an additive accelerator, between about 100 and about 1000
ppm of an additive suppressor, and between about 1 and about 6 ml/I
of an additive leveler. The plating current may be in the range
from about 2 mA/cm.sup.2 to about 10 mA/cm.sup.2 for filling copper
into the submicron trench and/or via structures. Examples of copper
plating chemistries and processes can be found in commonly assigned
U.S. patent application Ser. No. 10/616,097, titled "Multiple-Step
Electrodeposition Process For Direct Copper Plating On Barrier
Metals", filed on Jul. 8, 2003, and U.S. patent application No.
60/510,190, titled "Methods And Chemistry For Providing Initial
Conformal Electrochemical Deposition Of Copper In Sub-Micron
Features", filed on Oct. 10, 2003. An example of an electrochemical
plating (ECP) system and an exemplary plating cell are described in
FIGS. 5-6 below.
[0043] It has been found that conventional copper plating processes
for using 10-50 g/l of H.sub.2SO.sub.4, and plating current density
of 2-10 mA/cm.sup.2 will not result in a thin continuous copper
film (.ltoreq.1000 .ANG.) deposition on a Ru layer. A continuous
copper film is formed on Ru when the plating current density and/or
concentration of H.sub.2SO.sub.4 (or acidity) are increased beyond
the values used in conventional copper plating. A minimum or
critical current density (CCD) has been found where plating current
densities equal to or above this value will form a thin continuous
copper film on a Ru layer and current densities below this value
will not form a thin continuous film on the Ru layer. The magnitude
of the CCD is strongly dependent on the acidity of the plating
solution.
[0044] FIG. 2 illustrates an example of the critical current
density (CCD) versus sulfuric acid (H.sub.2SO.sub.4) concentration.
The CCD, as shown in FIG. 2, is defined as the minimum current
density required to form a 1000 .ANG. continuous copper film on a
Ru surface. Below the CCD, no visually shiny continuous copper film
will be deposited at the center regions of the substrate. While the
magnitude of CCD strongly depends on the acidity level of the
plating bath, the CCD is independent of the Ru deposition method
(either ALD, CVD or PVD).
[0045] It is well known that the kinetics of nucleation and crystal
growth for electro-deposition is intimately related to the local
electrochemical over-potential at the nucleation/growth sites.
Over-potential is defined as the difference between the actual
potential and the zero-current (open-circuit) potential. A high
over-potential favors new crystal nucleation by lowering the
critical nucleus size and increasing the density of nuclei, while a
low electrochemical over-potential favors growth on existing
crystallites. Further, the existence of sulfur-containing organic
additives (e.g., accelerator) in the plating solution is believed
to enhance the surface diffusion of Cu adatoms and thus promote
crystal growth at the expense of nucleation. Cu adatoms are copper
atoms that land on the substrate surface during plating and before
they are incorporated into the Cu film. Since the plating current
density depends on the electrochemical over-potential for a given
bath, the copper deposit structure/morphology is therefore affected
by the plating current density. Scanning electron microscopic (SEM)
pictures, taken near the center of a substrate having an 1000 .ANG.
(measured near the edge of the substrate) copper film plated on an
100 .ANG. Ru film in a 10 g/l sulfuric acid containing plating
solution at a 3 mA/cm.sup.2 plating current, was found to have
large crystallites and poor film deposition in the center region of
the substrate. The 100 .ANG. thick Ru film was deposited by PVD.
According to the results shown in FIG. 2, the CCD is about 40
mA/cm.sup.2 when the sulfuric acid concentration is 10 g/l. The
current density of 3 mA/cm.sup.2 is much lower than 40 mA/cm.sup.2
(CCD) and thus as expected a non-continuous layer was formed. It is
believed that under this plating condition, only a few crystallites
are stable enough to serve as the nucleation center for further
crystal growth, and thus the energy from the plating current is
primarily used in growing these crystals, with the help of fast
copper adatom surface diffusion. Therefore, the SEM shows large
crystallites and Cu island deposition in the center region of the
substrate. To form a continuous copper film across the entire
substrate under this condition, the deposited layer would have to
be very thick and the deposited layer would likely contain voids,
which would make it unsuitable for Cu interconnect applications. It
has been found that a substrate that has a 5000 .ANG. thick
continuous copper film can be formed on a Ru (100 .ANG. thick and
deposited by PVD) film, using a plating solution that contained 60
g/l of H.sub.2SO.sub.4 and a plating current density of about 10
mA/cm.sup.2 (slightly lower than the CCD of 15 mA/cm.sup.2).
However, there were large voids at the copper/Ru interface.
[0046] When the plating current was increased to 30 mA/cm.sup.2,
the density of the crystallites was found to increase and the sizes
of the crystallites was found to decrease near the center of the
substrate. However, no continuous copper film was formed on Ru
surface since the plating current was below the CCD. As before, the
Ru film was 100 .ANG. thick and was deposited by PVD.
[0047] There are also disadvantages in increasing plating current.
Generally, a high plating current density tends to result in poor
gapfill. Generally, plating current densities of less than about 10
mA/cm.sup.2 have been found to encourage bottom-up gapfill. In
order to reduce the plating current density to the range suitable
for bottom-up gapfill, the concentration of sulfuric acid needs to
be increased. When the sulfuric acid concentration is raised to 160
g/l and the plating current is at 5 mA/cm.sup.2, which is equal to
the CCD at the particular acidic concentration, a continuous 1000
.ANG. copper film was formed across a 100 .ANG. Ru film on a
substrate. However, cross-section SEM pictures show that voids were
formed at the copper/Ru interface. When the plating current was
raised to 10 mA/cm.sup.2 (2 times CCD of 5 mA/cm.sup.2) and the
sulfuric acid concentration was maintained at 160 g/l, a continuous
5000 .ANG. copper film was formed on a 100 .ANG. Ru layer with no
voids at the copper/Ru interface.
[0048] One of the reasons for the CCD dependence on bath acidity is
related to the local electrochemical over-potential discussed
above. Plating solution with low acidity has higher resistance.
Therefore, higher CCD is needed to overcome the higher resistance
in a plating bath with low acidity.
[0049] Recent research presented by Chyan et. al. from University
of North Texas in American Chemical Society National Meeting in New
Orleans, La., held in March 23 to Mar. 27, 2003, shows that
ruthenium oxide (RuO.sub.2) has a metal-like conductivity, and
copper also plates and adheres strongly to ruthenium oxide. The
high CCDs observed on as-deposited Ru surface could be a result of
Ru surface oxidation and/or the existence of organic surface
contaminants. The "pure" Ru surface is suspected to be more active
for Cu nucleation. Removing the surface oxide layer or organic
surface contaminants by a pre-treatment process before copper
plating could greatly reduce the plating current and the plating
bath acidity required to form a thin continuous copper layer
without copper/Ru interface voids. FIG. 3 shows the pre-treatment
process flow. In step 301, the substrate with a group VIII metal,
such as Ru, on top is pre-treated by a process, such as annealing
in a reducing gas (e.g. hydrogen gas), to clean the surface of
metal oxide or organic contaminants. At step 302, a copper film is
directly plated on the pre-treated substrate. One possible oxide
reduction reaction is shown in equation (1) below.
RuO.sub.2+2H.sub.2-------->Ru+2H.sub.2O (1)
[0050] A substrate with 100 .ANG. PVD Ru film is pre-treated by
annealing just prior to Cu plating. The annealing process is
performed in the presence of a hydrogen-containing gas, such as a
forming gas, which contains 4% H.sub.2 and 96% N.sub.2, at a
temperature between about room temperature to about 400.degree. C.,
preferably between about 100.degree. C. to about 400.degree. C., a
gas flow rate between about 1 sccm to about 20 slm, and under about
5 mTorr to about 1500 Torr for about 2 seconds to about 5 hours.
The annealing time is preferably within 1 hour for manufacturing
efficiency. The purpose of the substrate annealing is either to
reduce the RuO.sub.2 surface back to Ru and/or to desorb the
organic surface contaminants. In one embodiment, the
hydrogen-containing gas is mixed with non-reactive gases, such as
N.sub.2 or inert gases (e.g. Ar, He, etc.). For the purpose of
desorbing organic surface contaminants, annealing with a
non-reactive gas to Ru, such as N.sub.2 or inert gas (e.g., Ar),
can be used. The annealing process can be performed in a
single-wafer rapid thermal annealing chamber, available from
Applied Materials in Santa Clara, Calif., or in a batch
furnace.
[0051] FIG. 4A illustrates an example of where the magnitude of the
CCD was reduced after the as-deposited Ru substrate was annealed in
the forming gas at 270.degree. C. for 30 seconds in an anneal
chamber described in FIG. 5 below. Curve 401 shows the CCD for
copper plating on an as-deposited Ru substrate surface. Curve 402
shows the much reduced CCD for copper plating on a forming gas
annealed Ru substrate surface. For example, the CCD for a solution
containing 10 g/l of H.sub.2SO.sub.4 lowered the CCD from 40
mA/cm.sup.2 to 8 mA/cm.sup.2 and a plating solution containing 100
g/l of H.sub.2SO.sub.4 lowered the CCD from 10 mA/cm.sup.2 to 3
mA/cm.sup.2. Both curves 401 and 402 show that CCD decreases with
the increase of acid concentration. With the forming gas anneal,
the direct copper plating process can be operated at similar
current densities as the conventional copper plating process. After
the forming gas anneal, the Ru substrate surface tends to become
more hydrophilic, as is expected for a clean and pure Ru surface.
Cu plating onto the forming-gas annealed Ru films must be performed
within 4 hours and preferably within 2 hours, following the
forming-gas anneal, in order to maintain the large reduction in
CCD. If the substrate is exposed to the oxygen or other
contaminants for too long, the CCD will gradually go back to the
pre-anneal state due to reformation of RuO.sub.x or re-deposition
of organic surface contaminants from ambient atmosphere.
[0052] The large reduction of CCD caused by the hydrogen-containing
gas anneal is very important, since the reduction in CCD allows a
Cu film to be deposited at current densities suitable for gapfill
into submicron trench/via structures using acidic CuSO.sub.4 baths
containing all practical acid concentrations in the range from
about 10 g/l to about 300 g/l.
[0053] In one example, SEM pictures taken of a deposited 1000 .ANG.
copper film on annealed 80 .ANG. ALD Ru, using a plating solution
containing a sulfuric acid concentration of 100 g/l and a plating
current density (PCD) of 3 mA/cm.sup.2 (equal to the CCD,
PCD/CCD=1), showed that a continuous copper film was deposited with
no voids between the copper/Ru interface. No voids between the
copper/Ru interface is an indication of good copper (Cu) and Ru
interface integrity and good adhesion of Cu on the annealed Ru
surface. In a second example, SEM pictures taken of a deposited
1000 .ANG. copper film on annealed 80 .ANG. ALD Ru, using a plating
solution containing a sulfuric acid concentration of 100 g/l and a
plating current density of 4.5 mA/cm.sup.2 (or PCD/CCD=1.5), also
showed that a continuous copper film was deposited with no voids
between the copper/Ru interface. Similarly, plating current density
of 7.5 mA/cm.sup.2 (or PCD/CCD=2.5), also achieved a continuous
copper film with no voids between the copper/Ru interface. These
results show that gas anneal pre-treatment lowers the plating
current density and improves the Ru/Cu interface adhesion and
integrity.
[0054] The copper/Ru interface shows good integrity without voids
even when PCD/CCD equals to 1 when Cu is deposited on forming-gas
annealed Ru surface. In contrast, when plating at the CCD (or
PCD/CCD=1), the interface between copper and an un-annealed Ru
surface will develop interfacial voids as described earlier. A
clean Ru surface allows better copper nucleation and deposition and
therefore the interface integrity is improved.
[0055] Another benefit of pre-treating the group VIII metal surface
with hydrogen-containing gas anneal is the improved adhesion
between copper and the group VIII metal. Experimental results have
shown that the adhesion is better between Cu and the pre-treated,
clean and possibly oxide free, Ru surface due to good copper/Ru
interface integrity (no voids). Good interface integrity between
the Cu and the Ru layers can be an important aspect in forming a
reliable semiconductor device. Obviously, having a pre-treated Ru
surface is critical to achieve high quality Cu deposition on Ru
films.
[0056] Another aspect of Cu plating onto a forming-gas annealed Ru
surface is the full substrate surface coverage by the plated Cu
film due to the improved hydrophilicity mentioned above. The step
coverage of copper plating on the substrate features should also
improve since the annealed Ru surface is more hydrophilic and is
more able to draw the plating solution deep into the features.
[0057] In addition to the annealing with a hydrogen-containing gas,
the surface pre-treatment of the group VIII metal prior to direct
copper plating can also be accomplished by other methods. One
example of another pre-treatment method is a cathodic treatment in
a copper-ion-free acid solution. The surface RuO.sub.x film can be
cathodically reduced and the weakly-bound organic surface
contaminants can be expelled from the surface by the cathodic
polarization. One possible reduction reaction is shown in equation
(2) below. The cathodic treatment can be performed in an integrated
cell similar to the copper plating cell, as described below in
association with FIG. 6, or in a treatment cell separated from the
copper plating system. The cathodic treatment cell requires an
anode, a cathode and a copper-ion-free acid bath. The acid could be
sulfuric acid and the concentration should be in the range between
about 10 g/l to about 100 g/l, and preferably in the range between
about 10 g/l to about 50 g/l. But other types of acidic solutions,
such as organic sulfonic acid solutions (e.g. methylsulfonic acid),
can also be used. The acidic bath needs to be free of copper to
prevent copper deposition, which would be poorly nucleated copper
islands, on Ru during the cathodic treatment.
RuO.sub.2+4H*+4e.sup.------>Ru+2H.sub.2O (2)
[0058] The cathodic treatment can be realized through potential
control or current control. With the potential control approach, a
reference electrode is needed to monitor the wafer potential, in
addition to the working electrode, which is the thin as-deposited
Ru film on the wafer surface, and an anode. The preferred reference
electrode is a thin copper wire placed close to the substrate
surface. The potential control can be realized through a
potentiostat. The controlled Ru electrode potential, with respect
to the copper reference electrode, is in the range of about 0 volt
to about -0.5 volt. In addition to RuO.sub.x reduction to Ru,
H.sub.2 evolution could occur on the Ru film surface. With the
current control approach, a cathodic current will be passed between
the substrate with as-deposited Ru and an anode. The current
density should be in the range of about 0.05 mA/cm.sup.2 to about 1
mA/cm.sup.2. The treatment time should be in the range of about 2
seconds to about 30 minutes. However, for throughput concern, the
treatment is preferably kept below 5 minutes.
[0059] After the surface pre-treatment, the substrate will be
placed in a plating cell for copper plating to fill the
interconnect features. The catholyte solution (the solution used to
contact and plate metal/copper onto the substrate) generally
includes several constituents. The constituents generally include a
virgin makeup plating solution (a plating solution that does not
contain any plating additives, such as levelers, suppressors, or
accelerators, such as that provided by Shipley Ronal of
Marlborough, Mass. or Enthone, a division of Cookson Electronics
PWB Materials & Chemistry of London), water (generally included
as part of the VMS, but may also be added), and a plurality of
plating solution additives configured to provide control over
various parameters of the plating process. The virgin plating
solution will generally contain copper sulfate (CuSO.sub.4), water
and acid, such as sulfuric acid. The plurality of additives will
generally include an accelerator, a suppressor and/or a
leveler.
[0060] FIG. 4B illustrates a plot of copper resistivity versus the
plating solution acid concentration for a 5000 .ANG. film plated on
an annealed Ru layer for an as-deposited (or as-plated) copper film
(curve 411) and a film annealed at 270.degree. C. for 30 seconds
(curve 412). The resistivity of the copper film was measured using
a ResMap 4-pt probe sheet resistance measurement tool, which is
manufactured by Creative Design Engineering Inc. of Cupertino,
Calif. The 5000 .ANG. copper films were plated on a 100 .ANG. PVD
Ru at a current density equal to the critical current density
(CCD). The results, as shown in FIG. 4B, illustrate that Cu
resistivity decreases with increasing acidity for both as-deposited
and annealed Cu. In addition, thermal annealing of plated copper at
270.degree. C. for 30 seconds (curve 412) reduces the resistivity
of copper, as compared to the as-deposited (or as-plated) Cu (curve
411). Referring to FIG. 4B, as the acid level was increased from
about 10-40 g/l to about 60 .mu.l, the resistivity of the annealed
Cu was reduced to 1.9 .mu.Ohm-cm (see curve 412). The copper
resistivity was further reduced to 1.7 .mu.Ohm-cm, a value close to
the bulk resistivity of copper, at acidity of about 160 g/l. Higher
acid concentration is therefore desired for direct plating of
copper on Ru surface to reduce copper resistivity. A lower
resitivity cooper layer is desirable since it can improve the speed
of the formed device and reduce the heat generated in the
device.
[0061] Therefore, to assure the copper resistivity is kept as low
as possible the plating catholyte should contain about 50 g/l to
about 300 g/l of sulfuric acid, preferably between about 60 g/l to
about 180 g/l. The sulfuric acid concentration in the range of
about 50 g/l to about 300 g/l is greater than the acid
concentration of conventional plating chemistry of about 10 g/l to
about 40 g/l. In addition to the benefit of lowering the copper
resistivity, high acidity in the plating bath also has the
following benefits. First, the high acid level promotes the
electrochemical activity of the organic additives in the bath.
Second, the acid level will increase the electrochemical
polarization slope to help plating into deep features with high
aspect ratios (AR.gtoreq.2). Third, the high acid level will tend
to clean the barrier layer surface of micro-contaminants that can
weaken the adhesion between the copper deposits and the barrier
metal surface. Fourth, and finally, the high acid level tends to
improve the electrolyte's ability to "wet" the barrier surface,
since it tends to remove oxides and other surface contaminants. The
acid used could be other types of acids, such as sulfonic acid
(including alkane sulfonic acids). The molecular weight of
H.sub.2SO.sub.4 is 98 g/mole. The molarity of 50 g/l sulfuric acid
is 1.0. When dissolved in dilute solution, each H.sub.2SO.sub.4
molecule releases 2H.sup.+ ion. If another type of acid is used,
instead of sulfuric acid, equivalent H.sup.+ concentration range
should be used.
[0062] The desired copper concentration in the catholyte is between
about 20 g/l and about 60 g/l, preferably between about 30 g/l and
about 50 g/l of copper. The copper is generally provided to the
solution via copper sulfate, and/or through the electrolytic
reaction of the plating process wherein copper ions are provided to
the solution via the anolyte from a soluble copper anode positioned
in the anolyte solution. More particularly, copper sulfate
pentahydrate (CuSO.sub.4.5H.sub.2O) may be diluted to obtain a
copper concentration of about 40 g/l, for example. A common acid
and copper source combination is sulfuric acid and copper sulfate,
for example. The catholyte may also contain chlorine (Cl.sup.-)
ions, which can be supplied by the addition of hydrochloric acid or
copper chloride, for example, to the plating solution. The
concentration of the chlorine (Cl.sup.-) ions may be between about
20 ppm and about 100 ppm.
[0063] The plating solution (catholyte) generally contains one or
more plating additives to enhance various properties of the plated
film. The additives may include suppressors at a concentration of
between about 100 ppm and about 1000 ppm, preferably between about
100 ppm and 300 ppm. Exemplary suppressors include ethylene oxide
and propylene oxide copolymers. Additives may also include
accelerators at a concentration of between about 2 ppm and about 50
ppm, preferably within the range of between about 6 ppm and 30 ppm.
Exemplary accelerators are based on sulfopropyl-disulfide (SPS) or
mercapto-propane-sulphonate (MPSA) and their derivatives.
[0064] Additionally, a leveler, such as ViaForm leveler from
Enthone of West Haven, Conn., may optionally be added to the
catholyte solution at a concentration of between about 1 ml/l and
about 12 ml/l, or more particularly, in the range of between about
1.5 ml/l and 4 ml/l. The temperature of the plating bath is
generally maintained between about 10.degree. C. and about
30.degree. C.
[0065] Copper plating can be performed within a cell on the Electra
Cu ECP.RTM. system or the SlimCell Copper Plating system, both of
which are available from Applied Materials, Inc. of Santa Clara,
Calif. FIG. 5 illustrates a top plan view of a SlimCell Copper
Plating system 500. ECP system 500 includes a factory interface
(FI) 530, which is also generally termed a substrate loading
station. Factory interface 530 includes a plurality of substrate
loading stations configured to interface with substrate containing
cassettes 534. A robot 532 is positioned in factory interface 530
and is configured to access substrates contained in the cassettes
534. Further, robot 532 also extends into a link tunnel 515 that
connects factory interface 530 to processing mainframe or platform
513. The position of robot 532 allows the robot to access substrate
cassettes 534 to retrieve substrates therefrom and then deliver the
substrates to one of the processing cells 514, 516 positioned on
the mainframe 513, or alternatively, to the annealing station 535.
Similarly, robot 532 may be used to retrieve substrates from the
processing cells 514, 516 or the annealing chamber 535 after a
substrate processing sequence is complete. In this situation robot
532 may deliver the substrate back to one of the cassettes 534 for
removal from system 500.
[0066] The annealing station 535, which will be further discussed
herein, generally includes a two position annealing chamber,
wherein a cooling plate/position 536 and a heating plate/position
537 are positioned adjacently with a substrate transfer robot 540
positioned proximate thereto, e.g., between the two stations. The
robot 540 is generally configured to move substrates between the
respective heating plate 537 and cooling plate 536. Further,
although the annealing chamber 535 is illustrated as being
positioned such that it is accessed from the link tunnel 515,
embodiments of the invention are not limited to any particular
configuration or placement. In one embodiment, the annealing
station 535 may be positioned in direct communication with the
mainframe 513, i.e., accessed by mainframe robot 520. For example,
as illustrated in FIG. 5, the annealing station 535 may be
positioned in direct communication with the link tunnel 515, which
allows for access to mainframe 513, and as such, the annealing
chamber 535 is illustrated as being in communication with the
mainframe 513. Details of a suitable annealing chamber are
described in commonly assigned U.S. patent application No.
60/463,860, titled "Two Position Anneal Chamber", filed on Apr. 18,
2003.
[0067] In one embodiment, the annealing process is performed in an
integrated annealing chamber, as shown as annealing chamber 535 in
FIG. 5. In another embodiment, the annealing process is performed
in a separate annealing system. In other embodiments, the annealing
process is performed in a single-wafer chamber or a batch
furnace.
[0068] As mentioned above, ECP system 500 also includes a
processing mainframe 513 having a substrate transfer robot 520
centrally positioned thereon. Robot 520 generally includes one or
more arms/blades 522, 524 configured to support and transfer
substrates thereon. Additionally, the robot 520 and the
accompanying blades 522, 524 are generally configured to extend,
rotate, and vertically move so that the robot 520 may insert and
remove substrates to and from a plurality of processing locations
502, 504, 506, 508, 510, 512, 514, 516 positioned on the mainframe
513. Similarly, factory interface robot 532 also includes the
ability to rotate, extend, and vertically move its substrate
support blade, while also allowing for linear travel along the
robot track that extends from the factory interface 530 to the
mainframe 513. Generally, process locations 502, 504, 506, 508,
510, 512, 514, 516 may be any number of processing cells utilized
in an electrochemical plating platform. More particularly, the
process locations may be configured as electrochemical plating
cells, rinsing cells, bevel clean cells, spin rinse dry cells,
substrate surface cleaning cells (which collectively includes
cleaning, rinsing, and etching cells), electroless plating cells,
metrology inspection stations, and/or other processing cells that
may be beneficially used in conjunction with a plating platform.
Each of the respective processing cells and robots are generally in
communication with a process controller 511, which may be a
microprocessor-based control system configured to receive inputs
from both a user and/or various sensors positioned on the system
500 and appropriately control the operation of system 500 in
accordance with the inputs.
[0069] FIG. 6 illustrates a partial perspective and sectional view
of an exemplary plating cell 600 that may be implemented in
processing locations 502, 504, 506, 508, 510, 512, 514, 516 of FIG.
5. The electrochemical plating cell 600 generally includes an outer
basin 601 and an inner basin 602 positioned within outer basin 601.
Inner basin 602 is generally configured to contain a plating
solution that is used to plate a metal, e.g., copper, onto a
substrate during an electrochemical plating process. During the
plating process, the plating solution is generally continuously
supplied to inner basin 602 (at about 1 gallon per minute for a 10
liter plating cell, for example), and therefore, the plating
solution continually overflows the uppermost point (generally
termed a "weir") of inner basin 602 and is collected by outer basin
601 and drained therefrom for chemical management and
recirculation. Plating cell 600 is generally positioned at a tilt
angle, i.e., the frame portion 603 of plating cell 600 is generally
elevated on one side such that the components of plating cell 600
are tilted between about 30 and about 300, or generally between
about 40 and about 100 for optimal results. The frame member 603 of
plating cell 600 supports an annular base member on an upper
portion thereof. Since frame member 603 is elevated on one side,
the upper surface of base member 604 is generally tilted from the
horizontal at an angle that corresponds to the angle of frame
member 603 relative to a horizontal position. Base member 604
includes an annular or disk shaped recess formed into a central
portion thereof, the annular recess being configured to receive a
disk shaped anode member 605. Base member 604 further includes a
plurality of fluid inlets/drains 609 extending from a lower surface
thereof. Each of the fluid inlets/drains 609 are generally
configured to individually supply or drain a fluid to or from
either the anode compartment or the cathode compartment of plating
cell 600. Anode member 605 generally includes a plurality of slots
607 formed therethrough, wherein the slots 607 are generally
positioned in parallel orientation with each other across the
surface of the anode 605. The parallel orientation allows for dense
fluids generated at the anode surface to flow downwardly across the
anode surface and into one of the slots 607. Plating cell 600
further includes a membrane support assembly 606. Membrane support
assembly 606 is generally secured at an outer periphery thereof to
base member 604, and includes an interior region configured to
allow fluids to pass therethrough. A membrane 608 is stretched
across the support 606 and operates to fluidly separate a catholyte
chamber and anolyte chamber portions of the plating cell. The
membrane support assembly may include an o-ring type seal
positioned near a perimeter of the membrane, wherein the seal is
configured to prevent fluids from traveling from one side of the
membrane secured on the membrane support 606 to the other side of
the membrane. A diffusion plate 610, which is generally a porous
ceramic disk member and is configured to generate a substantially
laminar flow or even flow of fluid in the direction of the
substrate being plated, is positioned in the cell between membrane
608 and the substrate being plated. The exemplary plating cell is
further illustrated in commonly assigned U.S. patent application
Ser. No. 10/268,284, which was filed on Oct. 9, 2002 under the
title "Electrochemical Processing Cell", claiming priority to U.S.
Provisional Application Ser. No. 60/398,345, which was filed on
Jul. 24, 2002, both of which are incorporated herein by reference
in their entireties.
[0070] In operation, the plating cell 600 of the invention provides
a small volume (electrolyte volume) processing cell that may be
used for copper electrochemical plating processes, for example. The
plating cell 600 may be horizontally positioned or positioned in a
tilted orientation, i.e., where one side of the cell is elevated
vertically higher than the opposing side of the cell, as
illustrated in FIG. 6. If the plating cell 600 is implemented in a
tilted configuration, then a tilted head assembly and substrate
support member may be utilized to immerse the substrate at a
constant immersion angle, i.e., immerse the substrate such that the
angle between the substrate and the upper surface of the
electrolyte does not change during the immersion process. Further,
the immersion process may include a varying immersion velocity,
i.e., an increasing velocity as the substrate becomes immersed in
the electrolyte solution. The combination of the constant immersion
angle and the varying immersion velocity operates to eliminate air
bubbles on the substrate surface.
[0071] Assuming a tilted implementation is utilized, a substrate is
first immersed into a plating solution contained within inner basin
602. FIG. 7A shows the plating current as a function of time for a
substrate with a Group VIII metal, such as Ru, barrier layer.
Between time 0 to time t.sub.1 is the substrate immersion period.
There is no electrical bias current or voltage applied on the
substrate during this period, which is very different from the
plating process on copper seed layer. Copper plating on substrate
with copper seed layer requires an electrical bias during the
immersion period to ensure that the copper seed layer does not
dissolve, or corrode, in the plating solution to cause
discontinuity in copper seed layer. During the immersion period for
copper plating on substrate with copper seed layer, typically a
constant cathodic voltage of between about 0.8 volt to about 3
volts is applied.
[0072] Once the substrate is immersed in the plating solution, the
plating process includes applying a forward plating bias which
promotes the deposition of the metal onto the substrate. The
electrical bias can be applied as a constant current or voltage, a
ramped current or voltage, or a stepped current or voltage to
achieve the deposition characteristics desired. An initial higher
current level is used to help the nucleation of the copper deposit
on the substrate surface. For example, during the nucleation
period, which is between t.sub.1 to t.sub.2 in FIG. 7A, a constant
bias current, I.sub.1, in the range of about 5 mA/cm.sup.2 to about
20 mA/cm.sup.2 is maintained. The current density during this
period should be equal to or higher than the critical current,
preferably higher than the critical current density for faster
nucleation to provide a thin continuous (less than 200 .ANG.) Cu
film on top of Ru underlayer. The nucleation period (t.sub.1 to
t.sub.2) lasts between about 0.1 second to about 5 seconds.
[0073] After the nucleation step, a lower current level is
preferably used to gap-fill the features on the substrate. The
gap-fill process is performed between times between t.sub.2 to
t.sub.3. In one embodiment, a constant cathodic current is applied
during this period, I.sub.2, which may be in a range between about
2 mA/cm.sup.2 and about 10 mA/cm.sup.2. This current density range
may be optimized for bottom-up gapfill. This gap-fill period,
t.sub.2 to t.sub.3, typically lasts between about 3 seconds to
about 20 seconds to deposit about 200 .ANG. to about 3000 .ANG. of
copper on the substrate surface.
[0074] A low current density during the gap-fill period is
beneficial to fill the desired features, but the deposition rate is
slow. Therefore, after a desired amount of copper film has been
deposited during the gap-fill period, the current density is
increased to improve deposition rate and chamber throughput. In one
embodiment, an intermediate step is added to the processing
sequence before the final bulk fill step to increase the deposition
rate and also assure that the feature will be filled. The
intermediate step can be run at a current density, I.sub.3, which
is between the gap-fill current density, I.sub.2, and bulk-fill
current density, I.sub.4, which is applied for a period of time
between t.sub.3 to t.sub.4. The current density, I.sub.3, in this
intermediate step period, t.sub.3 to t.sub.4, may be in a range
between about 10 mA/cm.sup.2 and about 30 mA/cm.sup.2 and the
duration t.sub.3 to t.sub.4 may be between about 0 second to about
10 seconds. In one embodiment, a final bulk-fill step is used in
the gap-fill process at a current density, I.sub.4, in a range
between about 40 mA/cm.sup.2 and about 60 mA/cm.sup.2. The
duration, t.sub.4 to t.sub.5, of the bulk fill step may be between
about 10 seconds and about 60 seconds. The bulk-fill plating will
last until a layer having a final thickness has been reached, which
may be between about 4000 .ANG. and about 8000 .ANG..
[0075] FIG. 7B illustrates the corresponding plating voltage as a
function of time for the current density curves depicted in FIG.
7A. The plating voltage decreases slightly from t.sub.1 to t.sub.2
due to the formation of the initial thin copper film. Similarly,
the plating voltages decrease slightly from t.sub.2 to t.sub.3,
from t.sub.3 to t.sub.4, and from t.sub.4 to t.sub.5 due to the
increase of copper film thickness on the substrate surface.
[0076] In another embodiment, the plating voltage is used to
control the deposition of the plated copper film. FIG. 8A
illustrates a plot of plating voltage as a function of time for a
typical substrate that has 100 .ANG. of a Group VIII metal, such as
Ru, deposited on the wafer surface. Referring to FIG. 8A, between
time 0 to time t.sub.11 is the substrate immersion period. In one
embodiment, no electrical bias current or voltage is applied to the
substrate during the immersion period. Similar to the process
described in FIGS. 7A and 7B, once the substrate is immersed in the
plating solution, a forward plating bias is applied which promotes
the deposition of the metal onto the substrate. The electrical bias
can be applied as a constant voltage, a ramped voltage, or a
stepped voltage to achieve the deposition characteristics desired.
In one embodiment, an initial higher voltage level is applied to
help the nucleation of the copper deposited on the substrate
surface. During the nucleation period, which is between t.sub.11 to
t.sub.12 in FIG. 8A, a constant bias voltage, V.sub.1, in the range
of about 1 volt to about 10 volts is maintained. The plating
voltage during this period should make the current density equal to
or higher than the critical current density, preferably higher than
the critical current density for faster nucleation, as mentioned
earlier. The nucleation period (t.sub.11 to t.sub.12) may last
between about 0.1 second to about 5 seconds.
[0077] After the nucleation period, a lower voltage level is
preferably used to assist gap-fill of features on the substrate.
The gap-fill period will last for the period between t.sub.12 to
t.sub.13. In one embodiment a constant cathodic voltage, V.sub.2,
applied during the gap-fill period may be between about 0.2 volt
and about 2 volts. The gap-fill period, t.sub.12 to t.sub.13,
typically lasts between about 3 seconds to about 20 seconds to
deposit about 200 .ANG. to about 3000 .ANG. of copper on the
substrate surface.
[0078] The lower voltage (equal to lower current) during the
gap-fill period will improve gap-fill, but also lower the
deposition rate of the plated film. Therefore, after the gap-fill
period has been completed the voltage level can be raised to
improve deposition rate and chamber throughput. In one embodiment,
an intermediate step is added before the final bulk fill step to
increase the deposition rate and also assure that the features will
be filled. The intermediate step can be run at a voltage, V.sub.3,
which is between the gap-fill voltage, V.sub.2, and the bulk-fill
voltage, V.sub.4, and is applied for the period between t.sub.13 to
t.sub.14. The voltage, V.sub.3, in this transitional period,
t.sub.13 to t.sub.14, may be between about 2 volts and about 5
volts. The duration of the intermediate step, t.sub.13 to t.sub.14,
may be between about 0 second and about 10 seconds. In one
embodiment, the bulk-fill voltage, V.sub.4, may be between about 2
volts and about 10 volts which may be used to complete the gap-fill
process. The duration, t.sub.14 to t.sub.15, of the bulk fill step
may be between about 10 seconds to about 60 seconds. The bulk-fill
plating will last until a layer having a final thickness of between
about 4000 .ANG. and about 8000 .ANG. has been deposited.
[0079] FIG. 8B illustrates the corresponding plating current as a
function of time for FIG. 8A. The plating current increase slightly
from t.sub.11 to t.sub.12 due to the formation of the initial thin
copper film. Similarly, the plating currents increase slightly from
t.sub.12 to t.sub.13, from t.sub.13 to t.sub.14, and from t.sub.14
to t.sub.15 due to the increase of copper film thickness on the
substrate surface.
[0080] During the nucleation periods, such as t.sub.1 to t.sub.2 in
FIGS. 7A and 7B and t.sub.11 to t.sub.12 in FIGS. 8A and 8B, the
electrical bias can also be pulsed as shown in FIG. 9A or be a
ramped-down bias as shown in FIG. 9B.
[0081] Further, during the application of each of the above noted
plating biases, the substrate may be rotated at between about 10
rpm and about 200 rpm, and preferably between about 20 rpm and
about 100 rpm.
EXAMPLE
[0082] FIG. 10 shows the SEM of excellent gapfill of plated copper
on an annealed Ru surface in 0.14 .mu.m.times.0.8 .mu.m trenches.
The as-deposited Ru is an 80 .ANG. ALD Ru. The pre-treatment
process was performed on the substrate using a forming gas to
anneal the wafer at temperature of 300.degree. C. for 3 minutes.
The plating solution used to gap-fill the features contained 40 g/l
of copper, 100 g/l of sulfuric acid, 50 ppm of Cl ions, 12 ppm of
sulfopropyl-disulfide (SPS) accelerator, 200 ppm of ethylene oxide
and propylene oxide copolymers suppressor and 2 ml/l of ViaForm
leveler. The plating bath was maintained at 18.degree. C. The
copper plating current was 10 mA/cm.sup.2 for the first 100 .ANG.
(for nucleation) and 5 mA/cm.sup.2 for the remaining 1900 .ANG.
deposition (for gap fill). Additional bulk-fill plating can be
performed to reach the desired total thickness.
[0083] The experimental results and discussion related to Ru is
merely used as examples. The inventive concept can be applied to
other group VIII metals, such as rhodium (Rh), palladium (Pd),
osmium (Os), iridium (Ir), and platinum (Pt).
[0084] Although several preferred embodiments which incorporate the
teachings of the present invention have been shown and described in
detail, those skilled in the art can readily devise many other
varied embodiments that still incorporate these teachings.
* * * * *