U.S. patent application number 11/175562 was filed with the patent office on 2005-11-03 for stacked module systems and methods.
This patent application is currently assigned to Staktek Group, L.P.. Invention is credited to Partridge, Julian, Wehrly, James Douglas JR..
Application Number | 20050242423 11/175562 |
Document ID | / |
Family ID | 35394816 |
Filed Date | 2005-11-03 |
United States Patent
Application |
20050242423 |
Kind Code |
A1 |
Partridge, Julian ; et
al. |
November 3, 2005 |
Stacked module systems and methods
Abstract
The present invention stacks chip scale-packaged integrated
circuits (CSPs) into modules that conserve PWB or other board
surface area. In a preferred embodiment in accordance with the
invention, a form standard associated with one or more CSPs
provides a physical form that allows many of the varying package
sizes found in the broad family of CSP packages to be used to
advantage while employing a standard connective flex circuitry
design. In a preferred embodiment, the contacts of the lower CSP
will be compressed before flex circuitry is attached to a
combination of the CSP and a form standard to create lower profile
contacts between CSP and the flex circuitry.
Inventors: |
Partridge, Julian; (Austin,
TX) ; Wehrly, James Douglas JR.; (Austin,
TX) |
Correspondence
Address: |
J. SCOTT DENKO
ANDREWS & KURTH LLP
111 CONGRESS AVE., SUITE 1700
AUSTIN
TX
78701
US
|
Assignee: |
Staktek Group, L.P.
|
Family ID: |
35394816 |
Appl. No.: |
11/175562 |
Filed: |
July 5, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11175562 |
Jul 5, 2005 |
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10836855 |
Apr 30, 2004 |
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10836855 |
Apr 30, 2004 |
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10453398 |
Jun 3, 2003 |
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6914324 |
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10453398 |
Jun 3, 2003 |
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10005581 |
Oct 26, 2001 |
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6576992 |
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Current U.S.
Class: |
257/686 ;
257/E23.065; 257/E23.177; 257/E25.023 |
Current CPC
Class: |
H01L 2225/107 20130101;
H01L 2924/3011 20130101; H05K 2201/056 20130101; H01L 2224/32225
20130101; H01L 23/3114 20130101; H01L 23/5387 20130101; H01L 23/36
20130101; H01L 2924/00 20130101; H05K 1/141 20130101; H05K
2201/10734 20130101; H01L 23/49816 20130101; H01L 2224/16237
20130101; H05K 1/189 20130101; H01L 2924/01327 20130101; H05K 3/363
20130101; H01L 23/4985 20130101; H01L 23/13 20130101; H01L 25/105
20130101; H01L 2224/73253 20130101; H01L 2225/1094 20130101; H01L
2924/01327 20130101; H05K 2201/10689 20130101; H05K 1/147
20130101 |
Class at
Publication: |
257/686 |
International
Class: |
H01L 023/02 |
Claims
1-20. (canceled)
21. A high-density circuit module comprising: a first CSP having a
planar surface rising from which are contacts, the contacts rising
from the planar surface by a height D1; a second CSP disposed above
the first CSP in stacked disposition; a first form standard
disposed, in substantial part, above the first CSP; flex circuitry
connecting the first and second CSPs; at least one metallic bond
attaching the flex circuitry and the first form standard; and
module contacts, the module contacts extending from the flex
circuit by a height Dm, where Dm is greater than D1.
22. The high-density circuit module of claim 21 further comprising
a second form standard.
23. The high-density circuit module of claim 22 in which the flex
circuitry is comprised of a first flex circuit and a second flex
circuit which are each attached to the first form standard with at
least one metallic bond.
24. The high-density circuit module of claim 21 in which the
metallic bond comprises tin and gold.
25. The high-density circuit module of claim 21 in which the
metallic bond is created by combining a first metallic material
applied to the first form standard and a second metallic material
from which the flex circuitry is comprised.
26. A high-density circuit module comprising: a first CSP; a second
CSP stacked above the first CSP; a first form standard associated
with the first CSP; a second form standard associated with the
second CSP; and flex circuitry connecting the first and second
CSPs, the flex circuitry being attached to the first form standard
and comprising at least two conductive layers.
27. The high-density circuit module of claim 26 in which the
attachment of the flex circuitry to the first form standard is with
at least one metallic bond.
28. The high-density module of claim 27 in which the at least one
metallic bond is comprised of a first metallic material and a
second metallic material wherein the first metallic material is
comprised of tin.
29. The high-density module of claim 27 in which the flex circuitry
is comprised of a first flex circuit and a second flex circuit and
each of the first and second flex circuits is attached to the first
form standard with at least one metallic bond.
30. The high-density module of claim 26 in which the flex circuitry
is attached to the first form standard with adhesive.
31. (canceled)
Description
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 10/453,398, filed Jun. 3, 2003, which is a
continuation-in-part of U.S. patent application Ser. No.
10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 and a
continuation-in-part of PCT App. No. PCT/US03/29000, filed Sep. 15,
2003.
[0002] U.S. patent application Ser. No. 10/453,398, filed Jun. 3,
2003, is hereby incorporated by reference.
[0003] PCT Pat. App. No. PCT/US03/29000, filed Sep. 15, 2003, is
hereby incorporated by reference.
TECHNICAL FIELD
[0004] The present invention relates to aggregating integrated
circuits and, in particular, to stacking integrated circuits in
chip-scale packages.
BACKGROUND OF THE INVENTION
[0005] A variety of techniques are used to stack packaged
integrated circuits. Some methods require special packages, while
other techniques stack conventional packages.
[0006] The predominant package configuration employed during the
past decade has encapsulated an integrated circuit (IC) in a
plastic surround typically having a rectangular configuration. The
enveloped integrated circuit is connected to the application
environment through leads emergent from the edge periphery of the
plastic encapsulation. Such "leaded packages" have been the
constituent elements most commonly employed by techniques for
stacking packaged integrated circuits.
[0007] Leaded packages play an important role in electronics, but
efforts to miniaturize electronic components and assemblies have
driven development of technologies that preserve circuit board
surface area. Because leaded packages have leads emergent from
peripheral sides of the package, leaded packages occupy more than a
minimal amount of circuit board surface area. Consequently,
alternatives to leaded packages known as chip scale packaging or
"CSP" have recently gained market share.
[0008] CSP refers generally to packages that provide connection to
an integrated circuit through a set of contacts (often embodied as
"bumps" or "balls") arrayed across a major surface of the package.
Instead of leads emergent from a peripheral side of the package,
contacts are placed on a major surface and typically emerge from
the planar bottom surface of the package. The absence of "leads" on
package sides renders most stacking techniques devised for leaded
packages inapplicable for CSP stacking.
[0009] A variety of previous techniques for stacking CSPs typically
present complex structural arrangements and thermal or high
frequency performance issues. For example, thermal performance is a
characteristic of importance in CSP stacks.
[0010] What is needed, therefore, is a technique and system for
stacking CSPs that provides a thermally efficient, reliable
structure that performs well at higher frequencies but does not add
excessive height to the stack yet allows production at reasonable
cost with readily understood and managed materials and methods.
SUMMARY OF THE INVENTION
[0011] The present invention stacks chip scale-packaged integrated
circuits (CSPs) into modules that conserve PWB or other board
surface area. Although the present invention is applied most
frequently to chip scale packages that contain one die, it may be
employed with chip scale packages that include more than one
integrated circuit die. Multiple numbers of CSPs may be stacked in
accordance with the present invention. The CSPs employed in stacked
modules devised in accordance with the present invention are
connected with flex circuitry. That flex circuitry may exhibit one
or two or more conductive layers.
[0012] In the present invention, at least one form standard is
employed to provide a physical form that allows many of the varying
package sizes found in the broad family of CSP packages to be used
to advantage while employing a standard connective flex circuitry
design. In a preferred embodiment, the form standard will be
devised of heat transference material, a metal, for example, such
as copper would be preferred, to improve thermal performance.
[0013] In constructing modules in accordance with some preferred
modes of the invention, CSP contacts are reduced in height to
create lower profile modules. With some of the preferred methods of
the present invention, the compressed contacts mix with solder
paste and set beneficially as lower diameter contacts. This creates
low profile embodiments of the modules of the present
invention.
SUMMARY OF THE DRAWINGS
[0014] FIG. 1 is an elevation view of a high-density circuit module
devised in accordance with a preferred two-high embodiment of the
present invention.
[0015] FIG. 2 depicts, in enlarged view, the area marked "A" in
FIG. 1.
[0016] FIG. 3A depicts a part of an exemplar CSP before its
incorporation into a module or unit of the present invention.
[0017] FIG. 3B depicts a part of an exemplar CSP after one of its
contacts has been reduced in height according to a preferred mode
of the present invention.
[0018] FIG. 4 depicts a preferred construction method that may be
employed in making a high-density module devised in accordance with
a preferred embodiment of the present invention.
[0019] FIG. 5 depicts a preferred construction method that may be
employed in making a high-density module devised in accordance with
a preferred embodiment of the present invention.
[0020] FIG. 6 depicts a unit that may be employed in a module
devised in accordance with a preferred embodiment of the present
invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
[0021] FIG. 1 shows a two-high module 10 devised in accordance with
a preferred embodiment of the invention. FIG. 1 has an area marked
"A" that is subsequently shown in enlarged depiction in FIG. 2.
Module 10 is comprised of two CSPs: CSP 16 and CSP 18. Each of the
CSPs has an upper surface 20 and a lower surface 22 and opposite
lateral edges 24 and 26 and typically include at least one
integrated circuit surrounded by a plastic body 27. The body need
not be plastic, but a large majority of packages in CSP
technologies are plastic. Those of skill will realize that the
present invention may be devised to create modules with different
size CSPs and that the constituent CSPs may be of different types
within the same module 10. For example, one of the constituent CSPs
may be a typical CSP having lateral edges 24 and 26 that have an
appreciable height to present a "side" while other constituent CSPs
of the same module 10 may be devised in packages that have lateral
edges 24 and 26 that are more in the character of an edge rather
than a side having appreciable height.
[0022] The term CSP should be broadly considered in the context of
this application. Collectively, these will be known herein as chip
scale packaged integrated circuits (CSPs) and preferred embodiments
will be described in terms of CSPs, but the particular
configurations used in the explanatory figures are not, however, to
be construed as limiting. For example, the elevation views are
depicted with CSPs of a particular profile known to those in the
art, but it should be understood that the figures are exemplary
only. The invention may be employed to advantage in the wide range
of CSP configurations available in the art where an array of
connective elements is available from at least one major surface.
The invention is advantageously employed with CSPs that contain
memory circuits, but may be employed to advantage with logic and
computing circuits where added capacity without commensurate PWB or
other board surface area consumption is desired.
[0023] Typical CSPs, such as, for example, ball-grid-array ("BGA"),
micro-ball-grid array, and fine-pitch ball grid array ("FBGA")
packages have an array of connective contacts embodied, for
example, as leads, bumps, solder balls, or balls that extend from
lower surface 22 of a plastic casing in any of several patterns and
pitches. An external portion of the connective contacts is often
finished with a ball of solder. Shown in FIG. 1 are contacts 28
along lower surfaces 22 of the illustrated constituent CSPs 16 and
18. Contacts 28 provide connection to the integrated circuit or
circuits within the respective packages.
[0024] In FIG. 1, flex circuitry ("flex", "flex circuits" or
"flexible circuit structures") is shown connecting constituent CSPs
16 and 18. A single flex circuit may be employed in place of the
two depicted flex circuits 30 and 32. The entirety of the flex
circuitry may be flexible or, as those of skill in the art will
recognize, a PCB structure made flexible in certain areas to allow
conformability around CSPs and rigid in other areas for planarity
along CSP surfaces may be employed as an alternative flex circuit
in the present invention. For example, structures known as
rigid-flex may be employed.
[0025] A first form standard 34 is shown disposed adjacent to upper
surface 20 of CSP 18. A second form standard is also shown
associated with CSP 16. Form standard 34 may be fixed to upper
surface 20 of the respective CSP with an adhesive 36 which
preferably is thermally conductive. Form standard 34 may also, in
alternative embodiments, merely lay on upper surface 20 or be
separated from upper surface 20 by an air gap or medium such as a
thermal slug or non-thermal layer. A form standard may be employed
on each CSP in module 10 for heat extraction enhancement as shown
in the depiction of FIG. 1 which is a preferred mode for the
present invention where heat extraction is a high priority. In
other embodiments, form standard 34 may be inverted relative to the
corresponding CSP so that, for example, it would be opened over the
upper surface 20 of CSP 18.
[0026] Form standard 34 is, in a preferred embodiment, devised from
copper to create, as shown in the depicted preferred embodiment of
FIG. 1, a mandrel that mitigates thermal accumulation while
providing a standard sized form about which flex circuitry is
disposed. Form standard 34 may also be devised from nickel plated
copper in preferred embodiments. Form standard 34 may take other
shapes and forms such as, for example, an angular "cap" that rests
upon the respective CSP body. It also need not be thermally
enhancing although such attributes are preferable. The form
standard 34 allows the invention to be employed with CSPs of
varying sizes, while articulating a single set of connective
structures useable with the varying sizes of CSPs. Thus, a single
set of connective structures such as flex circuits 30 and 32 (or a
single flexible circuit in the mode where a single flex is used in
place of the flex circuit pair 30 and 32 as shown in FIG. 5) may be
devised and used with the form standard 34 method and/or systems
disclosed herein to create stacked modules with CSPs having
different sized packages. This will allow the same flex circuitry
set design to be employed to create iterations of a stacked module
10 from constituent CSPs having a first arbitrary dimension X
across attribute Y (where Y may be, for example, package width), as
well as modules 10 from constituent CSPs having a second arbitrary
dimension X prime across that same attribute Y. Thus, CSPs of
different sizes may be stacked into modules 10 with the same set of
connective structures (i.e., flex circuitry). Further, as those of
skill will recognize, mixed sizes of CSPs may be implemented into
the same module 10, such as would be useful to implement
embodiments of a system-on-a-stack such as those disclosed in
co-pending application PCT/US03/29000, filed Sep. 15, 2003, which
is incorporated by reference and commonly owned by the assignee of
the present application.
[0027] In one preferred embodiment, portions of flex circuits 30
and 32 are fixed to form standard 34 by bonds 35 which are, in some
preferred modes, metallurgical bonds created by placing on form
standard 34, a first metal layer such as tin, for example, which,
when melted, combines with a second metal that was placed on the
flex circuitry or is part of the flex circuitry (such as the gold
plating on a conductive layer of the flex) to form a higher melting
point intermetallic bond that will not remelt during subsequent
reflow operations as will be described further.
[0028] FIG. 2 depicts in enlarged view, the area marked "A" in FIG.
1. FIG. 2 illustrates in a preferred embodiment, an arrangement of
a form standard 34 and its relation to flex circuitry 32 in a
two-high module 10 that employs a form standard 34 with each of
CSPs 16 and 18. The internal layer constructions of flex circuitry
32 are not shown in this figure. Shown in greater detail than in
FIG. 1, are bonds 35 that will be described with reference to later
Figs. Also shown in FIG. 2 is an application of adhesive 36 between
form standards 34 and CSPs 18 and 16. In a preferred embodiment, an
adhesive 33 may also be employed between form standard 34
associated with CSP 16 and the flex circuitry 32. Adhesive 33 will
preferably be thermally conductive.
[0029] Although those of skill will recognize that the Figs. are
not drawn to scale, the contacts 28 of CSPs 16 and 18 have been
shown to have (although need not exhibit in every embodiment) a
limited height above the lower surface 22 of the corresponding CSP.
FIG. 3A depicts a contact 28 of CSP 18 before that contact 28 has
undergone the step of height reduction described further
subsequently. As shown, contact 28 rises a height Dx above surface
22 of CSP 18. FIG. 3B depicts contact 28 after the step of height
reduction described further subsequently. In FIG. 3B, the height
reduction was conducted before attachment of a form standard 34 to
CSP 18. As is later explained, height reduction of contacts 28 may
occur either before or after attachment of a form standard 34 to
CSP 18. As shown, contact 28 rises a height Dc above surface 22 of
CSP 18. With reference to FIG. 2, in some embodiments, contacts 28
may rise a height D1 above said surface 22 after incorporation of
CSP 18 into module 10 or later shown unit 39 (FIG. 6.). Height D1
is greater than the height Dc such contacts exhibit after the step
of contact height reduction, but before attachment of flex
circuitry as shown in FIGS. 3B, 4, and 5. Even so, in preferred
embodiments, height D1 of contacts 28 after CSP 18 is incorporated
in a module 10 (such as shown in FIG. 2) or unit 39 (such as shown
in FIG. 6) is less than height Dx which is the height above surface
22 exhibit by a CSP contact 28 before incorporation of CSP 18 into
either a unit 39 (shown in FIG. 6) or module 10 and before contact
height reduction according to preferred modes of the present
invention. As shown in FIG. 2, module contacts 38 rise a height of
Dm from flex circuit 32 and, in preferred embodiments of module 10,
D1 is less than Dm.
[0030] With reference to FIG. 4, combination 37 is depicted as
consisting of form standard 34 attached to CSP 18 which, when
attached to flex circuitry, is adapted to be employed in module 10.
The attachment of form standard 34 to CSP 18 may be realized with
adhesive depicted by reference 36 which is preferably a film
adhesive that is applied by heat tacking either to form standard 34
or CSP 18. A variety of other methods may be used to adhere form
standard 34 to CSP 18 and in some embodiments, no adhesion may be
used
[0031] As further depicted in FIG. 4, flex circuits 30 and 32 are
prepared for attachment to combination 37 by the application of
solder paste 41 at sites that correspond to contacts 28 of CSP 18
to be connected to the flex circuitry. Also shown are glue
applications indicated by references 43 which are, when glue is
employed to attach form standard 34 to the flex circuitry,
preferably liquid glue.
[0032] As shown in this embodiment, contacts 28 of CSP 18 have
height Dc which is less than height D1 shown in earlier FIG. 2. The
depicted contacts 28 of CSP 18 are reduced in height by compression
or other means of height reduction before attachment of combination
37 to the flex circuitry. This compression may be done before or
after attachment of form standard 34 and CSP 18 with
after-attachment compression being preferred. Contacts 28 may be
reduced in height while in a solid or semi-solid state. Unless
reduced in height, contacts 28 on CSP 18 tend to "sit-up" on solder
paste sites 41 during creation of module 10. This causes the glue
line between the flex circuitry and form standard 34 to be thicker
than may be desired. The glue reaches to fill the gap between the
flex and form standard 34 that results from the distancing of the
attached form standard 34 from the flex by the contacts 28
"sitting" upon the solder paste sites 41.
[0033] With a thicker glue line between flex and form standard 34,
upon reflowing, the solder in contacts 28 mixes with solder paste
41 and reaches to span the space between CSP 18 and the flex
circuitry which is now a fixed distance away from CSP 18. This
results in a larger vertical dimension for contact 28 than is
necessary due to the higher glue line and, consequently, a module
10 with a taller profile. The higher glue line was created by not
reducing the contact diameters before attachment of the flex
circuitry to the form standard 34 (or the form standard part of
combination 37). With the preferred methods of the present
invention, however, upon reflow, the compressed contacts 28 mix
with solder paste 41 and set beneficially as lower diameter
contacts 28. The resulting unit combining combination 37 with flex
circuitry may then be employed to create low profile embodiment of
module 10.
[0034] FIG. 5 depicts a preferred alternative and additional method
to reduce module 10 height while providing a stable bond 35 between
form standard 34 and the flex circuitry. The preferable bonds 35
that were earlier shown in FIG. 1 may be created by the following
technique. As shown in FIG. 5, a first metallic material indicated
by reference 47 has been layered on, or appended or plated to form
standard 34. A second metallic material represented by reference 49
on flex circuit 30 is provided by, for example, applying a thin
layer of metal to flex circuit 30 or, by exposing part of a
conductive layer of the flex circuit. When form standard 34 is
brought into proximity with the flex circuitry, and localized
heating is applied to the area where the first and second metals 47
and 49 are adjacent, an intermetallic bond 35 is created. A
preferred metallic material 47 would be a thin layer of tin applied
to create a layer about 0.0005". When melted to combine with the
gold of a conductive layer of flex circuitry exposed at that, for
example, site, the resulting intermetallic bond 35 will have a
higher melting point resulting in the additional advantage of not
re-melting during subsequent re-flow operations at particular
temperatures.
[0035] A variety of methods may be used to provide the localized
heating appropriate to implement the metallic bonding described
here including localized heat application with which many in the
art are familiar as well as ultrasonic bonding methods where the
patterns in the flex circuitry are not exposed to the vibration
inherent in such methods and the metals chosen to implement the
bonds have melting points within the range achieved by the
ultrasonic method.
[0036] FIG. 6 depicts unit 39 comprised from flex circuitry 31
which, in this depicted embodiment, is a single flex circuit, and
form standard 34 and CSP 18. Heat is shown as being applied to area
50 where the first metallic material 47 and second metallic
material 49 were made adjacent by bringing combination 37 and flex
circuitry 31 together.
[0037] The creation of intermetallic bonds may also be employed to
bond combination 37 to flex circuitry along other sites where form
standard 34 and flex circuitry are adjacent such as, for example,
on sites or continuously along the top side of form standard where
typically glue is otherwise applied to further fasten flex
circuitry to form standard 34. The intermetallic bonding described
here may be employed alone or with other methods such as the
contact compression techniques described herein to create instances
of module 10 that present a low profile.
[0038] In a preferred embodiment, flex circuits 30 and 32 are
multi-layer flexible circuit structures that have at least two
conductive layers. Other embodiments may, however, employ flex
circuitry, either as one circuit or two flex circuits to connect a
pair of CSPs, that have only a single conductive layer and may
exhibit the variety of simple construction parameters that are
known to those of skill in the art with such features as covercoats
on one, both or neither side.
[0039] Preferably, the conductive layers are metal such as alloy
110 and as those of skill will know, often have conductive areas
plated with gold. The use of plural conductive layers provides
advantages and the creation of a distributed capacitance across
module 10 intended to reduce noise or bounce effects that can,
particularly at higher frequencies, degrade signal integrity, as
those of skill in the art will recognize. Module 10 of FIG. 1 has
plural module contacts 38. In embodiments where module 10 includes
more than two IC's, there may be found connections between flex
circuits which are typically balls but may be low profile contacts
constructed with pads and/or rings that are connected with solder
paste applications to appropriate connections. Appropriate fills
can provide added structural stability and coplanarity where
desired and, depending upon the fill, can improve thermal
performance.
[0040] Although the present invention has been described in detail,
it will be apparent to those skilled in the art that the invention
may be embodied in a variety of specific forms and that various
changes, substitutions and alterations can be made without
departing from the spirit and scope of the invention. The described
embodiments are only illustrative and not restrictive and the scope
of the invention is, therefore, indicated by the following
claims.
* * * * *