U.S. patent application number 10/851211 was filed with the patent office on 2005-07-14 for wiring structure forming method and semiconductor device.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Sakai, Hisaya, Shimizu, Noriyoshi.
Application Number | 20050151263 10/851211 |
Document ID | / |
Family ID | 34737153 |
Filed Date | 2005-07-14 |
United States Patent
Application |
20050151263 |
Kind Code |
A1 |
Sakai, Hisaya ; et
al. |
July 14, 2005 |
Wiring structure forming method and semiconductor device
Abstract
After a via hole to connect a lower wiring and an upper wiring
not shown is formed in an insulating film using an etching stopper
film and a hard mask, a base film made from tantalum is formed on
the insulating film so as to cover an inner wall of the via hole by
a one-step low-power bias sputtering method of the present
invention. Thus, the base film with a thin and uniform film
thickness covering a region from an inner wall surface of the via
hole to the insulating film is obtained.
Inventors: |
Sakai, Hisaya; (Kawasaki,
JP) ; Shimizu, Noriyoshi; (Kawasaki, JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW
SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
34737153 |
Appl. No.: |
10/851211 |
Filed: |
May 24, 2004 |
Current U.S.
Class: |
257/762 ;
257/E21.169; 257/E21.583; 438/637 |
Current CPC
Class: |
H01L 21/76865 20130101;
H01L 21/7684 20130101; H01L 21/2855 20130101; H01L 21/76843
20130101; H01L 21/76873 20130101 |
Class at
Publication: |
257/762 ;
438/637 |
International
Class: |
H01L 021/331 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 8, 2004 |
JP |
2004-003383 |
Claims
What is claimed is:
1. A wiring structure forming method, comprising the steps of:
forming an opening in an insulating film over a substrate; forming
a base film over the insulating film in such a manner that the base
film covers an inner wall surface of the opening by a sputtering
method; removing the base film over the insulating film other than
that in the opening in such a manner that the base film remains
only over the inner wall surface of the opening; and embedding a
conductive material in the opening with the base film therebetween,
wherein the base film is formed in such a manner that a film
thickness thereof in a portion other than the opening over the
insulating film is equal to or less than {fraction (1/20)} of a
diameter of the opening.
2. The wiring structure forming method according to claim 1,
wherein the base film is formed in such a manner that a film
thickness thereof in a portion other than the opening over the
insulating film is equal to or less than {fraction (1/30)} of a
diameter of the opening.
3. The wiring structure forming method according to claim 1,
wherein the base film is formed in such a manner that a film
thickness thereof over a bottom surface of the inner wall surface
of the opening is not less than 20% nor more than 100% of a film
thickness in a portion other than the opening over the insulating
film.
4. A wiring structure forming method, comprising the steps of:
forming an opening in an insulating film over a substrate; forming
a base film in such a manner that the base film covers only an
inner wall surface of the opening and is not deposited over the
insulating film other than that in the opening by a sputtering
method; and embedding a conductive material in the opening with the
base film therebetween.
5. The wiring structure forming method according to claim 1,
wherein the base film is formed by the sputtering method under a
condition of 1<Vd/Ve<2 where Vd/Ve is a ratio of a deposition
rate (Vd) of a material for the base film to an etching rate (Ve)
thereof.
6. The wiring structure forming method according to claim 1,
wherein the base film is formed by plural sputtering steps
comprising: a first step under a condition of Vd/Ve>1; and a
second step under a condition of Vd/Ve<1 where Vd/Ve is a ratio
of a deposition rate (Vd) of a material for the base film to an
etching rate (Ve) thereof.
7. The wiring structure forming method according to claim 5,
wherein the base film is formed so as to cover only the inner wall
surface of the opening and not to be deposited over the insulating
film other than that in the opening.
8. The wiring structure forming method according to claim 1,
wherein when the base film is formed, a bias voltage is applied to
the substrate.
9. The wiring structure forming method according to claim 8,
wherein the base film is formed under a condition that a target
power is not less than 0.1 kW nor more than 5.0 kW and a bias
voltage is not less than 100 W nor more than 450 W.
10. The wiring structure forming method according to claim 1,
wherein the base film is formed under a condition that a pressure
of an atmosphere of a sputtering ion species is not less than
1.times.10.sup.-2 Pa nor more than 1.times.10.sup.-1 Pa.
11. The wiring structure forming method according to claim 1,
wherein the conductive material is copper or a conductive substance
containing copper, and the opening includes at least a connection
hole.
12. The wiring structure forming method according to claim 1,
wherein a material for the base film is at least one type selected
from the group consisting of tantalum, titanium, tungsten,
zirconium, and vanadium or a nitride containing the at least one
type.
13. A semiconductor device, comprising: a semiconductor substrate;
an insulating film which is provided over said semiconductor
substrate and in which an opening is formed; a base film which
covers only an inner wall surface of the opening; and a conductive
material which is embedded in the opening with said base film
therebetween, wherein said base film is a sputtering film covering
the inner wall surface at a uniform film thickness and made from a
uniform material.
14. The semiconductor device according to claim 13, wherein said
conductive material is copper or a conductive substance containing
copper, and the opening includes at least a connection hole.
15. The semiconductor device according to claim 13, wherein a
material for said base film is at least one type selected from the
group consisting of tantalum, titanium, tungsten, zirconium, and
vanadium or a nitride containing the at least one type.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2004-003383, filed on Jan. 8, 2004, the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a wiring structure forming
method in which a conductive material is embedded in an opening
formed in an insulating film above a substrate, and a semiconductor
device, and particularly it is technology suitable for application
to a so-called damascene method in which Cu wiring is formed with
an opening as a minute wiring trench or connection hole and with Cu
(alloy) as a conductive material.
[0004] 2. Description of the Related Art
[0005] With high integration of a semiconductor element and a
reduction in chip size, finer wiring and multilayered wiring are
acceleratingly promoted. In a logic device having such a multilayer
wiring structure, wiring delay is becoming one of factors governing
device signal delay. The device signal delay is proportional to the
product of wiring resistance and wiring capacity, and hence, to
improve wiring delay, reductions in wiring resistance and wiring
capacity are important.
[0006] To reduce the wiring resistance, the formation of wiring
with Cu which is low-resistance metal as a material is studied.
Since it is very difficult to form wiring by patterning Cu, a
so-called damascene method in which an opening which becomes a
wiring trench or a connection hole (via hole) is formed in an
insulating film and filled with Cu to form the wiring is worked
out.
[0007] When Cu wiring is formed by the damascene method, a step of
forming a base film which covers an inner wall of the opening
before Cu is deposited is included, mainly in order to prevent Cu
from diffusing into the insulating film. Refractory metal such as
Ta or W used as a material for the base film is generally high
resistant. In recent years when finer wiring is promoted, it is
indispensable to reduce the resistance value of the base film from
a matter of wiring resistance. In particular, in the case of an
ultra-fine wiring layer containing a via hole with a diameter of
0.1 .mu.m and a wiring with a width of 0.1 .mu.m, it is necessary
to thin the base film as much as possible in order to reduce wiring
resistance and contact resistance, and hence the technology for
forming a base film thin and uniformly on an inner wall of a wiring
trench or a via hole is desired.
[0008] A CVD method is first thought of as a method for forming
such a base film. As far as the formation of the thin and uniform
base film is concerned, it is thought that the use of the CVD
method is advantageous, but the CVD method has a big problem in
compatibility with and adhesiveness to a low dielectric constant
insulating material which is expected as a material for the
insulating film in which the opening is formed, and the application
of this method is difficult in the present circumstances. A
sputtering method is superior in the aforementioned compatibility
and adhesiveness to the CVD method, whereby the use of the
sputtering method for the formation of the base film is considered
to be suitable.
[0009] At present, as sputtering technology used for forming the
base film, there are a long throw sputtering method in which the
distance between a substrate and a target is set longer than
normal, a bias sputtering method in which a film is formed while a
bias voltage is applied to a substrate, a multistep sputtering
method in which two or more steps of sputtering as a combination of
sputter deposition and sputter etching are performed, and so
on.
[0010] (Patent Document 1)
[0011] Japanese Patent Application No. 2002-318674
[0012] However, under the present circumstances, even if the
aforementioned various methods are used, the base film cannot be
formed thin and uniformly on an inner wall surface, that is, from a
side wall surface to a bottom surface, of the wiring trench or the
via hole.
[0013] Specifically, part of a process of forming wiring containing
a base film is shown in FIG. 7A and FIG. 7B, and FIG. 8. Here, for
example, when a via hole 102 to connect a lower wiring 101 and an
upper wiring not shown is formed in an interlayer insulating film
103 using an etching stopper film 104 and a hard mask 105, a Ta
base film 106 is formed on the interlayer insulating film 103 so as
to cover an inner wall of the via hole 102 by a sputtering method,
and thereafter Cu 107 is deposited so as to be embedded in the via
hole 102 by a plating method. Here, FIG. 7A shows a case where a
long throw sputtering method is used as the sputtering method when
the base film 106 is formed, FIG. 7B shows a case where a bias
sputtering method is used, and FIG. 8 shows a case where a
multistep sputtering method is used.
[0014] In the case of the long throw sputtering method (which is
carried out without applying a substrate bias under the condition
that the target power is between 10 kW and 20 kW and the pressure
is 4.times.10.sup.-2 Pa in the example in FIG. 7A), Ta is thickly
deposited on a bottom surface of the via hole 102 and a portion
(field portion) other than the via hole 102 of the insulating film
103, whereas scarce Ta is deposited on a sidewall surface of the
via hole 102. As a result, due to insufficient coverage of the
sidewall surface, poor embedding, for example, a void 108 occurs in
copper 107 formed by plating.
[0015] In the case of the bias sputtering method (which is carried
out under the condition that the target power is between 10 kW and
20 kW, the pressure is 4.times.10.sup.-2 Pa, and the substrate bias
is between 200 W and 500 W in the example in FIG. 7B), excessive Ta
is deposited not only on the bottom surface of the via hole 102 but
also in the vicinity of a rim portion of the via hole 102 (a
so-called overhang is formed), which causes poor embedding, for
example, a void 109 in the copper 107.
[0016] In the case of the multistep sputtering method (in which in
a first step, long throw sputtering is carried out under the
condition that the target power is between 10 kW and 20 kW, the
pressure is 4.times.10.sup.-2 Pa, and the substrate bias is between
0 W and 300 W, and in a second step, bias sputtering etching is
carried out under the condition that the target power is between
0.2 kW and 5 kW, the pressure is between 3.times.10.sup.-1 Pa and
7.times.10.sup.-1 Pa, and the substrate bias is between 200 W and
500 W in the example in FIG. 8). Ta deposited on the bottom surface
of the via hole 102 in the first step adheres again to a side
surface of the via hole 102 to make up a shortage of Ta on the side
surface, but on the other hand, if an etching factor is strong, Ta
becomes insufficient on the bottom surface of the via hole 102.
When positional displacement occurs between the lower wiring 101
and the via hole 102 due to this, for example, Cu deposited by
plating diffuses into the insulating film.
[0017] Even if the various sputtering methods are used as described
above, it is very difficult to form the basic film with a uniform
film thickness in the opening. There is also a disadvantage that to
control the film forming state of the base film causes complication
of a film forming process thereof, resulting in an increase in the
time required for the process. This causes an increase in target
power consumption, an increase in particles produced at the time of
film formation, and a deterioration in throughput, which leads to a
considerably thick deposition on the field portion while the
necessary amount of film is formed in the opening. The base film
deposited on the field portion needs to be removed by polishing in
a chemical mechanical polishing (CMP) process, but the base film
too thick leads to a deterioration in throughput in the CMP process
and furthermore exerts a bad influence on the capability of the
entire manufacturing line. Moreover, CMP of the base film has
chemical polishing as a strong factor, and hence flaws such as
scratches easily occur, which may contribute to a reduction in the
yield of wiring formation.
SUMMARY OF THE INVENTION
[0018] The present invention is made in view of the aforementioned
problems, and its object is to provide a wiring structure forming
method which can form a base film thin and uniformly on an inner
wall surface, that is, from a sidewall surface to a bottom surface,
of an opening without causing any disadvantage in terms of wiring
formation by relatively simple steps to realize a highly reliable
ultra-fine wiring structure, and a semiconductor device.
[0019] A wiring structure forming method of the present invention
comprises the steps of: forming an opening in an insulating film
over a substrate; forming a base film over the insulating film by a
sputtering method in such a manner that the base film covers an
inner wall surface of the opening; removing the base film over the
insulating film other than that in the opening in such a manner
that the base film remains only over the inner wall surface of the
opening; and embedding a conductive material in the opening with
the base film therebetween, and the base film is formed in such a
manner that a film thickness thereof in a portion other than the
opening over the insulating film is equal to or less than {fraction
(1/20)} of a diameter of the opening.
[0020] A wiring structure forming method of the present invention
comprises the steps of: forming an opening in an insulating film
over a substrate; forming a base film by a sputtering method in
such a manner that the base film covers only an inner wall surface
of the opening and is not deposited over the insulating film other
than that in the opening; and embedding a conductive material in
the opening with the base film therebetween.
[0021] A wiring structure forming method of the present invention
comprises the steps of: forming an opening in an insulating film
over a substrate; and embedding a conductive material in the
opening with a base film which covers an inner wall surface of the
opening therebetween, and the base film is formed by a sputtering
method under a condition of
1<Vd/Ve<2
[0022] where Vd/Ve is a ratio of a deposition rate (Vd) of a
material for the base film to an etching rate (Ve) thereof.
[0023] A wiring structure forming method of the present invention
comprises the steps of: forming an opening in an insulating film
over a substrate; and embedding a conductive material in the
opening with a base film which covers an inner wall surface of the
opening therebetween, and the base film is formed by plural
sputtering steps comprising:
[0024] a first step under a condition of Vd/Ve>1; and
[0025] a second step under a condition of Vd/Ve<1 where Vd/Ve is
a ratio of a deposition rate (Vd) of a material for the base film
to an etching rate (Ve) thereof.
[0026] A semiconductor device of the present invention comprises: a
semiconductor substrate; an insulating film which is provided over
the semiconductor substrate and in which an opening is formed; a
base film which covers only an inner wall surface of the opening;
and a conductive material which is embedded in the opening with the
base film therebetween, and the base film is a sputtering film
covering the inner wall surface at a uniform film thickness and
made from a uniform material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a characteristic chart showing the quantitative
relation between film formation time and a ratio (Vd/Ve) of a
deposition rate (Vd) of sputtering particles and an etching rate
(Ve) thereof in a bias sputtering process;
[0028] FIG. 2 is a characteristic chart showing the results of
investigations of the relation between film formation time and film
thickness inside and outside a via hole with a diameter of 0.1
.mu.m in the bias sputtering process;
[0029] FIG. 3A and FIG. 3B are schematic sectional views each
showing a state in which a base film is formed by a sputtering
method of the present invention;
[0030] FIG. 4 is a characteristic chart showing film thickness in a
field portion of a base film when the base film with a uniform film
thickness is formed by a two-step bias sputtering method;
[0031] FIG. 5A and FIG. 5B are schematic sectional views showing a
wiring forming method according to an embodiment in the order of
steps;
[0032] FIG. 6A to FIG. 6C are schematic sectional views, subsequent
to FIG. 5B, showing the wiring forming method according to the
embodiment in the order of steps;
[0033] FIG. 7A and FIG. 7B are schematic sectional views each
showing part of a process of forming wiring including a base film
as a prior art; and
[0034] FIG. 8 is a schematic sectional view showing part of a
process of forming wiring including a base film as a prior art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] Basic Gist of the Present Invention
[0036] As described above, various conventional sputtering methods
have a tendency to aim at realization of a base film with a thin
and uniform film thickness by adding a film forming condition to a
sputtering process or increasing the process and making the process
more elaborate, for example, the application of a bias to a
substrate or sputtering divided into plural steps. However, in the
present circumstances, this inevitably causes the complication of
the process, and moreover uniformity of the base film over the
entire inner wall surface of an opening is not obtained. The
present inventor changes his point of view from the aforementioned
tendency to addition of the condition to the sputtering process to
a microscopic state of sputtering, that is, a microscopic film
forming state woven by a balance between deposition of sputtering
particles and etching thereof in the sputtering process, quantifies
this microscopic state, and pays attention to the correlation
between this microscopic state and the film forming state of the
entire base film.
[0037] The present inventor thinks that if, in the sputtering
process, the sputtering condition is set so that the ratio of the
deposition rate of sputtering particles to the etching rate thereof
is within a certain range throughout the sputtering process, the
thin and uniform base film can be formed over the entire inner
surface of the opening even by one-step sputtering, and
investigates the relation between film formation time and this
ratio with a bias sputtering method as an example.
[0038] (One-Step Bias Sputtering)
[0039] FIG. 1 is a characteristic chart showing the quantitative
relation between film formation time and a ratio (Vd/Ve) of a
deposition rate (Vd) of sputtering particles and an etching rate
(Ve) thereof in a bias sputtering process. Here, a general bias
sputtering method is carried out under the condition that the
target power is 10 kW, the pressure is 4.times.10.sup.-2 Pa, and
the substrate bias is 200 W, and bias sputtering etching is carried
out under the condition that the target power is 0.5 kW, the
pressure is between 3.times.10.sup.-2 Pa and 7.times.10.sup.-1 Pa,
and the substrate bias is 200 W.
[0040] In a general bias sputtering method, the film is usually
formed in the range of a Vd/Ve ratio of 2.5 or more to maintain a
certain degree of film forming rate. In this range of Vd/Ve, the
proportion of deposition is higher than that of etching, whereby
the resputtering effect is small. In this case, to secure the
coverage of a sidewall portion of the inner wall of the opening, it
is necessary to increase the film formation time and substrate
bias, but this causes adverse effects such as an increase in
overhang, an increase in particles when the film is formed, and
difficulty in reducing the thickness of the film.
[0041] In bias sputtering etching in a multistep sputtering method,
to strengthen an etching factor, the range of a Vd/Ve ratio less
than 1 (for example, approximately 0.75) is often selected. In this
range, the contribution of Ta ions as a material for the film is
small, and the etching effect by Ar ions is large, whereby film
formation progresses in a state in which a film material is hardly
deposited. This etching effect tends to increase as the pressure at
the time of film formation (pressure of an Ar atmosphere) becomes
higher, and film peeling in a rim portion of the opening and film
peeling in a bottom portion of the opening increase, whereby there
arises the high possibility of causing failures such as Cu
diffusion into an insulating film caused by a wiring short-circuit
and positional displacement of the opening, respectively.
[0042] As a result of forming the base film by the one-step bias
sputtering within the range of a Vd/Ve ratio not less than 1 nor
more than 2.5, the present inventor finds that if the ratio is
controlled to be 1<Vd/Ve<2 throughout the formation of the
film, the thin and uniform base film over the entire inner wall
surface of the opening is obtained. Namely, in this case, the
supply of Ta ions and resputtering by Ar ions are balanced, local
etching in the rim portion and the bottom portion of the opening is
prevented, and a certain amount of Ta is secured even in the bottom
portion. Moreover, reinforcement of the film thickness on the
sidewall of the opening by the resputtering effect moderately
progresses, and as a result, the thin and uniform base film over
the entire inner wall surface of the opening is obtained.
[0043] Here, to obtain 1<Vd/Ve<2 throughout the formation of
the film, it is suitable to carry out sputtering under the
condition that the target power is a relatively low power between
0.1 kW and 5.0 kW, the pressure of an atmosphere of sputtering ion
species (Ar in this case) is between 1.times.10.sup.-2 Pa and
1.times.10.sup.-1 Pa, and the substrate bias is between 100 W and
450 W, and in this example, the target power is set at 5 kW, the
pressure is set at 6.times.10.sup.-2 Pa, and the substrate bias is
set at 300 W. As described above, in this example, a desired base
film shape is attained by a smaller sputtering amount than in prior
arts by low power in the one-step bias sputtering, and as a result
effects such as reductions in wiring resistance and contact
resistance, a reduction in target power consumption, an increase in
throughput, and a reduction in particles at the time of film
formation are produced.
[0044] Moreover, the present inventor compares a film thickness on
the inner wall surface of the opening of the base film and a film
thickness on the field portion under the sputtering condition which
satisfies 1<Vd/Ve<2 throughout film formation.
[0045] FIG. 2 is a characteristic chart showing the results of
investigations of the relation between film formation time and film
thickness inside and outside a via hole with a diameter of 0.1
.mu.m in the bias sputtering process. Here, the general bias
sputtering method is carried out under the condition that the
target power is 10 kW, the pressure is 4.times.10.sup.-2 Pa, and
the substrate bias is 200 W, and sputtering of the present
invention is carried out under the condition that the target power
is 5 kW, the pressure is 6.times.10.sup.-2 Pa, and the substrate
bias is 300 W.
[0046] It turns out that in the general bias sputtering method, the
film thickness of the base film on the field portion is larger than
that on the inner wall surface of the via hole, whereas in this
example, the film thickness of the base film on the inner wall
surface of the via hole is formed larger than that on the field
portion, an increase in film thickness on the field portion with
the progress of film formation is slight, and that the film
thickness on the field portion is kept below 5 nm. In other words,
this means that the film thickness of the base film on the field
portion is equal to or less than {fraction (1/20)}, more preferably
{fraction (1/30)} of the diameter (0.1 .mu.m in this case) of the
via hole. Moreover, it means that the film thickness of the base
film on the field portion is between 20% and 100% of the film
thickness on the inner wall of the via hole, and approximately 20%
in this case. Further, it is confirmed that the state of embedding
of Cu in the via hole in this film formation range is
satisfactory.
[0047] Furthermore, the present inventor thinks out that according
to the aforementioned experimental results, under a predetermined
sputtering condition satisfying 1<Vd/Ve<2, the thin and
uniform base film is formed only on the entire inner wall surface
of the opening, and on a portion on the insulating film other than
the opening, that is, on the field portion, the supply of Ta ions
and resputtering by Ar ions are nearly equal, so that a state in
which the deposition amount of Ta ions becomes zero is obtained. In
this case, only Cu on the field portion is required to be removed
by polishing in a CMP process subsequent to Cu deposition, which
can reduce a polishing process of the base film.
[0048] Specifically, a state in which the base film is formed by
the sputtering method of the present invention is shown in FIG. 3A
and FIG. 3B.
[0049] As shown in FIG. 3A, after a via hole 102 to connect a lower
wiring 101 and an upper wiring not shown is formed in an insulating
film 103 using an etching stopper film 104 and a hard mask 105, a
base film 111 made from Ta is formed on the insulating film 103 so
as to cover an inner wall of the via hole 102 by a one-step
low-power bias sputtering method of the present invention. Thus,
the base film 111 with a thin and uniform film thickness covering a
region from an inner wall surface of the via hole 102 to the
insulating film 103 is obtained. Thereafter, Cu 107 is deposited so
as to be embedded in the via hole 102 by a plating method. Any void
and the like do not occur in the via hole 102 and so on even if the
Cu 107 is embedded, leading to the realization of satisfactory Cu
deposition.
[0050] Moreover, as shown in FIG. 3B, by selecting the sputtering
condition within the range satisfying 1<Vd/Ve<2, it is
possible that the base film 111 with the thin and uniform thickness
is formed so as to cover only the inner wall of the via hole 102
without the film material being deposited on the field portion.
Here, in order that only the via hole 102 is filled with the Cu 107
after the Cu 107 is deposited so as to be embedded in the via hole
102, in the example in FIG. 3A, it is necessary to remove the Cu
107 and the base film 111 on the field portion in sequence by
polishing by the CMP method, but in the example in FIG. 3B, since
the base film 111 does not exist on the field portion, only the Cu
107 on the field portion is required to be removed by polishing by
the CMP method, whereby the CMP process of the base film 111 can be
reduced.
[0051] (Multistep Sputtering)
[0052] In the present invention, also by multistep sputtering in
addition to the aforementioned one-step bias sputtering, it is
possible that the base film with a thin and uniform thickness is
formed on the inner wall surface of the opening, and that the film
thickness on the field portion is formed to be equal to or less
than {fraction (1/20)} (more preferably equal to or less than
{fraction (1/30)}) of the diameter of the opening.
[0053] FIG. 4 is a characteristic chart showing the film thickness
on the field portion of the base film when the base film with a
uniform film thickness is formed by a two-step bias sputtering
method. Here, a second step is carried out under the condition that
the target power is 2.5 kW, the pressure is between
4.times.10.sup.-2 Pa and 8.times.10.sup.-2 Pa, and the substrate
bias is 300 W or under the condition that the target power is 0.5
kW, the pressure is between 4.times.10.sup.-2 Pa and
8.times.10.sup.-2 Pa, and the substrate bias is 200 W.
[0054] In this example, in a first step, the film with a film
thickness approximately between 5 nm and 10 nm is formed under the
sputtering condition of Vd/Ve>1, and in the second step,
sputtering etching is carried out under the sputtering condition of
Vd/Ve<1. Consequently, the base film with the thin and uniform
film thickness is formed on the inner wall surface of the via hole,
and the film thickness on the filed portion is kept below 5 nm, and
hence it turns out that an effect equal to that by the one-step
bias sputtering method of the present invention can be
obtained.
[0055] Specific Embodiment of the Present Invention
[0056] A specific embodiment in which the present invention is
applied to the formation of Cu wiring (and via connection) by a
damascene method will be explained below.
[0057] FIG. 5A and FIG. 5B and FIG. 6A to FIG. 6C are schematic
sectional views showing a wiring forming method according to this
embodiment in the order of steps.
[0058] First, as shown in FIG. 5A, after a semiconductor element
such as a MOS transistor is formed on a semiconductor substrate not
shown, a lower wiring 1 is formed to be connected to the
semiconductor element. Subsequently, an etching stopper film 2 with
a film thickness of a few tens of nm is formed on the lower wiring
1, for example, using a material such as SiO+SiC, and thereafter,
an interlayer insulating film 3 with a film thickness of a few
hundreds of nm is formed on the etching stopper film 2 using an
organic or inorganic insulating material by an SOG method or a CVD
method. Then, after a hard mask 4 having an opening is formed on
the interlayer insulating film 3, for example, by using a material
such as SiO+SiC, a via hole 5 with a diameter approximately between
0.1 .mu.m and 0.15 .mu.m and a depth approximately between 300 nm
and 700 nm is formed in the interlayer insulating film 3 by dry
etching with the hard mask 4. CF based gas, NH.sub.3 base gas, or
N.sub.2/H.sub.2 gas is used as etching gas. At this time, an
opening is also formed in the etching stopper film 2, and the
surface of the lower wiring 1 is exposed from a bottom surface of
the lower wiring 1.
[0059] Subsequently, as shown in FIG. 5B, one-step bias sputtering
is carried out under the sputtering condition which satisfies
1<Vd/Ve<2 and under which a film material is not deposited on
a field portion, and here the target power is between 0.2 kW and 5
kW, the pressure is 4.times.10.sup.-2 Pa, and the substrate bias is
between 150 W and 450 W. By performing sputtering with Ta as a
material under this condition, Ta is (hardly) deposited on the
interlayer insulating film 3 (field portion) other than that in the
via hole 5 but deposited only on an inner wall surface of the via
hole 5, and a base film 6 with a uniform film thickness of 5 nm or
less is formed. It is also possible here to use at least one type
of refractory metal selected from the group consisting of Ti, W,
Zr, and V or a nitride of these metals in place of Ta as a
sputtering material. Moreover, it is defined that a preliminary
step of this film forming step includes an electric discharge
starting step, an electric discharge stabilizing step, an electric
discharge completing step, and a substrate electricity removing
step. Incidentally, there is a possibility that the substrate
electricity removing step is not included.
[0060] Thereafter, as shown in FIG. 6A, a seed metal film 7 is
formed with Cu as a material on the interlayer insulating film 3 by
sputtering so as to cover the inner wall surface of the via hole 5
with the base film 6 between them. The seed metal film 7 with a
film thickness approximately between 40 nm and 150 nm is formed
under the sputtering condition that the target power is between 5
kW and 30 kW, the pressure is between 1.times.10.sup.-5 Pa and 10
Pa, and the substrate bias is between 200 W and 500 W. Here, it is
also possible to use a Cu alloy containing Al, Ti, Zr, Ni, Ag, Pd,
and so on in place of Cu as a material for the seed metal film
7.
[0061] Subsequently, as shown in FIG. 6B, Cu 8 is embedded in a
wiring trench 12 by the plating method with the seed metal film 7
as an electrode. On this occasion, the Cu 8 with a film thickness
approximately between 500 nm and 2000 nm is deposited at a current
density between 7 A/cm.sup.2 and 30 A/cm.sup.2 with a copper
sulfate bath.
[0062] Then, as shown in FIG. 6C, the Cu 8 is removed by polishing
by the CMP method with an organic acid slurry solution and, for
example, the hard mask 4 as a stopper, and a via-plug 9 which is
made by filling the via hole 5 with the Cu 8 with the base film 6
therebetween is formed. At this time, Ta of the base film 6 does
not exist on the field portion, whereby only polishing of the Cu 8
is needed.
[0063] Thereafter, a wiring structure is completed through the
formation of another interlayer insulating film not shown and an
upper wiring not shown which is connected to the via-plug 9.
[0064] Incidentally, also when the lower wiring 1 is formed, it is
also possible to form a base film which thin and uniformly covers
an inner wall of a wiring trench formed in an insulating film by
sputtering technology of the present invention and embed Cu in this
wiring trench with the base film therebetween by a damascene
method.
[0065] Moreover, in this embodiment, the case where the sputtering
technology of the present invention is used for the formation of
the base film of the via-plug in the damascene method is shown as
an example, but the present invention is not limited to this case,
and, for example, it is also possible that the present invention is
applied to a dual damascene method, and that a base film with a
thin and uniform film thickness is formed by the aforementioned
sputtering method so as to cover the inner wall surface from a via
hole to a wiring trench and at the same time Cu is embedded in the
via hole and the wiring trench to thereby form a wiring
structure.
[0066] As explained above, according to this embodiment, it becomes
possible to form a base film thin and uniformly in an opening, in
this case, on an inner wall surface, that is, from a sidewall
surface to a bottom surface, of the via hole 5 without causing any
disadvantage in terms of wiring formation by relatively simple
steps, and improvements in wiring resistance and contact
resistance, lowering of load and a reduction in the CMP process, a
reduction in target power consumption, an increase in throughput, a
reduction in particles at the time of film formation, an increase
in wiring performance, and an increase in manufacturing line
capability are attained to thereby realize a highly reliable
ultra-fine wiring structure.
[0067] According to the present invention, it becomes possible to
form a base film thin and uniformly on an inner wall surface, that
is, from a sidewall surface to a bottom surface, of an opening
without causing any disadvantage in terms of wiring formation by
relatively simple steps, and improvements in wiring resistance and
contact resistance, lowering of load and a reduction in the CMP
process, a reduction in target power consumption, an increase in
throughput, a reduction in particles at the time of film formation,
an increase in wiring performance, and an increase in manufacturing
line capability are attained to thereby realize a highly reliable
ultra-fine wiring structure.
[0068] The present embodiments are to be considered in all respects
as illustrative and no restrictive, and all changes which come
within the meaning and range of equivalency of the claims are
therefore intended to be embraced therein. The invention may be
embodied in other specific forms without departing from the spirit
or essential characteristics thereof.
* * * * *