U.S. patent application number 10/970688 was filed with the patent office on 2005-06-30 for dynamic schottky barrier mosfet device and method of manufacture.
Invention is credited to Larson, John M., Snyder, John P..
Application Number | 20050139860 10/970688 |
Document ID | / |
Family ID | 34468044 |
Filed Date | 2005-06-30 |
United States Patent
Application |
20050139860 |
Kind Code |
A1 |
Snyder, John P. ; et
al. |
June 30, 2005 |
Dynamic schottky barrier MOSFET device and method of
manufacture
Abstract
A device for regulating a flow of electric current and its
manufacturing method are provided. The device includes
metal-insulator-semiconductor source-drain contacts forming
Schottky barrier or Schottky-like junctions to the semiconductor
substrate. The device includes an interfacial layer between the
semiconductor substrate and a metal source and/or drain electrode,
thereby dynamically adjusting a Schottky barrier height by applying
different bias conditions. The dynamic Schottky barrier modulation
provides increased electric current for low drain bias conditions,
reducing the sub-linear turn-on characteristic of Schottky barrier
MOSFET devices and improving device performance.
Inventors: |
Snyder, John P.; (Edina,
MN) ; Larson, John M.; (Northfield, MN) |
Correspondence
Address: |
Min (Amy) S. Xu, Esq.
DORSEY & WHITNEY LLP
Intellectual Property Department
50 South Sixth Street, Suite 1500
Minneapolis
MN
55402-1498
US
|
Family ID: |
34468044 |
Appl. No.: |
10/970688 |
Filed: |
October 21, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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60513410 |
Oct 22, 2003 |
|
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|
60514041 |
Oct 24, 2003 |
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Current U.S.
Class: |
257/155 ;
257/E21.425; 257/E21.431; 257/E29.021; 257/E29.042; 257/E29.271;
438/534 |
Current CPC
Class: |
H01L 29/7839 20130101;
H01L 29/6656 20130101; H01L 29/66643 20130101; H01L 29/0653
20130101; H01L 29/0895 20130101; H01L 29/66636 20130101 |
Class at
Publication: |
257/155 ;
438/534 |
International
Class: |
H01L 029/74; H01L
021/425 |
Claims
We claim:
1. A MOSFET device comprising: a gate electrode on a semiconductor
substrate; a source electrode and a drain electrode on the
semiconductor substrate, wherein at least one of the source
electrode and the drain electrode is metal; and an interfacial
layer between the substrate and at least one of the metal source
and drain electrodes.
2. The device of claim 1 wherein the interfacial layer is disposed
in areas at least proximal to the gate electrode.
3. The device of claim 1 wherein an entire Schottky or
Schottky-like junction between the substrate and at least one of
the metal source and drain electrodes incorporates the interfacial
layer.
4. The device of claim 1 wherein at least in areas proximal to the
gate electrode, a Schottky or Schottky-like junction between the
substrate and at least one of the metal source and drain electrodes
incorporates the interfacial layer.
5. The device of claim 1 wherein at least one of the metal source
and drain electrodes having the interfacial layer form a Schottky
or Schottky-like junction to the substrate.
6. The device of claim 1 wherein the interfacial layer comprises an
insulator.
7. A method of manufacturing a MOSFET device for regulating a flow
of electrical current, the method comprising: providing a gate
electrode on a semiconductor substrate; exposing the semiconductor
substrate in an area proximal to the gate electrode; etching the
semiconductor substrate on the exposed area using an at least
partially isotropic etch; depositing a thin film of metal in the
etched area of the semiconductor substrate; and reacting the metal
with the semiconductor substrate such that at least one of a
Schottky or Schottky-like source electrode and drain electrode is
formed.
8. The method of claim 7 wherein the etching step is performed
using an etch having a lateral etch rate of from approximately
one-tenth to ten times of a vertical etch rate.
9. The method of claim 7 wherein the etching step is performed
using an etch having approximately the same lateral and vertical
etch rates.
10. The method of claim 7 wherein the gate electrode is provided by
the steps comprising: providing a thin insulating layer on the
semiconductor substrate; depositing a thin conducting film on the
thin insulating layer; patterning and etching the thin conducting
film to form the gate electrode; and forming at least one thin
insulating layer on at least one sidewall of the gate
electrode.
11. The method of claim 7 further comprising removing unreacted
metal from the MOSFET device after forming the Schottky or
Schottky-like source and drain electrodes.
12. The method of claim 7 wherein the reacting step is performed by
thermal annealing.
13. The method of claim 7 wherein the source electrode and the
drain electrode are formed from a member of the group consisting
of: Platinum Silicide, Palladium Silicide and Iridium Silicide, and
channel dopants in the semiconductor substrate are selected from
the group consisting of: Arsenic, Phosphorous, and Antimony.
14. The method of claim 7 wherein the source electrode and the
drain electrode are formed from a member of the group consisting of
the rare-earth suicides, and channel dopants in the semiconductor
substrate are selected from the group consisting of: Boron, Indium,
and Gallium.
15. The method of claim 7 wherein Schottky or Schottky-like contact
is formed at least in areas adjacent to a channel between the
source and drain electrodes.
16. The method of claim 7 wherein an entire surface of the at least
one of the source electrode and the drain electrode forms a
Schottky or Schottky-like contact with the semiconductor
substrate.
17. The method of claim 7 wherein before the step of providing the
gate electrode, dopants are introduced into the semiconductor
substrate.
18. The method of claim 7 wherein the semiconductor substrate has a
channel dopant concentration that varies significantly in a
vertical direction and is generally constant in a lateral
direction.
19. A method of manufacturing a device for regulating a flow of
electrical current, the method comprising: exposing a semiconductor
substrate in an area proximal to a gate electrode; etching the
semiconductor substrate on the exposed area using an at least
partially isotropic etch; and depositing and thermally annealing a
thin film of metal with the semiconductor substrate such that a
Schottky or Schottky-like source electrode and drain electrode is
formed.
20. The method of claim 19 wherein the etching step is performed
using an etch having a lateral etch rate of from approximately
one-tenth to ten times of a vertical etch rate.
21. The method of claim 19 wherein the etching step is performed
using an etch having approximately the same lateral and vertical
etch rates.
22. The method of claim 19 wherein the etching step is performed
using an etch having lateral and vertical etch rates such that a
channel width of the device is reduced by between approximately 1
and 50 percent.
23. The method of claim 19 wherein the semiconductor substrate is
heated during the depositing step, to encourage surface diffusion
of metal atoms along a surface of the semiconductor substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims the benefit of and priority to U.S.
provisional patent application No. 60/513,410, filed Oct. 22, 2003.
This application also claims the benefit of and priority to U.S.
provisional patent application No. 60/514,041, filed Oct. 24, 2003.
Each of the above provisional patent applications is incorporated
by reference herein in their entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to devices for regulating the
flow of electric current, and has specific application to the
fabrication of these devices in the context of an integrated
circuit ("IC"). More particularly, it relates to a transistor for
regulating the flow of electric current having metal source and/or
drains forming Schottky-barrier or Schottky-like contacts to a
channel region.
BACKGROUND OF THE INVENTION
[0003] One type of transistor known in the art is a
Schottky-barrier metal oxide semiconductor field effect transistor
(Schottky-barrier MOSFET or SB-MOS). As shown in FIG. 1, the SB-MOS
device 100 comprises a semiconductor substrate 110 in which a
source electrode 120 and a drain electrode 125 electrode are
formed, separated by a channel region 140 having channel dopants.
The channel region 140 is the current-carrying region of the
substrate 110. For purposes of the present invention, the channel
region 140 in the semiconductor substrate extends vertically below
the gate insulator 150 to a boundary approximately aligned with the
bottom edge of the source 120 and bottom edge of the drain 125
electrodes. The channel dopant concentration profile typically has
a maximum concentration 115, which is below the source 120 and
drain 125 electrodes, and thus outside of the channel region 140.
For the purpose of the present invention, channel dopants are not
constrained to be provided exclusively within the channel region
140, but may be found in regions substantially outside of the
channel region 140.
[0004] For a SB-MOS device at least one of the source 120 or the
drain 125 contacts is composed partially or fully of a metal
silicide. Because at least one of the source 120 or the drain 125
contacts is composed in part of a metal, they form Schottky or
Schottky-like contacts 130,135 with the substrate 110 and the
channel region 140. A Schottky contact is defined as a contact
formed by the intimate contact between a metal and a semiconductor,
and a Schottky-like contact is defined as a contact formed by the
close proximity of a semiconductor and a metal. The Schottky
contacts or Schottky-like contacts or junctions 130, 135 may be
provided by forming the source 120 or the drain 125 from a metal
silicide. The channel length is defined as the distance from the
source 120 contact to the drain 125 contact, laterally across the
channel region 140.
[0005] The Schottky or Schottky-like contacts 130, 135 are located
in an area adjacent to the channel region 140 formed between the
source 120 and drain 125. An insulating layer 150 is located on top
of the channel region 140. The insulating layer 150 is composed of
a material such as silicon dioxide. The channel region 140 extends
vertically from the insulating layer 150 to the bottom of the
source 120 and drain 125 electrodes. A gate electrode 160 is
positioned on top of the insulating layer 150, and a thin
insulating layer 170 surrounds the gate electrode 160. The thin
insulating layer 170 is also known as the spacer. The gate
electrode 160 may be doped poly silicon. The source 120 and drain
125 electrodes may extend laterally below the spacer 170 and gate
electrode 160. A field oxide 190 electrically isolates devices from
one another. An exemplary Schottky-barrier device is disclosed in
Spinnaker's U.S. Pat. No. 6,303,479.
[0006] Another type of MOSFET transistor known in the art is a
conventional impurity-doped source-drain transistor or conventional
MOSFET. This device is similar to the SB-MOS device shown in FIG.
1. The key difference is that the metal source-drain regions
120,125 of the SB-MOS are replaced with impurity doping in the
semiconductor substrate for the conventional MOSFET.
[0007] One of the important performance characteristics for a
MOSFET device is the drive current (I.sub.d), which is the
electrical current from source to drain when the applied source
voltage (V.sub.s) is grounded, and the gate (V.sub.g) and drain
(V.sub.d) are biased at the supply voltage (V.sub.dd). Drive
current is one of the important parameters that determines circuit
performance. For example, the switching speed of a transistor
scales as I.sub.d, so that higher drive current devices switch
faster, thereby providing higher performance integrated
circuits.
[0008] FIG. 2 shows the relationship of drive current (I.sub.d) 232
for varying gate voltage (V.sub.g) and drain voltage (V.sub.d) 231
for a SB-MOS and a conventional MOSFET. One characteristic of
SB-MOS device I.sub.d-V.sub.d curves is the sub-linear shape for
low V.sub.d 231, as shown by the solid lines 210,215,220,225,230.
Each of the I.sub.d-V.sub.d curves 210,215,220,225,230 has a
different V.sub.g. The I.sub.d-V.sub.d profile at low V.sub.d is
known as the turn-on characteristic. Conventional MOSFET transistor
technologies have a linear I.sub.d-V.sub.d turn-on characteristic
at low V.sub.d, as shown by the dashed lines 235,240,245,250,255 in
FIG. 2. Each of the I.sub.d-V.sub.d curves 235,240,245,250,255 has
a different V.sub.g. The sub-linear I.sub.d-V.sub.d turn-on
characteristic of the SB-MOS device increases as the channel length
decreases and can potentially reduce transistor performance,
possibly reducing the effective switching speed of the device for
example. Sub-linear turn-on has been observed in the literature and
referenced as a reason why SB-MOS devices will not be of
practicable use in integrated circuits (B. Winstead et al., IEEE
Transactions on Electron Devices, 2000, pp. 1241-1246). Industry
literature consistently teaches that the Schottky barrier height
.phi..sub.b should be reduced or made less than zero in order to
minimize the sub-linear turn-on phenomenon and thus to make SB-MOS
device performance competitive with alternative MOSFET device
technologies (J. Kedzierski et al., IEDM, 2000, pp. 57-60; E.
Dubois et al., Solid State Electronics, 2002, pp. 997-1004; J. Guo
et al., IEEE Transaction on Electron Devices, 2002, pp. 1897-1902;
K. Ikeda et al., IEEE Electronic Device Letters, 2002, pp. 670-672;
M. Tao et al., Applied Physics Letters, 2003, pp. 2593-2595).
[0009] There is a need in the industry for teaching a SB-MOS device
and method of fabrication that provides a means for improving the
turn-on characteristic thereby providing improved performance.
BRIEF SUMMARY OF THE INVENTION
[0010] In one aspect, the present invention provides a method of
fabricating a Schottky barrier MOSFET (SB-MOS) device wherein at
least one of the source and drain contact regions is comprised of a
metal and wherein the SB-MOS device includes an interfacial layer
located between at least one of the metal source or drain
electrodes and the semiconductor substrate, thereby forming a
Schottky or Schottky-like contact. In one embodiment of the present
invention, the interfacial layer is comprised of a conducting,
semiconducting, or insulating material.
[0011] While multiple embodiments are disclosed, still other
embodiments of the present invention will become apparent to those
skilled in the art from the following detailed description, which
shows and describes illustrative embodiments of the invention. As
will be realized, the invention is capable of modifications in
various obvious aspects, all without departing from the spirit and
scope of the present invention. Accordingly, the drawings and
detailed description are to be regarded as illustrative in nature
and not restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates a sectional view of a prior art
Schottky-barrier metal oxide semiconductor field effect transistor
("MOSFET");
[0013] FIG. 2 illustrates transistor curves for a SB-MOS device and
an impurity doped source-drain MOSFET device;
[0014] FIG. 3 illustrate a sectional view of an exemplary
embodiment of the present invention metal-insulator-semiconductor
(MIS) source-drain SB-MOS device;
[0015] FIG. 4 illustrates an exemplary embodiment of the present
invention process using implantation of the semiconductor
substrate;
[0016] FIG. 5 illustrates an exemplary embodiment of the present
invention process using a patterned silicon film on a thin gate
insulator;
[0017] FIG. 6 illustrates an exemplary embodiment of the present
invention process using a formation of thin insulator sidewalls,
and exposure of the silicon in the gate, source and drain
areas;
[0018] FIG. 7 illustrates an exemplary embodiment of the present
invention process using an at least partially isotropic etch;
[0019] FIG. 8 illustrates an exemplary embodiment of the present
invention process using a formation of a thin interfacial
layer;
[0020] FIG. 9 illustrates an exemplary embodiment of the present
invention process using an anisotropic etch;
[0021] FIG. 10 illustrates an exemplary embodiment of the present
invention process using a metal deposition, silicidation anneal,
and removal of unreacted metal;
[0022] FIG. 11 illustrates band diagrams for an exemplary zero
electric field two-terminal MIS diode device;
[0023] FIG. 12 illustrates band diagrams for an exemplary biased
two-terminal MIS diode device;
[0024] FIG. 13 illustrates band diagrams for different gate bias
conditions for the source-channel junction for a SB-MOS device
having only metal in the source-drain regions and no interfacial
insulator layer; and
[0025] FIG. 14 illustrates band diagrams for different gate bias
conditions for the source-channel junction for an exemplary
embodiment of the present invention MIS source-drain SB-MOS
device.
[0026] FIG. 15 illustrates an alternative exemplary embodiment of
the present invention process using a metal gate.
[0027] FIG. 16 illustrates a cross-sectional view of another
exemplary embodiment of the present invention process using a
metal-insulator semiconductor (MIS) source-drain SB-MOS device.
[0028] FIG. 17 illustrates a cross-sectional view of yet another
exemplary embodiment of the present invention process using a
metal-insulator-semiconductor (MIS) source-drain SB-MOS device.
DETAILED DESCRIPTION
[0029] In general, the present invention provides method of
fabrication of SB-MOS devices. In one embodiment of the present
invention, the method includes providing a semiconductor substrate
and doping the semiconductor substrate and channel region. The
method further includes providing a first electrically insulating
layer in contact with the semiconductor substrate. The method
further includes providing a gate electrode on the first insulating
layer, providing a second insulating layer around the gate
electrode including the gate electrode sidewalls, and exposing the
substrate on one or more areas proximal to the gate electrode. In
the present invention, the term proximal is defined as being
located within a lateral distance away of approximately 500 .ANG.
from one or more said objects. For example, in the previous
sentence, the substrate is exposed in one or more areas proximal to
the gate electrode, or the one or more areas are located within a
lateral distance away of approximately 500 .ANG. from the gate
electrode. The method further includes etching of the exposed areas
proximal to the gate electrode using a partially isotropic etch.
The method further includes providing an interfacial layer on the
exposed semiconductor substrate at least in areas proximal to the
gate electrode and first insulating layer, the interfacial layer
comprising a conducting, semiconducting, or insulating material,
but preferably an insulating material. The method further includes
using an anisotropic etch to expose the semiconductor substrate in
areas proximal but not below the gate electrode and providing an
insulating layer on the gate electrode sidewalls. The method
further includes depositing a thin film of metal and reacting the
metal with the exposed substrate, such that a metal silicide forms
on the substrate. The method further includes removing any
unreacted metal.
[0030] One of the advantages of the present invention is that the
metal source and drain electrodes provide significantly reduced
parasitic series resistance (.about.10 .OMEGA.-.mu.m) and contact
resistance (less than 10.sup.-8 .OMEGA.-cm.sup.2). The built-in
Schottky barrier at the Schottky contacts provides superior control
of off-state leakage current. The device substantially eliminates
parasitic bipolar action, making it unconditionally immune to
latch-up, snapback effects, and multi-cell soft errors in memory
and logic. Elimination of bipolar action also significantly reduces
the occurrence of other deleterious effects related to parasitic
bipolar action such as single event upsets and single cell soft
errors. The device of the present invention is easily
manufacturable, requiring two fewer masks for source/drain
formation, no shallow extension or deep source/drain implants, and
a low temperature source/drain formation process. Due to low
temperature processing, integration of new, potentially key
materials such as high K gate insulators, strained silicon and
metal gates is made easier
[0031] FIG. 3 shows a cross-sectional view of a preferred exemplary
embodiment of the present invention, as exemplified by a
metal-insulator-semiconductor (MIS) source-drain SB-MOS structure
300. This embodiment comprises a SB-MOS device in which at least
one of the source 305 or drain 310 regions consist of metal, so
that there is no doping in the source and/or drain regions. In this
embodiment, the device includes an interfacial layer 315, comprised
of a conducting, semiconducting, or insulating material, placed
between at least one of the metal source 305 or drain 310
electrodes and the semiconductor substrate 301, the interfacial
layer 315 being in contact with a channel region 320, thereby
forming a first Schottky barrier or Schottky-like contact 325 to
the channel region 320. In one preferred embodiment, the
interfacial layer 315 is an insulating material. A second Schottky
or Schottky-like barrier 330 is formed along the portion of the
metal source 305 and/or drain 310 electrodes having direct contact
between the metal and the semiconductor substrate 301. The present
invention does not recognize any limitations in regards to what
types of metals may be used in affecting the teachings of the
present invention. Thus, metals commonly used at the transistor
level, such as titanium, cobalt and the like, are specifically
anticipated, as well as a plethora of more exotic metals and other
alloys. Various metal silicides may also be employed, such as
Platinum silicide, Palladium silicide, Iridium Silicide, and/or the
rare-earth silicide, all of which should be considered as being
within the scope of the teachings of the present invention. It is
also noted that in another embodiment, the metal source/drain
regions 305,310 may be composed of multiple layers of metals and/or
metal silicides.
[0032] In one preferred embodiment, an Indium or Arsenic layer 340
is used as the channel and substrate dopants for a Schottky barrier
N-type MOSFET (SB-NMOS) or a Schottky barrier P-type MOSFET
(SB-PMOS) devices, respectively. These dopant atoms are used due to
their relatively low rates of diffusion through the silicon lattice
(compared to Phosphorous and Boron, the other two possible
candidates for channel and substrate dopants). This allows for
greater thermal budget during fabrication of the device, and
therefore less statistical variation in the characteristics of the
finished product. The present invention does not recognize any
limitations in regards to what types of dopants may be used in the
present invention.
[0033] In one preferred embodiment, the gate electrode 345 is
fabricated from Boron or Phosphorous doped polysilicon films for
the P-type and N-type devices, respectively. In this instance,
Boron or Phosphorous are used due to their large solid-solubilities
(compared to Arsenic and Indium). Alternatively, a metal gate may
be used. In the present embodiment, the gate electrode 345 may be
less than 100 nm in width (corresponding to the channel length L).
The gate electrode 345 has an electrically insulating sidewall 350,
which may be an oxide, a nitride, or a multi-layer stack of
differing insulating materials.
[0034] Devices are separated from each other by an insulating layer
(not shown), such as a thermally grown oxide (called a Field Oxide)
that works in conjunction with channel and substrate dopants to
electrically isolate the devices from each other. This field oxide
may be provided for by a conventional process, such as a LOCOS or
STI process.
[0035] One exemplary process for the fabrication of a MIS
source/drain SB-MOS device is illustrated in FIGS. 4-10. While this
process is exemplary of the broad teachings of the present
invention, it will be instructive to one skilled in the art to
teach the fundamental concepts of the present invention. It is
noted that this exemplary process is not limitive and that
additional processes which are specifically anticipated by the
present invention will be apparent to one skilled in the art. This
exemplary process flow may be described as follows:
[0036] FIG. 4 shows a silicon substrate 410 that has means for
electrically isolating transistors from one another. Throughout the
discussion herein, there will be examples provided that make
reference to a semiconductor substrate on which an SB-MOS device is
formed. The present invention does not restrict the semiconductor
substrate to any particular type. One skilled in the art will
readily realize that many semiconductor substrates may be used for
SB-MOS including silicon, silicon germanium, gallium arsenide,
indium phosphide, strained semiconductor substrates, silicon on
insulator, substrates of various crystallographic orientation such
as <110> and <100>. In another embodiment, the silicon
substrate 410 is strained. The use of a strained silicon substrate
410 in combination with a SB-MOS device results in additional
improvements in power and speed performance. In another embodiment,
the substrate is SOI. An SOI substrate comprises a semiconductor
material, such as silicon having a thickness of approximately 20 nm
to 100 nm, on a buried insulating material, such as silicon dioxide
(SiO.sub.2) having a thickness of approximately 100 nm to 400 nm,
which is formed on a semiconductor substrate. These substrate
materials and others may be used and are within the scope of the
teachings of the present invention.
[0037] As shown in FIG. 4, a thin screen oxide 420 is grown on the
substrate 410 to act as an implant mask. In one embodiment, the
oxide is grown to a thickness of about 200 .ANG.. The appropriate
channel dopant species 430 is then ion-implanted through the screen
oxide 420 such that a maximum dopant concentration 440 is provided
to a pre-determined depth D1 (450) in the silicon. In one
embodiment the channel dopant species is Arsenic for P-type devices
and Indium for N-type devices, however any other channel dopant
species commonly used at the transistor for P-type or N-type
devices is specifically anticipated by the present invention. In
another embodiment, the channel dopant concentration profile varies
significantly in the vertical direction but is generally constant
in the lateral direction. In a further embodiment, the depth D1 450
of the maximum dopant concentration is approximately 20 to 200
nm.
[0038] As shown in FIG. 5, the screen oxide is then removed in a
chemical etch, and a thin gate insulator 510, such as silicon
dioxide is grown. In one embodiment the screen oxide etch is
comprised of hydrofluoric acid, however other chemistries commonly
used to etch oxide, including both wet and dry etches, are
specifically anticipated. In another embodiment, the thin gate
insulator is comprised of silicon dioxide with a thickness of
approximately 6 to 50 .ANG.. In a further embodiment, a material
having a high dielectric constant (high K) is provided. Examples of
high K materials are those materials having dielectric constants
greater than that of silicon dioxide, including for example
nitrided silicon dioxide, silicon nitride, and metal oxides such as
TiO.sub.2, Al.sub.2O3, La.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2,
CeO.sub.2, Ta.sub.2O.sub.5,WO.sub.- 3, Y.sub.2O.sub.3, and
LaAlO.sub.3, and the like. The gate insulator growth is immediately
followed by providing an in-situ doped silicon film. The gate
insulator growth is immediately followed by providing an in-situ
doped silicon film. The film is heavily doped with, for example,
Phosphorous for an N-type device and Boron for a P-type device.
Using lithographic techniques and a silicon etch that is highly
selective to the gate insulator, the gate electrode 520 is
patterned as shown in the process step 500 illustrated in FIG. 5.
In another exemplary embodiment, a metal gate electrode may be
provided. In another embodiment, following gate electrode
patterning, additional channel dopants are provided and result in a
channel dopant concentration profile that varies significantly in
both the vertical and lateral directions.
[0039] As shown in FIG. 6, a thin insulator is then provided on the
top surface 625 and sidewalls 610 of the silicon gate electrode
520. In one embodiment, the thin insulator is a thermally grown
oxide that has a thickness of approximately 50 to 500 .ANG.. In
another embodiment, the thermally grown thin oxide is provided by a
rapid thermal oxidation (RTO) process having a maximum temperature
of 900 to 1200.degree. C. for a dwell time of 0.0 to 60 seconds.
One skilled in the art will readily realize that there are many
manufacturing methods for providing thin insulator layers such as
deposition. One skilled in the art will further realize that other
materials may be used for the thin insulator such as nitrides and
the insulating layer may be comprised of multiple insulator
materials. An anisotropic etch is then used to remove the insulator
layer on the horizontal surfaces (and thus expose the silicon 620,
625) thereby exposing the horizontal surface, while preserving the
insulator layer on the vertical surfaces. In this way, a sidewall
insulator 610 is formed. It will be obvious to one skilled in the
art that the gate electrode 520 and the sidewall insulator 610
function as a mask to the anisotropic etch such that the openings
in the thin insulator layer on the silicon substrate are proximal
with the gate electrode 520. In the embodiment in which the thin
insulator is approximately 50 to 500 .ANG., the openings in the
thin insulator layer will be proximal to the gate electrode 520 and
located within a lateral distance away from the gate electrode 520
that is approximately 50 to 500 .ANG.. In one exemplary embodiment,
the silicon surface 620 is recessed below the bottom of the gate
insulator to a depth D2 630 of approximately 1 nm to approximately
5 nm. In the embodiment in which an RTO process is used to provide
the sidewall insulator, the dopants both in the gate electrode and
in the channel region of the device are electrically activated
simultaneously with the sidewall insulator formation, as shown in
the process step 600 illustrated in FIG. 6.
[0040] As shown in FIG. 7, a second etch process step etches the
semiconductor substrate both laterally and vertically. This etch is
known as a partially isotropic etch. In one embodiment, a partially
isotropic etch having a lateral etch rate at least 10% of a
vertical etch rate is used. In another embodiment, a partially
isotropic etch having a vertical etch rate at least 10% of a
lateral etch rate is used. The depth of the second etch is D3 710.
The lateral etch displaces the exposed vertical sidewall of the
semiconductor substrate 720 laterally a distance L1 730 from the
edge of the sidewall oxide 610 to a position below the gate
electrode 520. Because the etch is partially isotropic, L1 may be
less than or equal to ten times D3 or D3 may be less than or equal
to ten times L1. In yet another embodiment, an etch having a
lateral etch rate approximately equal to a vertical etch rate is
used. For this embodiment, D3 may be approximately equal to L1. The
lateral etch provides a means for decreasing the channel length by
an amount of approximately two times L1. In one embodiment, the
vertical etch rate is sufficient to form an exposed vertical
surface 720 of the semiconductor substrate 410 laterally below the
gate electrode 520, as shown in the process step 700 illustrated in
FIG. 7. In yet a further embodiment, the partially isotropic etch
is provided by any one or a combination of a SF.sub.6 dry etch, a
HF:HNO.sub.3 wet etch, or any wet or dry etch that is commonly used
for the purpose of etching semiconductor material.
[0041] As shown in FIG. 8, an interfacial layer 810 is formed on
the exposed horizontal and vertical surfaces of the semiconductor
substrate 410. In one embodiment, the interfacial layer 810 is a
thermally grown silicon nitride (Si.sub.3N.sub.4) having a
thickness of less than about 2 nm as shown in the process step 800
illustrated in FIG. 8. In another embodiment, the interfacial layer
810 is comprised of either a metal, semiconductor or insulating
material.
[0042] Process step 900 shown in FIG. 9, provides a third
anisotropic etch to etch through the interfacial layer 810 and
expose the semiconductor substrate 410, at least in areas proximal
but not below the gate electrode 520 and gate electrode sidewall
spacer 610. This etch exposes the silicon substrate to a depth D4
(910).
[0043] As shown in FIG. 10, the next step encompasses depositing an
appropriate metal as a blanket film on all exposed surfaces.
Deposition may be provided by either a sputter or evaporation
process or more generally any thin film formation process. In one
embodiment, the substrate is heated during metal deposition to
encourage diffusion of the impinging metal atoms to the exposed
silicon surface 810, below the gate insulator. In one embodiment,
this metal is approximately 250 .ANG. thick but more generally
approximately 50 to 1000 .ANG. thick. Throughout the discussion
herein there will be examples provided that make reference to
Schottky and Schottky-like barriers and contacts in regards to IC
fabrication. The present invention does not recognize any
limitations in regards to what types of Schottky interfaces may be
used in affecting the teachings of the present invention. Thus, the
present invention specifically anticipates these types of contacts
to be created with any form of conductive material or alloy. For
example, for the P-type device, the metal source and drain
1010,1020 may be formed from any one or a combination of Platinum
Silicide, Palladium Silicide, or Iridium Silicide. For the N-type
device, the metal source and drain 1010,1020 may be formed from a
material from the group comprising Rare Earth Silicides such as
Erbium Silicide, Dysprosium Silicide or Ytterbium Silicide, or
combinations thereof. Any other metals commonly used at the
transistor level, such as titanium, cobalt and the like, are
specifically anticipated, as well as a plethora of more exotic
metals and other alloys. In another embodiment, the silicided
source/drain can be made of multiple layers of metal silicide, in
which case other exemplary silicides, such as titanium silicide or
tungsten silicide for example, may be used.
[0044] The wafer is then annealed for a specified time at a
specified temperature so that, at all places where the metal is in
direct contact with the silicon, a chemical reaction takes place
that converts the metal to a metal silicide 1010, 1020, 1030. In
one embodiment, for example, the wafer is annealed at about
400.degree. C. for about 45 minutes or more generally approximately
300 to 700.degree. C. for approximately 1 to 120 min. The metal
that was in direct contact with a non-silicon surface such as the
gate sidewall spacer 610 is left unreacted and thereby
unaffected.
[0045] A wet chemical etch is then used to remove the unreacted
metal while leaving the metal-silicide untouched. In one
embodiment, aqua regia is used to remove Platinum and HNO.sub.3 is
used to remove Erbium. Any other etch chemistries commonly used for
the purpose of etching Platinum or Erbium, or any other metal
systems used to form Schottky or Schottky-like contacts are
specifically anticipated by the present invention. The MIS
source-drain SB-MOS device is now complete and ready for electrical
contacting to gate 520, source 1010, and drain 1020, as shown in
the process step 1000 illustrated in FIG. 10.
[0046] As a result of this exemplary process, Schottky or
Schottky-like contacts are formed to the channel region 1040 and
substrate 410 respectively wherein the Schottky contacts are
located at a position controlled by the partially isotropic etch
process. In one embodiment, the interface 810 of the source 1010
and drain 1020 electrodes to the channel region 1040 is located
laterally below the spacer 610 and is aligned with the edge of the
sides of the gate electrodes 1040. In another embodiment, the
interface 810 of the source 1010 and drain 1020 electrodes to the
channel region 1040 is located laterally below the spacer 610 and
partially below the gate electrode 520. In yet another embodiment,
a gap is formed between the interface 810 of the source 1010 and
drain 1020 electrodes to the channel region 1040 and the edge of
the sides of the gate electrode 520.
[0047] While traditional Schottky contacts are abrupt, in the
present invention an interfacial layer is utilized between the
silicon substrate and the metal. This interfacial layer may be
ultra-thin, having a thickness of approximately 10 nm or less.
Thus, the present invention specifically anticipates Schottky-like
contacts and their equivalents to be useful in implementing the
present invention. Furthermore, the interfacial layer may comprise
materials that have conductive, semi-conductive, or insulator-like
properties. For example, ultra-thin interfacial layers of oxide or
nitride insulators may be used, or ultra-thin dopant layers formed
by dopant segregation techniques may be used, or ultra-thin
interfacial layers of a semiconductor such as Germanium may be used
to form Schottky-like contacts, among others.
[0048] By using the techniques of the present invention, several
benefits occur. First, the metal-insulator-semiconductor (MIS)
structure provides a means for dynamically controlling the
effective Schottky barrier height of the SB-MOS device. Referencing
FIG. 11, band diagrams for an exemplary MIS diode device are shown.
Basic operating principles and terminology are described in the PhD
thesis of Mark Sobolewski, Stanford University, 1989.
[0049] In FIG. 11, the band diagram for an N-type MIS diode is
shown in an idealized zero electric field state. In practice, a
finite built-in field may be present in the interfacial insulator
layer. The metal work function .phi..sub.m (1105) and semiconductor
electron affinity .chi..sub.s (1110) are referenced to the
conduction band (1115) of the insulating layer. E.sub.fm (1120) and
E.sub.fs (1125) are the metal and semiconductor Fermi levels
respectively, while E.sub.c (1130) is the conduction band. V.sub.d
(1135) and V.sub.i (1140) are the potential drops in the
semiconductor substrate depletion region and insulator
respectively, while .zeta. (1145) is the separation between the
Fermi level and the conduction band deep in the bulk of the
semiconductor. The insulator thickness is t.sub.i (1150) and the
effective Schottky barrier height .phi..sub.b,1 (1155) is defined
to be the separation between E.sub.fm (1120) and E.sub.c (1130) at
the silicon-insulator interface. In the idealized zero electric
field state, .phi..sub.b,1 (1155) is determined by .phi..sub.m
(1105) and .chi..sub.s (1110), both physical properties of the
system.
.phi..sub.b1=.phi..sub.m-.chi..sub.s. Equation 1
[0050] In FIG. 12, a positive bias is applied to the metal relative
to the grounded semiconductor substrate, thereby shifting E.sub.fm
(1120) up by -V (1205) relative to E.sub.fs (1125). This induces an
electric field at the interfacial insulator layer .epsilon..sub.s
(1210), thereby creating a potential drop V.sub.i (1215) across the
insulator. In this state, the new effective Schottky barrier height
.phi..sub.b,2 (1220) is given by Equation 2.
.phi..sub.b,2=-.chi..sub.s-V.sub.i=.phi..sub.b,1-V.sub.i Equation
2
[0051] Therefore, the potential drop V.sub.i (1215) in the
insulator interfacial layer provides a means for dynamically
changing the effective Schottky barrier height .phi..sub.b,2 (1220)
between the metal and the semiconductor substrate by an amount
V.sub.i (1215). The potential drop in the insulator layer will be a
function of the insulator layer thickness t.sub.i (1150), the metal
bias 1205 and therefore the electric field strength .epsilon..sub.s
1210 at the insulator, and the insulator dielectric constant.
[0052] These principles can be applied to a SB-MOS device having
MIS source and drain contacts. When considering the MOSFET
operational characteristics, the segment of the MIS source
electrode in contact with the channel region and immediately below
the gate insulator dominates the device performance, particularly
in the on-state. Furthermore, due to the three terminal MOSFET
structure, the electrostatic fields in the channel region of the
MOSFET have a two-dimensional character. For this reason, the
induced Schottky barrier modulation along the interface of the
source electrode to the channel region varies, having a maximum
where the source intersects the channel and gate insulator. The
following discussion references an "active" source MIS region. This
is the source MIS structure immediately below the gate insulator,
which extends approximately 5-20 nm below the gate insulator along
the source-channel junction. It is the region where the gate
induced electric field provides the strongest potential drop in the
MIS insulator and where approximately over 90% of current emission
from the source electrode occurs in the on-state.
[0053] In the off-state, with the gate and source contacts grounded
and the drain biased at V.sub.dd, a first electric field will be
provided at the insulator of the source MIS structure, causing a
first potential drop across the insulator V.sub.i,d and therefore a
first effective Schottky barrier height .phi..sub.bd. However, an
important difference between a three terminal MIS source-drain
MOSFET device of the present invention and a two terminal MIS diode
is the third terminal, the gate electrode, which is located in
close proximity to the MIS structure at the source. Depending on
the MOSFET geometry, the gate electrode may be displaced from the
source by approximately 1 nm while the drain electrode is displaced
by 10's of nm. In the on-state, the source contact remains grounded
while the drain and gate are both biased at V.sub.dd. Due to the
close proximity of the gate to the source, a second electric field,
substantially larger than the first electric field, is formed in
the active source MIS region, thereby inducing a second potential
drop across the insulator V.sub.idg and a second effective barrier
height .phi..sub.bdg. Along the vertically oriented portion of the
source electrode, adjacent to the channel region, the gate-induced
electric field decreases while moving down from the gate insulator,
thereby causing V.sub.idg to decrease and therefore .phi..sub.bdg
to increase as a function of position. The Schottky barrier height
modulation dramatically affects the current emission
characteristics from the source electrode.
[0054] For SB-MOS technology, current emission from the source
electrode is provided by a tunneling mechanism in the on-state.
FIG. 13 shows the band diagrams for three different gate biases
(V.sub.g) at the source-channel interface for a conventional n-type
SB-MOS device not having an MIS structure. As shown, in the region
near the source electrode, the conduction band forms a nearly
triangular barrier 1310, 1320, 1330. The total tunneling current
through this Schottky barrier is exponentially sensitive to the
barrier height .phi..sub.b 1340 but also the electric field at the
Schottky barrier contact .epsilon..sub.s 1350,1351,1352. It is
important to note that for this device, the barrier height
.phi..sub.b 1340 is fixed, and the gate modulates .epsilon..sub.s,
1350, 1351, 1352 thereby increasing the tunneling current as the
gate bias is increased.
[0055] FIG. 14 shows the band diagrams for three different gate
biases Vg at the source-channel interface for an N-type SB-MOS
device having an MIS source/drain structure. Only a portion of the
bands of the MIS insulator layer are shown. In the region near the
source electrode, the conduction band again forms a nearly
triangular barrier 1410, 1420, 1430. For a MIS device, the
effective barrier height b 1440, 1441, 1442 is modulated by the
gate at the same time .epsilon..sub.s 1450, 1451, 1452 is
modulated, thereby providing two mechanisms for increasing the
tunneling current, not just one (.epsilon..sub.s modulation) as is
the case for a conventional SB-MOS device. This effect will occur
for any V.sub.d as long as V.sub.g is biased and will thereby
provide improved drive current for low V.sub.d, reducing the
sub-linear turn-on characteristic at low V.sub.d and improving the
turn-on performance of the SB-MOS device and providing higher drive
current.
[0056] It is important that the insulator not be too thick, as the
charge carrier tunneling probability will eventually be inhibited
by the insulator barrier, thereby diminishing the net benefit of
modulating the Schottky barrier to a lower level.
[0057] An additional benefit of the MIS source-drain SB-MOS device
structure is that for a sufficiently thick insulator interfacial
layer, it will block the penetration of the metal states, which
cause pinning in the silicon. (see for example D. Connelly, et. al.
in "A New Route to Zero-Barrier Metal Source-Drain MOSFETs"
presented at the 2003 VLSI Symposium, Kyoto, 2003). This provides a
means for affecting the initial barrier height prior to any gate
biasing, and may allow for the introduction of other metals or
metal alloys to be used as metal source-drain contacts.
[0058] In summary, an interfacial layer disposed between the metal
source-drain contacts and the semiconductor substrate of an MIS
source/drain SB-MOS device provides a means for affecting the
unbiased initial effective Schottky barrier height, and furthermore
provides a means for dynamically adjusting the Schottky barrier
height by changing the gate, and secondarily the drain bias. This
enables the introduction of numerous metals, metal silicides and/or
metal alloys for affecting the preferred embodiments of the
teachings of the present invention, which otherwise would not be
possible if employing a pure metal-semiconductor Schottky barrier
junction having no interfacial layer. It further enables
substantially improved low V.sub.d turn-on characteristics and
higher drive currents.
[0059] FIG. 15 shows a cross-sectional view of another preferred
exemplary embodiment of the present invention, as exemplified by a
metal-insulator-semiconductor (MIS) source-drain SB-MOS structure
1500. This embodiment comprises a SB-MOS device in which at least
one of the source 1505 or drain 1510 regions consist of a first
1506 and second 1507 metal, so that there is no doping in the
source and/or drain regions. In this embodiment, the device
includes an interfacial layer 1515, either conducting,
semiconducting, or insulating, placed between the first metal 1506
and the semiconductor substrate 1501, the interfacial layer 1515
being in contact with a channel region 1520, thereby forming a
first Schottky barrier or Schottky-like contact 1525 to the channel
region 1520. The interfacial layer 1515 is furthermore placed
between the second metal 1507 and the semiconductor substrate,
thereby forming a second Schottky barrier or Schottky-like contact
1526 to the semiconductor substrate 1501.
[0060] The first and second metals may be provided using the
following exemplary process. Following process step 800 shown in
FIG. 8, a first metal is isotropically deposited, including in any
regions below the gate electrode. The first metal is subsequently
anisotropically etched. A second metal is then directionally
deposited, to minimize deposition on sidewalls of the gate
electrode and a short isotropic etch is used to remove any metals
deposited on the gate electrode sidewalls or other vertical
surfaces. The transistor is masked and a more thorough isotropic
etch of the second metal is provided. In one exemplary embodiment,
the first metal, located primarily below the gate electrode, is
selected for its Schottky barrier height properties to the channel
region in order to optimize the drive and/or to optimize the
leakage current of the device. In another exemplary embodiment, the
second metal, which fills the bulk of the source-drain regions may
be chosen based on its conductivity, with high conductivity metals
preferred. Furthermore, it may be engineered as an alloy or a stack
of metals so that for example it presents a mid-gap barrier between
the bulk of the source/drain regions and the semiconductor
substrate in order to control off-state leakage for both SB-NMOS
and SB-PMOS simultaneously. An alloy or metal stack may also be
employed for the second metal for optimizing conductivity or for
its process integration properties, such as its ability to provide
an etch stop when forming contact holes for the metallization and
wiring of the transistor device. The aforementioned selection
criteria for the first and second metals applies to this and all
other embodiments disclosed previously or subsequently.
[0061] The present invention does not recognize any limitations in
regards to what types of first or second metals may be used in
affecting the teachings of the present invention. Thus, metals
commonly used at the transistor level, such as titanium, cobalt and
the like, are specifically anticipated, as well as a plethora of
more exotic metals and other alloys that provide an appropriate
first and second Schottky barrier to optimize device performance.
Various metal silicides may also be employed such as Platinum
silicide, Palladium silicide, Iridium Silicide, and/or the
rare-earth silicides, all of which should be considered as being
within the scope of the teachings of the present invention. In
another embodiment, the first and second metals are the same and
may be provided in the same process step or in two different
process steps.
[0062] An Indium or Arsenic layer 1540 is used as the channel and
substrate dopants for an NMOS or PMOS devices, respectively. Boron
may also be used as a channel and substrate dopant for the NMOS
device. The gate electrode 1545 is fabricated from Boron or
Phosphorous doped polysilicon films for the P-type and N-type
devices, respectively. Alternatively, a metal gate may be used. The
gate electrode 1545 has a gate insulator 1550 and an electrically
insulating sidewall 1551, which may be an oxide, a nitride, or a
multi-layer stack of differing insulating materials as shown in
device 1500 in FIG. 15.
[0063] FIG. 16 shows a cross-sectional view of yet another
preferred exemplary embodiment of the present invention, as
exemplified by a metal-insulator-semiconductor (MIS) source-drain
SB-MOS structure 1600. This embodiment comprises a SB-MOS device in
which at least one of the source 1605 or drain 1610 regions consist
of a first 1606 and second 1607 metal, so that there is no doping
in the source and/or drain regions. In this embodiment, the device
includes a first interfacial layer 1615, either conducting,
semiconducting, or insulating, placed between the first metal 1606
and the semiconductor substrate 1601, the first interfacial layer
1615 being in contact with a channel region 1620, thereby forming a
first Schottky barrier or `Schottky-like` contact 1625 to the
channel region 1620. A second thick interfacial layer 1617 is
furthermore placed between the second metal 1607 and the
semiconductor substrate 1601. The second interfacial layer 1617 may
be provided by angled, rotated deposition. The second interfacial
layer 1617 is not necessarily composed of the same material or
materials of the first interfacial layer 1615. The second
interfacial layer provides a large potential barrier to current
transport from the second metal to the semiconductor substrate,
thereby reducing source-drain leakage current. In another exemplary
embodiment, the first and second metals are the same and may be
provided in the same process step or in two different process
steps.
[0064] The second interfacial layer may be provided by a
source-drain localized LOCOS process, otherwise called a
micro-LOCOS process. Following process step 700 shown in FIG. 7, a
thin pad oxide is deposited, followed by deposition of a thicker
nitride layer. An anisotropic etch is used to etch through the
nitride and pad oxide in the source-drain region, exposing the
semiconductor substrate. A thick oxide is thermally grown on the
exposed semiconductor substrate and a phosphoric strip removes any
exposed nitride layers. A short hydrofluoric acid dip removes the
pad oxide on the vertical sidewalls of the channel region, followed
by formation of a thin thermally grown nitride layer. An advantage
of this present embodiment is it avoids placing a thick insulator
on top of the gate electrode, which may be a result of a straight
deposited insulator. A first metal is isotropically deposited,
including in any regions below the gate electrode and is
anisotropically etched. A second metal is directionally deposited,
to minimize deposition on sidewalls of the gate electrode and a
short isotropic etch is used to remove any metals deposited on the
gate electrode sidewalls or other vertical surfaces. The transistor
is masked and a more thorough isotropic etch of the second metal is
provided. The present invention does not recognize any limitations
in regards to what types of first or second metals may be used in
affecting the teachings of the present invention. Thus, metals
commonly used at the transistor level, such as titanium, cobalt and
the like, are specifically anticipated, as well as a plethora of
more exotic metals and other alloys that provide an appropriate
first Schottky barrier to optimize device performance. Various
metal silicides may also be employed, such as Platinum silicide,
Palladium silicide, Iridium Silicide, and/or the rare-earth
silicides, all of which should be considered as being within the
scope of the teachings of the present invention.
[0065] An Indium or Arsenic layer 1640 is used as the channel and
substrate dopants for an NMOS or PMOS devices, respectively. Boron
may also be used for the channel and substrate dopant for NMOS. The
gate electrode 1645 is fabricated from Boron or Phosphorous doped
polysilicon films for the P-type and N-type devices, respectively.
Alternatively, a metal gate may be used. The gate electrode 1645
has a gate insulator 1650 and an electrically insulating sidewall
1660, which may be an oxide, a nitride, or a multi-layer stack of
differing insulating materials as shown in device 1600 in FIG.
16.
[0066] Referencing FIG. 16, in yet another exemplary embodiment, a
metal-semiconductor (MIS) source-drain SB-MOS structure may be
employed. In this structure, the first interfacial layer 1615 would
not be provided, so that the first metal 1606 is in direct contact
with the channel region 1620. To emphasize, no interfacial layer is
provided between the first metal 1606 and the channel region 1620.
In this embodiment, the first metal layer 1606 may be a metal, an
alloy or a silicide. Furthermore, the second metal layer 1607 may
be provided using the same methods described above, including for
example directional deposition techniques.
[0067] FIG. 17 shows a cross-sectional view of yet another
preferred exemplary embodiment of the present invention, as
exemplified by a metal-insulator-semiconductor (MIS) source-drain
SB-MOS structure 1700. This embodiment comprises a SB-MOS device in
which the source 1705 and/or drain 1710 regions consist of a first
1706 and optionally a second 1707 metal, so that there is no doping
in the source and/or drain regions. In this embodiment, the device
includes an interfacial layer 1715, either conducting,
semiconducting, or insulating, placed between the first metal 1706
and the semiconductor substrate 1701, the interfacial layer 1715
being in contact with a channel region 1720, thereby forming a
first Schottky barrier or `Schottky-like` contact 1725 to the
channel region 1720. The source 1705 and drain 1710 regions are in
contact with a buried oxide 1717, such as that of an SOI substrate.
The buried oxide 1717 provides a large potential barrier to current
transport from the second metal 1707 to the semiconductor substrate
1701, thereby reducing source-drain leakage current. In another
exemplary embodiment, the first and second metals 1706,1707 are the
same and may be provided in the same process step or in two
different process steps.
[0068] The first and second metals 1706,1707 may be provided using
the following exemplary process. Following process step 800 shown
in FIG. 8, the first metal 1706 is isotropically deposited,
including in any regions below the gate electrode 1745. The first
metal 1706 is subsequently anisotropically etched. The second metal
1707 is then directionally deposited, to minimize deposition on
sidewalls 1760 of the gate electrode 1745 and a short isotropic
etch is used to remove any metals deposited on the gate electrode
sidewalls 1760 or other vertical surfaces. The transistor is masked
and a more thorough isotropic etch of the second metal 1707 is
provided. The first and second metals 1706,1707 are selected based
on criteria previously noted. In another embodiment, the first and
second metals 1706,1707 are the same and may be provided in the
same process step or in two different process steps.
[0069] An Indium or Arsenic layer is used as the channel dopants
for an NMOS or PMOS devices, respectively. Boron may also be used
for the channel and substrate dopant for NMOS. The gate electrode
1745 is fabricated from Boron or Phosphorous doped polysilicon
films for the P-type and N-type devices, respectively.
Alternatively, a metal gate may be used. The gate electrode 1745
has a gate insulator 1750 and the electrically insulating sidewall
1760, which may be an oxide, a nitride, or a multi-layer stack of
differing insulating materials as shown in the structure 1700 in
FIG. 17.
[0070] Referencing FIG. 17, in yet another exemplary embodiment, a
metal-semiconductor (MIS) source-drain SB-MOS structure may be
employed. In this structure, the interfacial layer 1715 would not
be provided, so that the first metal 1706 is in direct contact with
the channel region 1720. To emphasize, no interfacial layer is
provided between the first metal 1706 and the channel region 1720.
In this embodiment, the first metal layer 1706 may be a metal, an
alloy or a silicide. Furthermore, the second metal layer 1707 may
be provided using the same methods described above, including for
example directional deposition techniques.
[0071] The present invention is particularly suitable for use in
situations where short channel length MOSFETs are to be fabricated,
especially in the range of channel lengths less than 100 nm.
However, nothing in the teachings of the present invention limits
application of the teachings of the present invention to these
short channel length devices. Advantageous use of the teachings of
the present invention may be had with channel lengths of any
dimension. The present invention further anticipates the use of a
plethora of channel, substrate and well implant profiles. For
example, the channel implant may be a simple profile whose profile
varies significantly in the vertical direction and is generally
constant in the lateral direction. Or, for example the channel
implant profile may be approximately symmetric, having a lateral
maximum concentration in approximately the center of the channel
region. Or, laterally and vertically non-uniform doping profiles
may be used.
[0072] Although the present invention has been described with
reference to preferred embodiments, persons skilled in the art will
recognize that changes may be made in form and detail without
departing from the spirit and scope of the invention. The present
invention may be used with any of a number of channel, substrate
and well implant profiles. The present invention applies to any use
of metal source drain technology, whether it employs SOI substrate,
strained Silicon substrate, SiGe substrate, FinFET technology, high
K gate insulators, and metal gates. This list is not limitive. Any
device for regulating the flow of electric current that employs
metal source-drain contacts will have the benefits taught
herein.
[0073] While, the present invention is particularly suitable for
use with SB-MOS semiconductor devices, it may also be applied to
other semiconductor devices. Thus, while this specification
describes a fabrication process for use with SB-MOS devices, this
term should be interpreted broadly to include any device for
regulating the flow of electrical current having a conducting
channel that has two or more points of electrical contact wherein
at least one of the electrical contacts is a Schottky or
Schottky-like contact.
* * * * *