U.S. patent application number 10/962236 was filed with the patent office on 2005-05-26 for methods and chemistry for providing initial conformal electrochemical deposition of copper in sub-micron features.
This patent application is currently assigned to APPLIED MATERIALS, INC.. Invention is credited to Hafezi, Hooman, Rosenfeld, Aron, Sun, Zhi-Wen, Yang, Michael X., Yu, Chunman.
Application Number | 20050109627 10/962236 |
Document ID | / |
Family ID | 34594727 |
Filed Date | 2005-05-26 |
United States Patent
Application |
20050109627 |
Kind Code |
A1 |
Sun, Zhi-Wen ; et
al. |
May 26, 2005 |
Methods and chemistry for providing initial conformal
electrochemical deposition of copper in sub-micron features
Abstract
A method for electrolytically repairing a copper seed layer. The
method includes positioning the seed layer in fluid communication
with a low conductivity seed layer repair solution, wherein the low
conductivity seed layer repair solution includes a copper
concentration of less than about 20 g/l, a pH of less than about 4,
a chlorine ion concentration of between about 20 ppm and about 100
ppm, and an additive organic surfactant configured to suppress a
copper deposition rate in the concentration range of 200 ppm to
2000 ppm. The method further includes applying a seed layer repair
bias configured to generate a current density of less than about 5
mA/cm.sup.2 across the seed layer and cleaning the repaired seed
layer in pure water containing less than 1 ppm chloride ions.
Inventors: |
Sun, Zhi-Wen; (San Jose,
CA) ; Hafezi, Hooman; (Redwood City, CA) ; Yu,
Chunman; (Campbell, CA) ; Rosenfeld, Aron;
(Palo Alto, CA) ; Yang, Michael X.; (Palo Alto,
CA) |
Correspondence
Address: |
MOSER, PATTERSON & SHERIDAN, LLP/
APPLIED MATERIALS, INC.
3040 POST OAK BOULEVARD, SUTIE 1500
HOUSTON
TX
77056
US
|
Assignee: |
APPLIED MATERIALS, INC.
|
Family ID: |
34594727 |
Appl. No.: |
10/962236 |
Filed: |
October 8, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60510190 |
Oct 10, 2003 |
|
|
|
Current U.S.
Class: |
205/115 ;
205/170; 205/291; 257/E21.175 |
Current CPC
Class: |
H01L 21/76843 20130101;
H01L 21/76873 20130101; H01L 21/2885 20130101; C25D 7/123 20130101;
H01L 21/76868 20130101; C25D 5/10 20130101; C25D 3/38 20130101;
H01L 2221/1089 20130101 |
Class at
Publication: |
205/115 ;
205/170; 205/291 |
International
Class: |
C25D 005/02 |
Claims
1. A method for electrolytically repairing a copper seed layer,
comprising: positioning the seed layer in fluid communication with
a low conductivity seed layer repair solution, the low conductivity
seed layer repair solution comprising: a copper concentration of
less than about 20 g/l; a pH of less than about 4; a chlorine ion
concentration of between about 20 ppm and about 100 ppm; and an
additive organic surfactant configured to suppress a copper
deposition rate at a concentration of between about 100 ppm and
about 2000 ppm; and applying a seed layer repair bias configured to
generate a current density of less than about 5 mA/cm.sup.2 across
the seed layer.
2. The method of claim 1, wherein the pH of the seed layer repair
solution is greater than about 1.5.
3. The method of claim 1, wherein the additive organic surfactant
comprises at least one of polyethylene glycol and copolymers of
ethylene oxide-propylene oxide.
4. The method of claim 1, wherein an electrical conductivity of the
seed layer repair solution is between about 6 mS/cm and about 20
mS/cm.
5. The method of claim 1, wherein positioning the seed layer
comprises immersing the seed layer into the seed layer repair
solution while simultaneously applying a forward immersion bias to
the seed layer.
6. The method of claim 1, wherein the copper concentration is
between about 3 g/l and about 10 g/l.
7. The method of claim 1, wherein the low conductivity seed layer
repair solution further comprises between about 0.1 g/l and about
1.0 g/l of acid.
8. A method for filling a semiconductor feature having a seed layer
deposited thereon with a conductive material, comprising:
positioning the seed layer in a first plating solution, the first
plating solution comprising a pH of between about 1.5 and about 4.0
and a copper concentration of between about 3 g/l and about 10 g/l;
applying a first plating bias to the seed layer to plate a metal
onto discontinuities in the seed layer, the first plating bias
being configured to generate a first current density across the
seed layer of less than about 5 mA/cm.sup.2; removing the seed
layer from the first plating solution; cleaning the seed layer of
residual chemical constituents from the first plating with a
cleaning solution, wherein the cleaning solution comprises less
than about 1 ppm of chlorine ions; positioning the seed layer in a
second plating solution, the second plating solution being
different from the first plating solution; and applying a second
plating bias to the seed layer to deposit a feature fill layer,
wherein the second plating bias is configured to generate a second
current density across the seed layer that is greater than the
first current density.
9. The method of claim 8, wherein the first plating solution
further comprises: a copper concentration of between about 3 g/l
and about 20 g/l; a chlorine concentration of between about 20 ppm
and about 100 ppm; and an organic surfactant at a concentration of
between about 100 ppm and 2000 ppm.
10. The method of claim 9, wherein the organic surfactant comprises
at least one of polyethylene glycol and copolymers of ethylene
oxide-propylene oxide.
11. The method of claim 9, further comprising adding an organic
wetting agent based on non-ionic surfactants at a concentration of
between about 50 ppm and about 500 ppm.
12. The method of claim 9, further comprising adding an organic
anti-foaming agent based on non ionic surfactant at a concentration
of between about 50 ppm and about 500 ppm.
13. The method of claim 8, wherein cleaning the seed layer further
comprises: transferring the substrate to a spin rinse dry cell;
rotating the substrate at a rate of between about 400 rpm and about
1000 rpm; and dispensing deionized water onto the seed layer to
remove chemical constituents therefrom.
14. The method of claim 8, wherein positioning the seed layer in
the first and second plating solutions further comprises applying a
cathodic bias to the seed layer during the immersion process, the
cathodic bias being configured to overcome seed layer etching
caused by the plating solution.
15. The method of claim 8, wherein the second plating solution
comprises copper ions at a concentration of between about 30 g/l
and about 60 g/l, chlorine ions at a concentration of between about
20 ppm and about 100 ppm, an organic plating suppressor additive at
a concentration of between about 100 ppm and about 2000 ppm, a
leveler additive at a concentration of between about 1 ml/l to
about 10 ml/l, and a plating accelerator additive at a
concentration of between about 5 ppm and about 60 ppm.
16. The method of claim 8, wherein the second plating bias is
configured to generate a current density of between about 3
mA/cm.sup.2 and about 10 mA/cm.sup.2 across a plating surface of
the substrate.
17. The method of claim 8, wherein the first plating solution has a
conductivity of between about 5 mS/cm and about 20 mS/cm.
18. A method for plating a metal onto a discontinuous seed layer,
comprising: immersing the seed layer in a low conductivity
electrolytic plating solution having a pH of between about 1.5 and
about 3.0; applying an electrical bias to the seed layer that is
configured to generate a current density of between about 1
mA/cm.sup.2 and about 5 mA/cm.sup.2 across the seed layer; removing
the seed layer from the low conductivity electrolytic plating
solution; rinsing the seed layer of residual chemicals; immersing
the seed layer in a conductive gap fill electrolytic solution
having a pH of less than about 4; and applying a gap fill bias to
the seed layer to electrolytically fill features formed thereon,
the gap fill bias being configured to generate a current density of
between about 3 mA/cm.sup.2 and about 10 mA/cm.sup.2 across the
seed layer.
19. The method of claim 18, wherein immersing the substrate into
the low conductivity electrolytic plating solution and the
conductive gap fill solution further comprises applying a forward
immersion bias to the seed layer during the immersion, the forward
immersion bias being configured to overcome etching of the seed
layer by the solutions during immersion.
20. The method of claim 18, wherein the low conductivity
electrolytic plating solution further comprises a copper
concentration of between about 3 g/l and about 10 g/l and an acid
concentration of between about 0.1 g/l and about 2.0 g/l.
21. The method of claim 20, wherein the low conductivity
electrolytic plating solution further comprises an organic
suppressor surfactant at a concentration of between about 200 ppm
and about 2000 ppm.
22. A low conductivity electrolytic seed layer repair solution for
semiconductor processing, comprising: copper sulfate at a
concentration of between about 3 g/l and 20 g/l; acid at a
concentration of between about 0.1 g/l and 2 g/l; chlorine ions at
a concentration of between about 20 ppm and 70 ppm; and an additive
suppressor surfactant at a concentration of between about 200 ppm
and 2000 ppm.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims benefit of U.S. provisional patent
application Ser. No. 60/510,190, filed Oct. 10, 2003, which is
herein incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] Embodiments of the present invention generally relate to a
method and chemistry for electrolytically repairing a seed layer
deposited onto a semiconductor substrate.
[0004] 2. Description of the Related Art
[0005] Metallization for sub-quarter micron sized features is a
foundational technology for present and future generations of
integrated circuit manufacturing processes. In devices such as
ultra large scale integration-type devices, i.e., devices having
integrated circuits with more than a million logic gates, the
multilevel interconnects that lie at the heart of these devices are
generally formed by filling high aspect ratio interconnect features
with a conductive material (e.g., copper, gold, silver, or
aluminum). Conventionally, deposition techniques such as chemical
vapor deposition (CVD) and physical vapor deposition (PVD) have
been used to fill these interconnect features. However, as the
interconnect sizes decrease and aspect ratios increase, void-free
interconnect feature fill via conventional metallization techniques
becomes increasingly difficult via CVD and PVD techniques. As a
result thereof, plating techniques, such as electrochemical plating
(ECP) and electroless plating have emerged as viable processes for
filling sub-quarter micron sized high aspect ratio interconnect
features in integrated circuit manufacturing processes.
[0006] In an ECP process, for example, sub-quarter micron sized
high aspect ratio features formed into the surface of a substrate
(or a dielectric layer deposited thereon) may be efficiently filled
with a conductive material, such as copper. Most ECP processes are
generally two stage processes, wherein a seed layer is first formed
over the surface features of the substrate (this process may be
performed in a separate system), and then the substrate surface
features are exposed to an electrolyte solution while an electrical
bias is simultaneously applied between the substrate surface and an
anode positioned within the electrolyte solution. The electrolyte
solution is generally rich in ions to be plated onto the surface of
the substrate, and therefore, the application of the electrical
bias operates to drive a reductive reaction that reduces the metal
ions and precipitates the respective metal. Upon precipitating, the
metal plates onto the seed layer to form a film. This process may
be continued until the thickness of the layer reaches a desired
thickness.
[0007] As noted above, conventional plating practices include
depositing a copper seed layer via physical vapor deposition (PVD),
chemical vapor deposition (CVD), or atomic layer deposition (ALD)
onto a diffusion barrier layer (e.g., tantalum or tantalum
nitride). However, as the feature sizes become smaller, it becomes
extremely difficult to have adequate seed step coverage with PVD
techniques, as discontinuous islands of copper agglomerates are
often obtained close to the feature bottom in high aspect ratio
features with PVD techniques. For CVD techniques, a thick copper
layer (e.g., >200 .ANG.) over the field is generally needed to
have continuous sidewall coverage throughout the depth of high
aspect ration features, which often causes the throat of the
feature to close before the feature sidewalls are covered. As such,
CVD techniques are also prone to generating discontinuities in the
seed layer when the deposition thickness on the field is reduced to
prevent throat closure. These discontinuities in the seed layer
have been shown to cause plating defects in the layers plated over
the seed layer.
[0008] Therefore, there is a need for a method and chemistry for
electrochemically repairing discontinuities in a seed layer.
SUMMARY OF THE INVENTION
[0009] The present invention generally provides a method for
repairing discontinuities in copper seed layers formed on
substrates. The method includes using an acidic electrolytic
solution to plate a copper repair layer over copper seed layer
having discontinuities therein in a manner that operates to cover
the discontinuities. The chemistry of the invention generally
includes an electrolytic seed repair solution that has a pH of less
than about 4.
[0010] Embodiments of the invention further provide a method for
electrolytically repairing a copper seed layer. The method includes
positioning the substrate having the seed layer formed thereon in
fluid communication with a low conductivity seed layer repair
solution, which includes a copper concentration of less than about
20 g/l, a pH of less than about 4, a chlorine ion concentration of
between about 10 ppm and about 100 ppm, and an additive organic
surfactant configured to suppress a copper deposition rate. The
method further includes applying a seed layer repair bias
configured to generate a current density of less than about 5
mA/cm.sup.2 across the seed layer.
[0011] Embodiments of the invention further provide a method for
filling a semiconductor feature having a seed layer deposited
thereon with a conductive material. The method includes positioning
a substrate having a seed layer formed thereon in a first plating
solution having a pH of less than about 4 and a copper
concentration of less than about 10 g/l, applying a first plating
bias to the seed layer to plate a metal onto discontinuities in the
seed layer, the first plating bias having a first current density
across the seed layer of less than about 5 mA/cm.sup.2. The method
further includes removing the substrate from the first plating
solution, cleaning the seed layer of residual chemical constituents
from the first plating with a cleaning solution having less than
about 1 ppm of chlorine ions, positioning the seed layer in a
second plating solution, the second plating solution being
different from the first plating solution, and applying a second
plating bias to the seed layer to deposit a feature fill layer,
wherein the second plating bias is configured to generate a second
current density across the seed layer that is greater than the
first current density.
[0012] Embodiments of the invention further provide a method for
plating a metal onto a discontinuous seed layer. The method
includes repairing the discontinuous seed layer by immersing the
seed layer in a low conductivity electrolytic plating solution
having a pH of less than about 4, and applying a bias to the seed
layer that is configured to generate a current density of between
about 2 mA/cm.sup.2 and about 5 mA/cm.sup.2 across the seed layer.
The method further includes removing the seed layer from the low
conductivity electrolytic bath, rinsing the seed layer of residual
chemicals, immersing the seed layer in a conductive gap fill
electrolytic solution having a pH of between about 2 and about 6,
and applying a gap fill bias to the seed layer to electrolytically
fill features formed thereon, the gap fill bias being configured to
generate a current density of between about 5 mA/cm.sup.2 and about
40 mA/cm.sup.2.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] So that the manner in which the above recited features of
the present invention can be understood in detail, a more
particular description of the invention, briefly summarized above,
may be had by reference to embodiments, some of which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate only typical embodiments of
this invention and are therefore not to be considered limiting of
its scope, for the invention may admit to other equally effective
embodiments.
[0014] FIG. 1 illustrates a top plan view of an electrochemical
plating system capable of conducting the method of the
invention.
[0015] FIG. 2 illustrates a partial sectional and partial
perspective view of an exemplary plating cell used in the method of
the invention.
[0016] FIG. 3 illustrates a graph of the electrochemical
polarization for acidic baths for various suppressors.
[0017] FIG. 4 illustrates a graph of the effect of 1 ppm of
chlorine on suppressor post clean effectiveness.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0018] FIG. 1 illustrates a top plan view of an ECP system 100 of
the invention. ECP system 100 includes a factory interface 130,
which is also generally termed a substrate loading station. Factory
interface 130 includes a plurality of substrate loading stations
configured to interface with substrate containing cassettes 134. A
robot 132 is positioned in factory interface 130 and is configured
to access substrates contained in the cassettes 134. Further, robot
132 also extends into a link tunnel 115 that connects factory
interface 130 to processing mainframe or platform 113. The position
of robot 132 allows the robot to access substrate cassettes 134 to
retrieve substrates therefrom and then deliver the substrates to
one of the processing cells 114, 116 positioned on the mainframe
113, or alternatively, to an annealing station 135. Similarly,
robot 132 may be used to retrieve substrates from the processing
cells 114, 116 or the annealing chamber 135 after a substrate
processing sequence is complete. In this situation robot 132 may
deliver the substrate back to one of the cassettes 134 for removal
from system 100.
[0019] The processing mainframe 113 includes a substrate transfer
robot 120 centrally positioned thereon. Robot 120 generally
includes one or more arms/blades 122, 124 configured to support and
transfer substrates thereon. Additionally, the robot 120 and the
accompanying blades 122, 124 are generally configured to extend,
rotate, and vertically move so that the robot 120 may insert and
remove substrates to and from a plurality of processing locations
102, 104, 106, 108, 110, 112, 114, 116 positioned on the mainframe
113. Similarly, factory interface robot 132 also includes the
ability to rotate, extend, and vertically move its substrate
support blade(s), while also allowing for linear travel along the
robot track that extends from the factory interface 130 to the
mainframe 113. Generally, process locations 102, 104, 106, 108,
110, 112, 114, 116 may be any number of processing cells utilized
in an electrochemical plating platform. More particularly, the
process locations may be configured as electrochemical plating
cells, rinsing cells, bevel clean cells, spin rinse dry cells,
substrate surface cleaning cells (which collectively includes
cleaning, rinsing, etching, and ozone treatment cells, etc.),
electroless plating cells, metrology inspection stations, and/or
other processing cells that may be beneficially used in conjunction
with a plating platform. Each of the respective processing cells
and robots are generally in communication with a process controller
111, which may be a microprocessor-based control system configured
to receive inputs from both a user and/or various sensors
positioned on the system 100 and appropriately control the
operation of system 100 in accordance with the inputs.
[0020] In the exemplary plating system illustrated in FIG. 1, the
processing locations may be configured as follows. Processing
locations 114 and 116 may be configured as an interface between the
wet processing stations on the mainframe 113 and the dry processing
regions in the link tunnel 115, annealing chamber 135, and the
factory interface 130. The processing cells located at the
interface locations may be spin rinse dry cells and/or substrate
cleaning cells, for example. More particularly, each of locations
114 and 116 may include both a spin rinse dry cell and a substrate
cleaning cell in a stacked configuration. Locations 102, 104, 110,
and 112 may be configured as plating cells, either electrochemical
plating cells or electroless plating cells, for example. Locations
106, 108 may be configured as substrate bevel cleaning cells.
Additional configurations and implementations of an electrochemical
processing system are illustrated in commonly assigned U.S. patent
application Ser. No. 10/435,121 filed on Dec. 19, 2002 entitled
"Multi-Chemistry Electrochemical Processing System", which is
incorporated herein by reference in its entirety. Regardless of the
configuration of the respective plating cells, ECP system 100 is
generally configured to provide multiple plating cells on a single
platform, wherein each of the multiple plating cells is capable of
having a different chemistry therein from each of the other plating
cells on the platform.
[0021] FIG. 2 illustrates a partial perspective and sectional view
of an exemplary plating cell 200 that may be implemented in
processing locations 102, 104, 110, and 112 (or other processing
locations on system 100 as desired). The electrochemical plating
cell 200 generally includes an outer basin 201 and an inner basin
202 positioned within outer basin 201. Inner basin 202 is generally
configured to contain a plating solution that is used to plate a
metal, e.g., copper, onto a substrate during an electrochemical
plating process. During the plating process, the plating solution
is generally continuously supplied to inner basin 202, and
therefore, the plating solution continually overflows the uppermost
point (generally termed a "weir") of inner basin 202 and is
collected by outer basin 201 and drained therefrom for chemical
management and/or recirculation.
[0022] Plating cell 200 is generally positioned at a tilt angle,
i.e., a frame portion 203 of plating cell 200 is generally elevated
on one side such that the components of plating cell 200 are tilted
between about 3.degree. and about 300 from horizontal, or generally
between about 4.degree. and about 10.degree.. The frame member 203
of plating cell 200 supports an annular base member 204 on an upper
portion thereof, and since frame member 203 is elevated on one
side, the upper surface of base member 204 is generally tilted from
the horizontal at an angle that corresponds to the tilt angle of
frame member 203 relative to a horizontal position.
[0023] Base member 204 includes an annular or disk shaped recess
formed into a central portion thereof, the annular recess being
configured to receive a disk shaped anode member 205. Base member
204 further includes a plurality of fluid inlets/drains 209
extending from a lower surface thereof. Each of the fluid
inlets/drains 209 are generally configured to individually supply
or drain a fluid to or from either the anode compartment or the
cathode compartment of plating cell 200. Anode member 205 generally
includes a plurality of slots 207 formed therethrough, wherein the
slots 207 are generally positioned in parallel orientation with
each other across the surface of the anode 205. The parallel
orientation allows for dense fluids generated at the anode surface
to flow downwardly across the anode surface and into one of the
slots 207.
[0024] Plating cell 200 further includes a membrane support
assembly 206. Membrane support assembly 206 is generally secured at
an outer periphery thereof to base member 204, and includes an
interior region configured to allow fluids to pass therethrough. A
membrane 208, which may be a cationic membrane, is stretched across
the support 206 and operates to fluidly separate a catholyte
chamber (positioned adjacent the substrate being plated) and
anolyte chamber (positioned adjacent the anode electrode in the
cell) of the plating cell. The membrane support assembly 206 may
include an o-ring type seal positioned near a perimeter of the
membrane 208, wherein the seal is configured to prevent fluids from
traveling from one side of the membrane 208 secured on the membrane
support 206 to the other side of the membrane 208.
[0025] A diffusion plate 210, which is generally a porous ceramic
disk member is configured to generate a substantially laminar flow
or even flow of fluid in the direction of the substrate being
plated, is positioned in the cell between membrane 208 and the
substrate being plated. The diffusion plate 210 is generally
manufactured from an electrically insulating material, and as such,
the diffusion plate 210 also operates to control the electric field
generated between the anode and the substrate. Embodiments of the
invention are not limited to ceramic diffusion members, as other
electrically insulative porous materials that are non-reactive with
electrochemical processing fluid may also be used. Additionally,
embodiments of the invention further contemplate that electrically
insulative materials that are not porous may be used, as holes or
bores may be formed therein to allow fluid to flow
therethrough.
[0026] The exemplary plating cell and the components thereof are
further illustrated in commonly assigned U.S. patent application
Ser. No. 10/268,284, which was filed on Oct. 9, 2002 under the
title "Electrochemical Processing Cell", claiming priority to U.S.
Provisional Application Ser. No. 60/398,345, which was filed on
Jul. 24, 2002, both of which are incorporated herein by reference
in their entireties. Additional embodiments of the plating cell are
discussed in commonly assigned U.S. patent application Ser. No.
10/627,336, filed on Jul. 24, 2003, entitled "Electrochemical
Processing Cell", which is also incorporated by reference herein in
its entirety.
[0027] In operation, ECP system 100 and plating cell 200 may be
used to electrolytically fill high aspect ratio features with a
conductive metal. More particularly, ECP system 100 and plating
cell 200 may be used to electrolytically repair or patch a seed
layer deposited onto a substrate having high aspect ratio features
thereon in a first electrolytic bath. Thereafter, ECP system 100
and plating cell 200 may be used to electrolytically plate a
conductive layer over the repaired or patched seed layer to fill
the high aspect ratio features in a second electrolytic bath,
wherein the first electrolytic bath is different from the first
electrolytic bath. As noted above, the seed layer (and generally an
underlying barrier layer) is generally deposited in a separate
deposition apparatus, such as a PVD or CVD system.
[0028] The process of repairing the seed layer and filling the
features generally begins with a substrate immersion process. The
immersion process includes securing the substrate to be plated to a
cathode electrode, often termed a contact ring, for processing.
Exemplary contact rings are illustrated in commonly assigned U.S.
Pat. No. 6,251,236, entitled "Cathode Contact Ring for
Electrochemical Deposition", and commonly assigned U.S. patent
application Ser. No. 10/278,527, entitled "Plating Uniformity
Control by Contact Ring Shaping" filed on Oct. 22, 2002, both of
which are hereby incorporated by reference in their entirety. The
substrate is secured to the contact ring such that a seed layer
deposited on the substrate is in electrical contact with the
electrical contact elements or pins of the contact ring. Once the
substrate is secured to the contact ring, the substrate is immersed
into a first electrolytic plating solution contained in a plating
cell, wherein the first electrolytic plating solution is configured
as a seed repair plating solution. The process of immersing the
substrate into the plating solution generally includes rotating,
tilting, and/or vertically actuating the contact ring having the
substrate secured thereto into the plating solution, as described
in commonly assigned U.S. patent application Ser. No. 10/266,477,
entitled "Tilted Electrochemical Plating Cell With Constant Wafer
Immersion Angle", filed on Oct. 7, 2002 and commonly assigned U.S.
Provisional Patent Application Ser. No. 60/448,575, entitled "Wafer
Immersion Mechanism", filed on Feb. 18, 2003, both of which are
hereby incorporated by reference in their entirety. The process of
immersing the substrate into the electrolytic solution may also
include applying an immersion bias to the substrate, as acidic
electrolytic solutions have been shown to etch seed layers, thus
compounding the problem of discontinuities in the seed layer. The
immersion bias will generally be a forward or plating bias that is
configured to overcome the etching effect of acidic solutions
during the immersion process. The process of supplying and
controlling an immersion bias is described in commonly assigned
U.S. patent application Ser. No. 10/135,546, entitled "Apparatus
and Method for Regulating the Electrical Power Applied to a
Substrate During Immersion", filed on Apr. 29, 2002.
[0029] Once the substrate is immersed in the seed repair solution,
a plating bias is generally applied to the substrate. The plating
bias is configured to drive a reduction reaction between the anode
of the plating cell, which is in electrical communication with the
anodic terminal of the power supply, and the cathode contact ring,
which is in electrical communication with the seed layer on the
substrate. The reduction reaction causes metal ions in the
electrolytic solution (the seed repair solution) to plate onto the
substrate. However, in order to facilitate plating on the
discontinuous areas of the seed layer, i.e., the void areas that
generally reside on the sidewalls of high aspect ratio features, a
low conductivity acidic seed layer repair solution is utilized.
More particularly, in order to facilitate an electrolytic copper
seed layer repair process, the acidic seed layer repair electrolyte
solution includes a low conductivity copper sulfate solution having
a pH of less than or equal to about 4, and a copper concentration
of less than or equal to about 20 g/l. Further, the pH may be
between about 1.5 and about 4, between about 1.5 and about 3,
between about 1 and about 2.5, or between about 1.5 and about 2.5,
for example, for this embodiment, along with the other embodiments
of the invention. As noted below, solutions having a pH of greater
than about 4 tend to generate unwanted precipitates, and as such,
they are not preferred for the seed layer repair solution. The
inventors have found that these concentrations are capable of
uniform copper deposition current distribution inside micro
recessed high aspect ratio features. The current density applied to
the substrate during the seed repair process is generally between 1
mA/cm.sup.2 and about 5 mA/cm.sup.2, for example, and the repair
process generally has a duration of between about 6.0 seconds and
about 55 seconds to ensure about a 100 to about a 200 angstrom
thick repair layer. More preferably, the current density is between
about 1 mA/cm2 and about 3 mA/cm2, and the duration is between
about 9 and about 42 seconds to ensure a 100-150 angstrom thick
repair layer. The conductivity of the plating solution containing
about 5 g/l Cu and about X g/l of H.sub.2SO.sub.4 at room
temperature have been measured. The conductivity, Y in units of
milli Siemens per centimeter, can be expressed as a function of the
H.sub.2SO.sub.4 concentration X as follows: Y=3.859 X+6.874, where
the H.sub.2SO.sub.4 concentration is in the range of between about
0 and about 1 g/l. Further, the addition of 50 ppm Cl and the
suppressor in the concentration range of interest does not change
the solution electrical conductivity.
[0030] In another embodiment of the invention, the seed repair
solution additionally includes a particular concentration of
suppressor molecules, along with between about loppm and about 100
ppm of chlorine ions, which operates to maximize electrochemical
polarization and obtain a fine grained smooth deposited seed layer
repair layer. The class of suppressors capable of supporting this
process includes polyethylene glycol having a molecular weight of
greater than about 600, and copolymers of ethylene oxide-propylene
oxide, and their derivatives having a molecular weight of greater
than about 1000. The concentration of the suppressor in the seed
repair solution is generally between about 100 mg/l and about 2000
mg/l, for example.
[0031] The seed layer repair solutions of the invention are
generally formulated to facilitate copper deposition along the
entire sidewall of high aspect ratio features via a more uniform
current distribution that is achieved by reducing the copper and
acid concentrations in the seed repair solution. For example, the
inventors have tested a plating solution containing approximately
5-10 g/l of copper, 0.5 g/l of acid (thus generating a pH of about
2.30), about 50 ppm of chlorine+ions, and an additive suppressor
compound. Implementation of this plating solution in a seed layer
repair plating process wherein a current density of less than about
5 mA/cm.sup.2 was applied for less than about 55 seconds provided
complete sidewall coverage and a smooth continuous copper layer
over the interior surfaces of the features when viewed on a
micrograph and compared to a similar sample processed under similar
conditions without the seed layer repair process. Additionally, the
acidic seed layer repair solution provided improved results over
conventional alkaline seed layer repair solutions, and further,
eliminated the requirement for additional safety precautions, e.g.,
acidic neutralization chemicals, that are necessary when working
with alkaline based plating solutions. Further still, since acidic
plating solutions are generally used for gap fill solutions, the
acidic seed layer repair solution required no additional chemical
management tools or processes, as the same constituents are used in
the seed layer repair solution, only in different concentrations.
Additionally, in a similar test using similar processing
parameters, a plating solution containing about 5 g/l of copper,
acid sufficient to generate a pH of about 3.1, about 50 ppm of
chlorine ions, and an additive suppressor was used under similar
processing conditions, and similar results were obtained, i.e.,
complete sidewall coverage and a smooth continuous copper layer
over the interior surfaces of the features when viewed on a
micrograph.
[0032] Further, with regard to the use of suppressor chemistry
noted above, it is generally known that the copper deposition rate
in acidic solutions occurs at a relative fast rate as a result of
the high exchange current density provided by the acidic bath.
Further, deposition from acidic baths without organic additives to
suppress the copper growth rate are known to be overly rough for
semiconductor processing applications involving high aspect ratio
features. Therefore, in order for the acidic seed layer repair
solutions noted above to be effective, i.e., to provide acceptable
plating rates, smoothness, and coverage in high aspect ratio
features, the addition of organic surfactants configured to
suppress the copper deposition rate is generally required. The
effectiveness of the surfactants in the acidic solution are
evidenced by the electrochemical polarization characteristics
illustrated in FIG. 3, which is a plot of the Cu deposition current
vs. Cu deposition potential, wherein the negative sign for the
current/potential indicates that both the current and the potential
are cathodic. Higher cathodic polarization (more negative potential
corresponding to any particular deposition current) will improve
the deposition smoothness by increasing the Cu nucleation rate
through over saturation of Cu ions. The addition of suppressor
molecules, such as PEG (polyethylene glycol) and EO (ethylene
oxide)/PO (propylene oxide) co-polymer molecules, has been shown to
significantly shift the Cu deposition potential cathodically as
compared to the make-up plating solution containing no additives.
Therefore, suppressor addition will significantly improve the Cu
deposit smoothness. The degree of improvement depends on the
suppressor molecular nature. For example, increasing the molecular
weight from between about 600 and about 2000, or more particularly,
between about 600 and about 1000, has been shown to further
increase the cathodic polarization, and hence the deposit
smoothness. Also, EO/PO co-polymers with different EO/PO
percentages and molecular arrangements provide even stronger
cathodic polarization than PEG molecules, so they are also
candidates as suitable suppressors. Exemplary suppressors that may
be used in the acidic seed layer repair solution of the invention
include polyethylene glycol, copolymers of ethylene oxide-propylene
oxide, and any derivatives of the above molecules.
[0033] Once the seed layer repair step or layer has been deposited,
the substrate is removed from the plating cell. The substrate is
then transferred to a second plating cell for subsequent
processing, which generally includes another electrochemical
plating process that is configured to completely fill the features
on the substrate. The second plating cell generally contains a
second plating solution, which is generally termed a gap fill
solution. The gap fill solution is generally different from the
seed layer repair solution, and more particularly, the gap fill
solution generally includes additional plating additives therein,
e.g., levelers and accelerators.
[0034] However, since the gap fill solution contains different
chemical constituents than the seed repair solution, the substrate
is generally cleaned between the seed repair plating process and
the gap fill plating process, as constituents from the seed repair
plating solution may adhere to the substrate surface when it is
removed from the seed repair plating cell and subsequently
contaminate the gap fill plating solution. The substrate cleaning
process may generally include transferring the substrate from the
seed repair plating cell to one of the spin rinse dry (SRD) cells
of the ECP system 100. Once the substrate is positioned in the SRD
a rinsing solution, such as deionized water, may be dispensed onto
the substrate surface to remove any remaining seed layer repair
chemical constituents from the surface of the substrate.
[0035] Additionally, the process of cleaning the substrate between
the seed layer repair and gap fill plating steps may further
include applying agitation to the substrate to facilitate cleaning.
The agitation may be sonic, ultra sonic, or megasonic, for example.
Further, in order to facilitate optimal removal of the seed layer
repair chemical constituents from the surface of the substrate, the
rinsing solution, which may be deionized water, for example,
generally contains less than about 1 ppm or less than about 1 mg/l
of chlorine. The lack of chlorine from the rinsing or cleaning
solution is important to the operation of the invention, as
chlorine concentrations greater than about 1 ppm in the rinsing
solution have been shown to make removal of the suppressor used in
the seed repair bath from the substrate surface difficult, which
results in challenges to void free gap fill, as the presence of the
residual suppressors prevents proper filling.
[0036] For example, FIG. 4 illustrates the effect of 1 ppm of
chlorine in the suppressor post clean effectiveness. The suppressor
residual on the plated wafer surface is simulated by soaking the
plated Cu film on top of a platinum disk electrode (hereafter
called Cu disk electrode) in the seed repair solution for 30
seconds. The treated Cu disk electrode is then cleaned in
post-seed-repair cleaning solutions. The effectiveness of the
cleaning process is checked by performing a polarization study in a
plating solution containing no organic additives. The presence or
absence of residual suppressors after cleaning can be seen by the
magnitude of Cu plating current during cathodic deposition. The
polarization curve on a clean Cu disk electrode that is not soaked
in the post-seed-repair solution is plotted (bottom curve) as
reference, this curve exhibits the typical behavior of Cu
deposition in the absence of any organic additives.
[0037] The top curve in FIG. 4 represents a polarization curve
taken immediately following the soaking of the Cu disk electrode in
post-seed-repair solution. Very strong suppression of Cu deposition
current due to suppressor residual on Cu disk electrode is
illustrated by this curve. Additionally, the degree of current
suppression exerted by the surface suppressor residual is
comparable to the suppression provided by the suppressor molecules
in the seed repair solution. The remaining three polarization
curves between the top and bottom curves were obtained after
cleaning the surface suppressor residual in the post-seed-repair
solutions containing 1 ppm chloride ion for a time period from 60
seconds to 240 seconds. It is apparent that a large part of the
residual suppressor still remains on the Cu disk electrode surface
even after 240 seconds of cleaning, and the residual amount was not
further reduced by increasing the cleaning time from 120 seconds to
240 seconds. Therefore, it can be concluded that the presence of
even 1 ppm chloride ion in the cleaning solution will prevent the
effective removal of suppressor residual on the wafer surface.
Further, the rinsing solution generally contains no organic
solvents, such as alcohol or acetone, for the same reasons the
solution does not contain chlorine.
[0038] Once the substrate is cleaned of the remaining surface
organics, then the substrate may be processed in a gap fill plating
solution. The gap fill plating solution is generally contained in a
plating cell that is different or separate from the plating cell
containing the seed layer repair solution. In the gap fill cell, an
acidic plating solution is generally used to plate copper into the
features to fill the features without generating interior voids in
the fill layer. The gap fill solution may include between about 30
and about 60 g/l of Cu, between about 5 and about 100 g/l of acid,
between about 20 and about 100 ppm of Cl ions, between about 5 and
about 30 ppm of an additive accelerator, between about 100 and
about 1000 ppm of an additive suppressor, and between about 1 and
about 6 ml/l of an additive leveler. A general duration for a
gapfill process is in the range of between about 10 and about 50
seconds using a plating current density of about 5 mA/cm.sup.2,
however, the inventors note that the gapfill duration may be
decreased if the plating process can be conducted at higher plating
rates without sacrificing fill or defect parameters.
[0039] Once the gap fill process has been completed, the substrate
may be removed from the gap fill plating cell and transferred to
another cell on ECP system 100 for further processing. Additional
processing steps include, for example, but are not limited to an
additional bulk plating step, an edge bead removal process, a spin
rinse dry process, a surface clean process, and/or an annealing
process. Once the post-plating processes are completed, the
substrate may be transferred out of ECP system 100 via robots 120,
132 and into substrate cassettes 134.
[0040] The seed layer repair process of the invention is generally
three step process in nature. The first fundamental step is wafer
immersion into the repair solution, where two important
requirements must be met. First, the wafer must be protected
against corrosion, and therefore, a cathodic potential bias must be
applied, and the potential should be such that the cathodic current
density is greater than or equal to about 1 mA/cm.sup.2. In
addition, accelerators should not be present in the repair solution
since accelerators induce Cu corrosion. Further, the lower limit
for the suppressor concentration should be high enough to ensure
that the repair solution possesses high enough anti-corrosion
capability. Second, the repair solution should not generate
excessive gas bubbles upon wafer immersion. Since the bubble
generation tendency generally increases with higher suppressor
concentrations, the suppressor concentration should be limited in
order to minimize plating defects.
[0041] The method or process of the invention also generally
includes a two step plating process, wherein the first step is a
seed layer repair step (as discussed above) and the second step is
a feature fill step. The repair and fill steps are generally
conducted in separate plating cells using separate and different
plating solutions and processing parameters. The method of the
invention generally includes providing a substrate having a seed
layer thereon to a first plating cell. The substrate provided to
the cell is generally a clean dry substrate with minimal oxidation
of the seed layer. Alternatively, the substrate provided to the
first plating cell may be treated with a pre-seed layer repair
solution, such as a solution configured to improve the wetability
of the substrate or a plating solution additive configured to
promote the seed layer repair process.
[0042] The electrochemical plating solution used in the seed layer
repair process, as described above, generally includes a copper
source, an acid source, a chlorine ion source, and at least one
plating solution additive, i.e., levelers, suppressors,
accelerators, antifoaming agents, etc. Specifically, the repair
solution may contain the following constituents: copper (between
about 5 and about 20 g/l, preferably between about 5 and about 10
g/l), an acid (between about 0.1 and about 5 g/l, preferably
between about 0.1 and about 1.0 g/l), a chlorine ion source
(between about 20 and about 100 ppm, preferably between about 20
and about 50 ppm), and an additive suppressor (between about 100
and about2000 ppm for PEG, EO/PO co-polymers, and their
derivatives. The lower limit imposed by effective suppression
during seed repair, and the upper limit imposed by bubble
generation in the seed-repair solution that can generate voids for
the repair layer). The solution generally does not contain any
leveler or accelerators. The accelerator is generally avoided as it
does not provide adequate seed layer protection against corrosion
that can be achieved during wafer immersion in the presence of
accelerators. Only strong suppressors or their combination with
levelers can provide the needed seed protection before repair.
[0043] The repair process begins with the substrate being
positioned in the first plating cell and in contact with the
plating solution (the seed layer repair solution). A seed layer
repair plating or forward bias, generally between about 1 mA/cm2
and about 3 mA/cm2 is applied to the seed layer for a duration of
between about 9 seconds and about 55 seconds. Although higher
current densities are known to plate faster, higher current
densities do not facilitate seed layer repair processes. As such,
lower current densities are preferred. The lower current density
limit of the seed layer repair plating process is generally imposed
by a throughput requirement, i.e., although lower current densities
are available, the lower limit is about as low as the process can
go while maintaining acceptable commercial throughput. Further,
although higher current densities are preferred, the upper limit of
the seed layer repair process is generally imposed by the
minimization of seed overhang. The duration of the repair process
is generally determined by the repair layer thickness and the
current density, i.e., the repair layer thickness generally needs
to be greater than 200 .ANG. for the subsequent gapfill and it
needs to be greater than 100 .ANG. to get continuous smooth repair
layer. Further still, the substrate support member and the
substrate being plated will generally be rotated during the seed
layer repair process at a rate of between about 5 rpm and about 100
rpm. The temperature of the substrate during the plating process is
generally between about 10.degree. C. and about 80.degree. C.
[0044] Another fundamental step in the seed layer repair process of
the invention is the post-seed-repair cleaning to remove the
residual additives on wafer surface. Generally, the only additive
in the repair solution is the suppressor molecule, so the inventors
have demonstrated how the suppressor residual can be removed and
how the presence of trace amount of chloride ions prevents the
effective cleaning. Because it is almost impossible to fully remove
the leveler species from the surface, the inventors have determined
that the use of levelers in the repair solution should be avoided,
even though the levelers can further enhance the anti-corrosion
capability of the repair solution. The only category of organic
additives the inventors believe can be effectively added into the
repair solutions is the non-ionic surfactant molecules like the
suppressors, the wetting agents, and the anti-foaming agents.
Wetting agents and anti-foaming agents will also act as secondary
suppressors in addition to improving the solution wetting to wafer
and reducing the occurrence of gas bubbles during wafer immersion.
Generally, wetting agents and anti-foaming agents are based on
non-ionic surfactants are legitimate candidates. Due to the weak
interaction of the non-ionic surfactants with Cu surface, these
additives can be removed from the Cu surface after the repair step
is completed with the cleaning method discussed above.
[0045] Once the repair and substrate cleaning process has been
completed, the substrate may be transferred to a second plating
cell where subsequent plating processes may be conducted thereon.
More particularly, the second plating cell may be configured with
both chemistry and processing parameters to facilitate a gap fill
plating process or a bulk fill plating process, for example.
[0046] While the foregoing is directed to embodiments of the
present invention, other and further embodiments of the invention
may be devised without departing from the basic scope thereof, and
the scope thereof is determined by the claims that follow.
* * * * *