U.S. patent application number 11/008654 was filed with the patent office on 2005-05-19 for use of palladium in ic manufacturing with conductive polymer bump.
Invention is credited to Akram, Salman, Farnworth, Warren M..
Application Number | 20050104210 11/008654 |
Document ID | / |
Family ID | 26921132 |
Filed Date | 2005-05-19 |
United States Patent
Application |
20050104210 |
Kind Code |
A1 |
Farnworth, Warren M. ; et
al. |
May 19, 2005 |
Use of palladium in IC manufacturing with conductive polymer
bump
Abstract
An apparatus and a method for forming a substrate having a
palladium metal layer over at least one contact point of the
substrate and having a flexible conductive polymer bump, preferably
a two-stage epoxy, on the palladium plated contact point. The
present invention also relates to assemblies comprising one or more
of these substrates.
Inventors: |
Farnworth, Warren M.;
(Nampa, ID) ; Akram, Salman; (Boise, ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
26921132 |
Appl. No.: |
11/008654 |
Filed: |
December 9, 2004 |
Related U.S. Patent Documents
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Application
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Filing Date |
Patent Number |
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11008654 |
Dec 9, 2004 |
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10430616 |
May 5, 2003 |
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10430616 |
May 5, 2003 |
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10116962 |
Apr 5, 2002 |
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6558979 |
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10116962 |
Apr 5, 2002 |
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09645947 |
Aug 25, 2000 |
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6413862 |
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09645947 |
Aug 25, 2000 |
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09227072 |
Jan 5, 1999 |
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6159769 |
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09227072 |
Jan 5, 1999 |
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08651816 |
May 21, 1996 |
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5925930 |
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Current U.S.
Class: |
257/737 ;
257/768; 257/E21.174; 257/E21.503; 257/E21.508; 257/E21.511;
257/E21.514; 257/E23.021; 257/E23.069; 438/613; 438/648 |
Current CPC
Class: |
H01L 2924/014 20130101;
H01L 2924/0665 20130101; H01L 2924/14 20130101; H01L 21/4853
20130101; H01L 2224/13111 20130101; H01L 2924/00014 20130101; H01L
2924/0105 20130101; H01L 2224/12 20130101; H01L 21/288 20130101;
H01L 24/11 20130101; H01L 2224/29101 20130101; H01L 2224/29298
20130101; H01L 2924/01047 20130101; H01L 2924/01079 20130101; H01L
24/29 20130101; H01L 2224/29111 20130101; H01L 2224/11 20130101;
H01L 2924/00013 20130101; H01L 2924/01013 20130101; H01L 2924/01046
20130101; H01L 2924/01082 20130101; H01L 2224/05001 20130101; H01L
24/03 20130101; H01L 2924/01033 20130101; H01L 2924/01078 20130101;
H05K 2201/10674 20130101; H01L 2224/05571 20130101; H01L 24/05
20130101; H01L 24/83 20130101; H01L 24/16 20130101; H01L 2924/12044
20130101; H01L 2224/05572 20130101; H01L 2224/2919 20130101; H01L
2224/8319 20130101; H05K 3/321 20130101; H01L 2224/16225 20130101;
H01L 2924/01029 20130101; H01L 2224/05023 20130101; H01L 2224/05568
20130101; H01L 2224/1319 20130101; H01L 2224/1132 20130101; H01L
2224/73204 20130101; H01L 2924/01005 20130101; H01L 21/563
20130101; H01L 2924/0132 20130101; H01L 23/49816 20130101; H01L
23/49894 20130101; H01L 2224/13099 20130101; H01L 24/81 20130101;
H01L 2224/81801 20130101; H01L 2924/01074 20130101; H01L 23/49811
20130101; H01L 2924/0781 20130101; H01L 2224/05022 20130101; H01L
24/12 20130101; H01L 2224/16 20130101; H01L 2224/838 20130101; H05K
2201/10977 20130101; H01L 2224/73203 20130101; H05K 3/244 20130101;
H05K 2201/10984 20130101; H01L 2924/0665 20130101; H01L 2924/00
20130101; H01L 2224/29101 20130101; H01L 2924/014 20130101; H01L
2924/00 20130101; H01L 2924/0132 20130101; H01L 2924/0105 20130101;
H01L 2924/01082 20130101; H01L 2924/3512 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 2224/2919 20130101; H01L
2924/00014 20130101; H01L 2224/13111 20130101; H01L 2924/01082
20130101; H01L 2924/00014 20130101; H01L 2924/00013 20130101; H01L
2224/29099 20130101; H01L 2924/00013 20130101; H01L 2224/29199
20130101; H01L 2924/00013 20130101; H01L 2224/29299 20130101; H01L
2924/00013 20130101; H01L 2224/2929 20130101; H01L 2924/00014
20130101; H01L 2224/05599 20130101; H01L 2224/05164 20130101; H01L
2924/00014 20130101; H01L 2924/3512 20130101; H01L 2924/00
20130101; H01L 2224/11 20130101; H01L 2924/00012 20130101; H01L
2224/12 20130101; H01L 2924/00012 20130101; H01L 2224/16 20130101;
H01L 2924/00012 20130101 |
Class at
Publication: |
257/737 ;
438/613; 257/768; 438/648 |
International
Class: |
H01L 021/44; H01L
023/48 |
Claims
1. A method for forming a semiconductor assembly having a plurality
of substrates, each substrate having at least one conductive
electrode, comprising: applying a layer of palladium on a portion
of the at least one conductive electrode of one substrate of the
plurality of substrates; and disposing a two-stage conductive
polymer bump between a portion of the at least one conductive
electrode having the layer of palladium thereon of the one
substrate of the plurality of substrates and a portion of the at
least one conductive electrode of another substrate of the
plurality of substrates for forming an electrical contact
therebetween.
2. The method of claim 1, wherein disposing a two-stage conductive
polymer bump comprises disposing a two-stage conductive polymer
bump including palladium therein on a portion of the layer of
palladium.
3. The method of claim 1, further comprising: applying a
passivation layer over a portion of a surface of the one substrate
of the plurality of substrates having the at least one conductive
electrode.
4. The method of claim 3, further comprising: etching a portion of
the passivation layer to expose a portion of the at least one
conductive electrode.
5. The method of claim 1, wherein disposing a two-stage conductive
polymer bump comprises disposing a two-stage epoxy bump on a
portion of layer of palladium.
6. The method of claim 1, wherein applying the layer of palladium
on a portion of the at least one conductive electrode of the one
substrate comprises: immersing the one substrate of the plurality
of substrates in an electroless plating solution containing
palladium dispersed therein.
7. The method of claim 1, wherein disposing a two-stage conductive
polymer bump comprises applying a layer of a polymer with a silk
screen to form the two-stage conductive polymer bump.
8. The method of claim 1, wherein disposing a two-stage conductive
polymer bump comprises applying multiple layers of a polymer with a
silk screen to form the two-stage conductive polymer bump.
9. The method of claim 1, wherein the one substrate of the
plurality of substrates comprises a silicon wafer.
10. The method of claim 1, wherein the one substrate of the
plurality of substrates comprises a printed circuit board.
11. The method of claim 1, wherein the one substrate of the
plurality of substrates comprises a semiconductor die having the at
least one conductive electrode comprising at least one bond
pad.
12. A method for forming a bump on a substrate for a semiconductor
assembly having a plurality of substrates, each substrate having at
least one conductive electrode, comprising: applying a layer of
palladium on a portion of the at least one conductive electrode of
one substrate of the plurality of substrates; and disposing a
two-stage conductive polymer bump between a portion of the at least
one conductive electrode having the layer of palladium thereon of
the one substrate of the plurality of substrates and a portion of
the at least one conductive electrode of another substrate of the
plurality of substrates for forming an electrical contact
therebetween.
13. The method of claim 12, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage conductive
polymer bump including palladium therein on a portion of the layer
of palladium.
14. The method of claim 12, further comprising: applying a
passivation layer over a portion of a surface of the one substrate
of the plurality of substrates having the at least one conductive
electrode.
15. The method of claim 14, further comprising: etching a portion
of the passivation layer to expose a portion of the at least one
conductive electrode.
16. The method of claim 12, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage epoxy bump
on a portion of the layer of palladium.
17. The method of claim 12, wherein applying the layer of palladium
on a portion of the at least one conductive electrode of the one
substrate comprises: immersing the one substrate of the plurality
of substrates in an electroless plating solution containing
palladium dispersed therein.
18. The method of claim 12, wherein disposing a two-stage
conductive polymer bump comprises applying a layer of a polymer
with a silk screen to form the two-stage conductive polymer
bump.
19. The method of claim 12, wherein disposing a two-stage
conductive polymer bump comprises applying multiple layers of a
polymer with a silk screen to form the two-stage conductive polymer
bump.
20. The method of claim 12, wherein the one substrate of the
plurality of substrates comprises a silicon wafer.
21. The method of claim 12, wherein the one substrate of the
plurality of substrates comprises a printed circuit board.
22. The method of claim 12, wherein the one substrate of the
plurality of substrates comprises a semiconductor die having the at
least one conductive electrode comprising at least one bond
pad.
23. A method for forming a bump on a bond pad of a semiconductor
assembly having a plurality of substrates, each substrate having at
least one conductive electrode having a bond pad, comprising:
applying a layer of palladium on a portion of the at least one
conductive electrode of one substrate of the plurality of
substrates; and disposing a two-stage conductive polymer bump
between a portion of the at least one conductive electrode having
the layer of palladium thereon of the one substrate of the
plurality of substrates and a portion of the at least one
conductive electrode of another substrate of the plurality of
substrates for forming an electrical contact therebetween.
24. The method of claim 23, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage conductive
polymer bump including palladium therein on a portion of the layer
of palladium.
25. The method of claim 23, further comprising: applying a
passivation layer over a portion of a surface of the one substrate
of the plurality of substrates having the at least one conductive
electrode.
26. The method of claim 25, further comprising: etching a portion
of the passivation layer to expose a portion of the at least one
conductive electrode.
27. The method of claim 23, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage epoxy bump
on a portion of the layer of palladium.
28. The method of claim 23, wherein applying the layer of palladium
on a portion of the at least one conductive electrode of the one
substrate comprises: immersing the one substrate of the plurality
of substrates in an electroless plating solution containing
palladium dispersed therein.
29. The method of claim 23, wherein disposing a two-stage
conductive polymer bump comprises applying a layer of a polymer
with a silk screen to form the two-stage conductive polymer
bump.
30. The method of claim 23, wherein disposing a two-stage
conductive polymer bump comprises applying multiple layers of a
polymer with a silk screen to form the two-stage conductive polymer
bump.
31. The method of claim 23, wherein the one substrate of the
plurality of substrates comprises a silicon wafer.
32. The method of claim 23, wherein the one substrate of the
plurality of substrates comprises a printed circuit board.
33. The method of claim 23, wherein the one substrate of the
plurality of substrates comprises a semiconductor die having the at
least one conductive electrode comprising at least one bond
pad.
34. A method for forming a semiconductor assembly having a
plurality of substrates, each substrate having at least one
conductive electrode having a pad, comprising: applying a layer of
palladium on a portion of the pad of the at least one conductive
electrode of one substrate of the plurality of substrates; and
disposing a two-stage conductive polymer bump between a portion of
the pad of the at least one conductive electrode having the layer
of palladium thereon of the one substrate of the plurality of
substrates and a portion of the pad of the at least one conductive
electrode of another substrate of the plurality of substrates for
forming an electrical contact therebetween.
35. The method of claim 34, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage conductive
polymer bump including palladium therein on a portion of the layer
of palladium.
36. The method of claim 34, further comprising: applying a
passivation layer over a portion of a surface of the one substrate
of the plurality of substrates having the pad of the at least one
conductive electrode.
37. The method of claim 36, further comprising: etching a portion
of the passivation layer to expose a portion the pad of the at
least one conductive electrode.
38. The method of claim 34, wherein disposing a two-stage
conductive polymer bump comprises disposing a two-stage epoxy bump
on a portion of the layer of palladium.
39. The method of claim 34, wherein applying the layer of palladium
on a portion of the pad of the at least one conductive electrode of
the one substrate comprises: immersing the one substrate of the
plurality of substrates in an electroless plating solution
containing palladium dispersed therein.
40. The method of claim 34, wherein disposing a two-stage
conductive polymer bump comprises applying a layer of a polymer
with a silk screen to form the two-stage conductive polymer
bump.
41. The method of claim 34, wherein disposing a two-stage
conductive polymer bump comprises applying multiple layers of a
polymer with a silk screen to form the two-stage conductive polymer
bump.
42. The method of claim 34, wherein the one substrate of the
plurality of substrates comprises a silicon wafer.
43. The method of claim 34, wherein the one substrate of the
plurality of substrates comprises a printed circuit board.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
10/430,616, filed May 5, 2003, pending, which is a continuation of
application Ser. No. 10/116,962, filed Apr. 5, 2002, now U.S. Pat.
No. 6,558,979, issued May 6, 2003, which is a continuation of
application Ser. No. 09/645,947, filed Aug. 25, 2000, now U.S. Pat.
No. 6,413,862, issued Jul. 2, 2002, which is a continuation of
application Ser. No. 09/227,072, filed Jan. 5, 1999, now U.S. Pat.
No. 6,159,769, issued Dec. 12, 2000, which is a divisional of
application Ser. No. 08/651,816, filed May 21, 1996, now U.S. Pat.
No. 5,925,930, issued Jul. 20, 1999.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to an apparatus and a method
for forming a conductive polymer bump on a substrate, such as a
flip-chip type semiconductor die, a silicon wafer, a printed
circuit board, or other substrate (hereinafter referred to
generally as a "substrate"). More particularly, the present
invention relates to forming a substrate having a palladium metal
layer over each contact point of the substrate and forming a
flexible conductive polymer bump on each contact point. The present
invention also relates to assemblies and methods of connecting one
or more of these substrates together or to another substrate.
[0004] 2. State of the Art
[0005] A flip chip is a semiconductor chip or die that has bumped
terminations spaced around an active surface of the die and is
intended for face-to-face attachment to a substrate or another
semiconductor die. The bumped terminations of the flip chips are
usually a "Ball Grid Array" ("BGA") configuration wherein an array
of minute solder balls is disposed on an attachment surface of a
semiconductor die, or a "Slightly Larger than Integrated Circuit
Carrier" ("SLICC") configuration wherein an array of minute solder
balls is disposed on an attachment surface of a semiconductor die
similar to a BGA, but having a smaller solder ball pitch and
diameter than a BGA.
[0006] The attachment of a flip chip to a substrate or another
semiconductor involves aligning the solder balls on the flip chip
with a plurality of contact points (configured to be a mirror image
of the solder ball arrangement on the flip chip) on the facing
surface of the substrate. A plurality of solder balls may also be
formed on the facing surface of the substrate at the contact
points. A quantity of liquid flux is often applied to the face of
the chip and/or substrate, and the chip and substrate are subjected
to elevated temperatures to effect reflowing or soldering of the
solder balls on the chip and/or corresponding solder balls on the
substrate. This connection technology is also referred to as "flip
chip attachment" or "C4--Controlled Collapse Chip Connection."
[0007] High performance microelectronic devices generally comprise
a number of flip chips attached to a substrate or printed circuit
board ("PCB") for electrical interconnection to other
microelectronic devices. For example, a very large scale
integration ("VLSI") chip may be electrically connected to a
substrate, printed circuit board, or other next level packaging
substrate.
[0008] Flip chip attachment requires the formation of contact
terminals on flip chip contact sites, each consisting of a metal
pad with a solder ball disposed thereon. Flip chip attachment also
requires the formation of solder joinable sites ("bond pads") on
the metal conductors of the substrate or PCB which are a
mirror-image of the solder ball arrangement on the flip chip. The
bond pads on the substrate are usually surrounded by non-solderable
barriers so that when the solder of the bond pads and of the chip
contact sites melts and merges ("reflow"), the surface tension
holds the semiconductor chip by solder columns, as if suspended
above the substrate. After cooling, the chip is essentially welded
face-down by these very small, closely spaced solder column
interconnections.
[0009] It is also known in the art that conductive polymers or
resins can be utilized in lieu of solder balls. U.S. Pat. No.
5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate
and a semiconductor die with a discontinuous passivation layer. The
discontinuities result in vias between the contact points of the
substrate and the semiconductor die. A resin with spaced conductive
metal particles suspended therein is disposed within the vias to
achieve electrical contact between the substrate and the
semiconductor die. U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to
Pasch relates to interconnecting conductive substrates using an
interposer having conductive plastic filled vias. U.S. Pat. No.
5,478,007 issued Dec. 26, 1995 to Marrs relates to using conductive
epoxy as a bond pad structure on a substrate for receiving a coined
ball bond on a die to achieve electrical communication between the
die and the substrate.
[0010] Such flip chip and substrate attachments (collectively
"electronic packages") are generally comprised of dissimilar
materials that expand at different rates on heating. The most
severe stress is due to the inherently large thermal coefficient of
expansion ("TCE") mismatch between the plastic and the metal. These
electronic packages are subject to two types of heat exposures:
process cycles, which are often high in temperature but few in
number; and operation cycles, which are numerous but less extreme.
If either the flip chip(s) or substrate(s) are unable to repeatedly
bear their share of the system thermal mismatch, the electronic
package will fracture, which destroys the functionality of the
electronic package.
[0011] As an electronic package dissipates heat to its surroundings
during operation, or as the ambient system temperature changes,
differential thermal expansions cause stresses to be generated in
the interconnection structures (e.g., solder ball bonds) between
the semiconductor die and the substrate. These stresses produce
instantaneous elastic and, most often, plastic strain, as well as
time-dependent (plastic and anelastic) strains in the joint,
especially within its weakest segment. Thus, the TCE mismatch
between chip and substrate will cause a shear displacement to be
applied on each terminal which can fracture the solder
connection.
[0012] The problem with TCE mismatch becomes evident during the
process of burn-in. Burn-in is the process of electrically
stressing a device, usually at an elevated temperature and voltage
environment, for an adequate period of time to cause failure of
marginal devices. When a chip, such as a flip chip, breaks free
from the substrate due to TCE mismatch, defective bonds, or the
like, the chip must be reattached and the burn-in process
reinitiated. This requires considerable time and effort which
results in increased production costs. Alternately, if the chip has
been underfilled and subsequently breaks free during burn-in, the
chip is not reworkable and must be discarded.
[0013] The problems with TCE mismatch are also applicable to
connections made with conductive polymers or resins, because after
curing the polymers or resins become substantially rigid. The rigid
connections are equally susceptible to breakage due to TCE
mismatch.
[0014] FIGS. 1a-1e show a contemporary, prior art method of forming
a conductive bump arrangement on a substrate. First, as shown in
FIG. 1a, a passivation film 102, such as at least one layer of
SiO.sub.2 film, Si.sub.3N.sub.4 film, or the like, is formed over a
face surface 104 of a semiconductor wafer 100 which has a
conductive electrode 106, usually an aluminum electrode. The
passivation film 102 is selectively etched to expose the conductive
electrode 106. FIG. 1b shows a metal layer 108 applied over a face
surface 110 of the passivation film 102 by deposition or
sputtering. A second layer of etch resist film 112 is applied to a
face surface 114 of the metal layer 108. The second etch resist
film 112 is masked, exposed, and stripped to expose a portion of
the metal layer 108 corresponding to the conductive electrode 106,
as shown in FIG. 1c. A solder bump 116 (generally an alloy of lead
and tin) is then formed on the exposed portion of the metal layer
108, as shown in FIG. 1d, by any known industry technique, such as
stenciling, screen printing, electroplating, electrolysis, or the
like. The second etch resist film 112 is removed and the metal
layer 108 is removed using the solder bump 116 as a mask to form
the structure shown in FIG. 1e. This conventional bump formation
method has drawbacks. The most obvious being the large number of
process steps required which results in high manufacturing
costs.
[0015] U.S. Pat. No. 4,970,571 issued Nov. 13, 1990 to Yamakawa et
al. (the '571 patent) relates to a bump formation method which
addresses the problems associated with conventional processing
methods by using electroless plating of palladium on the conductive
electrodes. Electroless plating is a metal deposition process,
usually in an aqueous medium, occurring through an exchange
reaction between metal complexes in solution and the particular
metal to be coated which does not require externally applied
electric current. The process of electroless plating of palladium
generally comprises dipping the semiconductor element with the
exposed conductive electrodes into a palladium solution wherein the
palladium selectively bonds or plates on the conductive electrodes.
The electroless plating process is a non-vacuum, high volume, high
throughput process which can be precisely controlled and uses
reliable equipment. The entire fabrication can be performed in a
less costly cleanroom environment which reduces processing time and
cost. The '571 patent teaches forming an electroless palladium
plated conductive electrode followed by the formation of a metal
bump on the palladium plated conductive electrode.
[0016] The benefits of using palladium in integrated circuits are
discussed in U.S. Pat. No. 4,182,781 issued Jan. 8, 1980, to Hooper
et al. (the '781 patent). The '781 patent teaches that palladium
forms a unique barrier metal in bump metallization systems which
increases yield and reliability of integrated circuit devices
designed for flip-chip attachment. It is also disclosed that
palladium is compatible with aluminum and has a thermal coefficient
of expansion that is sufficiently close to aluminum so that no
significant stress problems result. However, the '781 patent does
not teach using an electroless plating process to coat the
conductive electrode with palladium. However, electroless plating
is used to form the copper or nickel bump on the palladium coated
conductive electrode.
[0017] It would be advantageous to develop a more efficient
technique for forming conductive bumps on a flip chip which
eliminates some of the steps required by present industry standard
techniques while also abating the effects of TCE mismatch using
commercially-available, widely-practiced semiconductor device
fabrication techniques.
BRIEF SUMMARY OF THE INVENTION
[0018] The present invention relates to an apparatus and a method
for forming a substrate having a palladium metal layer over at
least one contact point of the substrate and having a flexible
conductive polymer bump, preferably a two-stage epoxy, on the
palladium plated contact point. The apparatus and method of the
present invention abate the effects of TCE mismatch and reduce the
number of steps required to produce substrates. The present
invention also relates to assemblies comprising one or more of
these substrates.
[0019] A preferred method for constructing the apparatus of the
present invention comprises providing a substrate, for example a
semiconductor wafer, which has at least one conductive electrode, a
semiconductor chip which has at least one bond pad, or a printed
circuit board. A passivation film such as at least one layer of
SiO.sub.2 film, Si.sub.3N.sub.4 film, or the like is formed over a
face surface of the substrate. The passivation film is selectively
etched to expose each conductive electrode or bond pad. The
substrate is then submersed in an electroless plating bath
containing palladium in solution. The palladium, through an
exchange reaction with the exposed conductive electrodes, bonds to
an upper surface of the conductive electrode or bond pad thereby
plating the conductive electrode or bond pad with a layer of
palladium.
[0020] It is, of course, understood that the passivation layer may
not be necessary when the material surrounding the conductive
electrode or bond pad is inert or is not otherwise susceptible to
being plated during the electroless plating process.
[0021] A conductive polymer is preferably applied to an upper
surface of the palladium layers to form a conductive polymer bump.
The conductive polymer bump is preferably a two-stage epoxy which
does not completely set, typically referred to as a "B-stage" type
epoxy. For example, a preferred two-stage epoxy such as RSC
3927-W/-B stage conductor, available from IMR Corporation, Nampa,
Id., can be used. The conductive polymer used to form the
conductive bump usually has a high electrical conductivity metal,
such as palladium, gold, silver, or the like, dispersed therein to
impart electrical conductivity to the polymer.
[0022] The conductive polymer bump can be formed by any number of
known industry standard techniques; however, the preferred method
comprises stencil printing the conductive polymer onto the
conductive electrode. The stencil printing process can be performed
in one step or in multiple printing steps wherein a plurality of
layers of conductive polymer are applied in succession. The stencil
printing method for forming the conductive polymer bumps of the
present invention is advantageous over presently known fabrication
methods, since it is a simpler process (having fewer processing
steps) and is less expensive.
[0023] A semiconductor assembly may be fabricated by attaching
substrates together in a face-to-face flip chip arrangement. The
substrates are mechanically attached to and in electrical
communication with one another via the plurality of conductive
polymer bumps formed on the palladium metal layers of the first
substrate, the palladium metal layers of the second substrate, or
both. An under-fill encapsulant may be disposed between the first
substrate and the second substrate for environmental protection and
to enhance the attachment of the first substrate and the second
substrate.
[0024] The use of a two-step curing epoxy virtually eliminates the
problems associated with TCE mismatch. Since the two-step curing
epoxy never completely sets to form a rigid matrix, the connections
will have an amount of "give" or "flex" during the thermal
expansion and contraction of the substrates, while still making a
reliable substrate-to-substrate electrical connection. This, in
turn, reduces the failure rate of semiconductor assemblies during
burn-in and during general use.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0025] While the specification concludes with claims particularly
pointing out and distinctly claiming that which is regarded as the
present invention, the advantages of this invention can be more
readily ascertained from the following description of the invention
when read in conjunction with the accompanying drawings in
which:
[0026] FIGS. 1a-1e illustrate side cross-sectional views of a prior
art method of forming a conductive bump on a substrate;
[0027] FIGS. 2a-2c illustrate side cross-sectional views of the
steps of a method of forming a conductive polymer bump on a
substrate of the present invention;
[0028] FIGS. 3a-3c illustrate side cross-sectional views of the
steps of a method of forming a conductive polymer bump on a
semiconductor die of the present invention;
[0029] FIG. 4 is a side cross-sectional view of a substrate
assembly of the present invention;
[0030] FIG. 5 is a side cross-sectional view of a first embodiment
of a substrate/chip assembly of the present invention; and
[0031] FIG. 6 is a side cross-sectional view of a second embodiment
of a substrate/chip assembly of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0032] FIGS. 2a-2c illustrate a method of forming a conductive
polymer bump on a substrate, such as a silicon wafer, a printed
circuit board, or the like, of the present invention. FIG. 2a
illustrates an exposed electrode substrate assembly 200 comprising
a substrate 202 which has at least one conductive electrode 204,
usually aluminum electrodes, disposed thereon. A passivation film
208 may be formed over a face surface 206 of the substrate 202. The
passivation film 208 is selectively etched to expose the conductive
electrode 204.
[0033] The exposed electrode substrate assembly 200 is immersed in
an electroless plating bath containing palladium in solution,
whereby through an exchange reaction the exposed conductive
electrodes 204 are selectively plated with a palladium layer 210
atop an upper surface 212 of the conductive electrode 204, as shown
in FIG. 2b. As shown in FIG. 2c, a conductive polymer is applied to
an upper surface 214 of the palladium layer 210 to form a
conductive polymer bump 216. The conductive polymer bump 216
preferably comprises a two-stage epoxy which does not completely
set. The conductive polymer used to form the conductive polymer
bump 216 preferably has a high electrical conductivity metal, such
as palladium, gold, silver, or the like, dispersed therein. The
conductive polymer bump 216 is preferably formed by stencil
printing or stenciling the conductive polymer onto the conductive
electrode 204.
[0034] It is, of course, understood that the passivation film 208
may be stripped from the substrate 202.
[0035] FIGS. 3a-3c illustrate a method of forming a conductive
polymer bump on a printed circuit board of the present invention.
FIG. 3a illustrates an exposed bond pad chip assembly 300
comprising a printed circuit board 302 which has at least one bond
pad 304, usually copper pads, disposed thereon. The bond pad 304
has a lead 306 (shown in shadow) within the printed circuit board
302 attached to a lower surface 308 of the bond pad 304.
Optionally, a passivation film 310 such as at least one layer of
resist polyimide film, or the like, is formed over a face surface
312 of the printed circuit board 302. The passivation film 310 is
selectively etched to expose the bond pad 304.
[0036] The exposed bond pad chip assembly 300 is immersed in an
electroless plating bath containing palladium in solution, whereby
through an exchange reaction the exposed bond pads 304 are
selectively plated with a palladium layer 314 atop an upper surface
316 of the bond pad 304, as shown in FIG. 3b. As shown in FIG. 3c,
a conductive polymer is applied to an upper surface 318 of the
palladium layer 314 to form a conductive polymer bump 320. The
conductive polymer bump 320 preferably comprises a two-stage epoxy
which does not completely set. The conductive polymer used to form
the conductive polymer bump 320 preferably has a metal, such as
palladium, gold, silver, or the like, dispersed therein. The
conductive polymer bump 320 can be formed in a manner discussed for
the conductive polymer bump 216 of FIG. 2.
[0037] It is, of course, understood that the passivation film 310
may be stripped from the printed circuit board 302.
[0038] FIG. 4 illustrates a substrate assembly 400 of the present
invention. The substrate assembly 400 comprises a first substrate
402 with a plurality of conductive electrodes 404 disposed on a
facing surface 406 of the first substrate 402. A palladium metal
layer 408 is disposed on each conductive electrode 404 by
electroless plating. The substrate assembly 400 further comprises a
second substrate 410 with a plurality of conductive electrodes 412
disposed on a facing surface 414 of the second substrate 410. A
palladium metal layer 416 is also disposed on each conductive
electrode 412. The first substrate 402 and the second substrate 410
are mechanically attached to and in electrical communication with
one another via a plurality of conductive polymer bumps 418
extending between the first substrate palladium metal layers 408
and the second substrate palladium metal layers 416. An under-fill
encapsulant 420 may be disposed between the first substrate 402 and
the second substrate 410 for environmental protection and to
enhance the attachment of the first substrate 402 and the second
substrate 410.
[0039] FIG. 5 illustrates a first embodiment of a substrate/chip
assembly 500 of the present invention. The substrate/chip assembly
500 comprises a substrate 502 with a plurality of conductive
electrodes 504 disposed on a facing surface 506 of the substrate
502. A palladium metal layer 508 is disposed on each conductive
electrode 504 by electroless plating. The substrate/chip assembly
500 further comprises a semiconductor chip 510 with a plurality of
bond pads 512 disposed on a facing surface 514 of the semiconductor
chip 510. A palladium metal layer 516 is also disposed on each bond
pad 512. The substrate 502 and the semiconductor chip 510 are
mechanically attached to and in electrical communication with one
another via a plurality of conductive polymer bumps 518 extending
between the substrate palladium metal layers 508 and the
semiconductor die palladium metal layers 516. An under-fill
encapsulant 520 may be disposed between the substrate 502 and the
semiconductor die 510 for environmental protection and to enhance
the attachment of the substrate 502 and the semiconductor chip
510.
[0040] FIG. 6 illustrates a second embodiment of a substrate/chip
assembly 600 of the present invention. The substrate/chip assembly
600 comprises a substrate 602 with a plurality of conductive
electrodes 604 disposed on a facing surface 606 of the substrate
602. The conductive electrodes 604 may comprise any suitable type
metal electrode, such as aluminum. The substrate/chip assembly 600
further comprises a semiconductor chip 610 with a plurality of bond
pads 612 disposed on a facing surface 614 of the semiconductor chip
610. A palladium metal layer 616 is also disposed on each bond pad
612. The substrate 602 and the semiconductor chip 610 are
mechanically attached to and in electrical communication with one
another via a plurality of conductive polymer bumps 618 extending
between the substrate conductive electrodes 604 and the
semiconductor die palladium metal layers 616. The conductive
material in the conductive polymer bumps 618 is capable of making
electrical contact with the conductive electrodes 604 and
penetrating any coating thereon whether an oxide coating or a
passivation layer coating. An under-fill encapsulant 620 may be
disposed between the substrate 602 and the semiconductor die 610
for environmental protection and to enhance the attachment of the
substrate 602 and the semiconductor chip 610.
[0041] It is, of course, understood that, although the assemblies
shown in FIGS. 4, 5 and 6 show substrates and/or semiconductor
chips which use the palladium layered structures of the present
invention, one of the substrates and/or semiconductor chips could
be one of industry standard manufacture.
[0042] Having thus described in detail preferred embodiments of the
present invention, it is to be understood that the invention
defined by the appended claims is not to be limited by particular
details set forth in the above description as many apparent
variations thereof are possible without departing from the spirit
or scope thereof.
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