U.S. patent application number 10/954806 was filed with the patent office on 2005-05-19 for method of depositing barrier layer from metal gates.
Invention is credited to Haukka, Suvi, Huotari, Hannu.
Application Number | 20050104112 10/954806 |
Document ID | / |
Family ID | 32397255 |
Filed Date | 2005-05-19 |
United States Patent
Application |
20050104112 |
Kind Code |
A1 |
Haukka, Suvi ; et
al. |
May 19, 2005 |
Method of depositing barrier layer from metal gates
Abstract
A method of manufacturing a high performance MOS device and
transistor gate stacks comprises forming a gate dielectric layer
over a semiconductor substrate; forming a barrier layer over the
gate dielectric layer by an ALD type process; and forming a gate
electrode layer over the barrier layer. The method enables the use
of hydrogen plasma, high energy hydrogen radicals and ions, other
reactive radicals, reactive oxygen and oxygen containing precursors
in the processing steps subsequent to the deposition of the gate
dielectric layer of the device. The ALD process for forming the
barrier layer is performed essentially in the absence of plasma and
reactive hydrogen radials and ions. This invention makes it
possible to use oxygen as a precursor in the deposition of the
metal gates. The barrier film also allows the use of hydrogen
plasma in the form of either direct or remote plasma in the
deposition of the gate electrode. Furthermore, the barrier film
prevents the electrode material from reacting with the gate
dielectric material. The barrier layer is ultra thin and, at the
same time, it forms a uniform cover over the entire surface of the
gate dielectric.
Inventors: |
Haukka, Suvi; (Helsinki,
FI) ; Huotari, Hannu; (Espoo, FI) |
Correspondence
Address: |
KNOBBE MARTENS OLSON & BEAR LLP
2040 MAIN STREET
FOURTEENTH FLOOR
IRVINE
CA
92614
US
|
Family ID: |
32397255 |
Appl. No.: |
10/954806 |
Filed: |
September 29, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10954806 |
Sep 29, 2004 |
|
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10430811 |
May 5, 2003 |
|
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6858524 |
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60430960 |
Dec 3, 2002 |
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Current U.S.
Class: |
257/310 ;
257/E21.204; 257/E21.635; 257/E21.637; 257/E29.16 |
Current CPC
Class: |
H01L 21/28088 20130101;
H01L 21/28202 20130101; H01L 29/513 20130101; H01L 21/28238
20130101; H01L 21/823842 20130101; H01L 29/518 20130101; H01L
29/4966 20130101; H01L 21/28185 20130101; H01L 21/28194 20130101;
H01L 21/823828 20130101; H01L 29/517 20130101 |
Class at
Publication: |
257/310 |
International
Class: |
H01L 027/108 |
Claims
We claim:
1. A gate stack in an integrated circuit comprising a dielectric
layer, a gate electrode and a barrier layer located between the
dielectric layer and the gate electrode, wherein the barrier layer
is composed of a different material than the gate electrode and
wherein the gate dielectric comprises a metal oxide and the barrier
layer comprises the same metal and nitrogen.
2. The gate stack of claim 1, wherein the metal is Hf.
3. The gate stack of claim 1, wherein the barrier layer further
comprises another element selected from the group consisting of
Group IV elements and other metals.
4. The gate stack of claim 3, wherein the barrier layer is
comprised of a material selected from the group consisting of HfN,
TaN, HfSi.sub.xN.sub.y, TiSi.sub.xN.sub.y, TaSi.sub.xN.sub.y,
WN.sub.xC.sub.y, and HfAl.sub.xN.sub.y.
5. The gate stack of claim 4, wherein the barrier layer is
comprised of a material selected from the group consisting of HfN
and WN.sub.xC.sub.y.
6. The gate stack of claim 1, wherein the barrier layer has a
thickness of less than 80 .ANG..
7. The gate stack of claim 1, wherein the barrier layer has a
thickness small enough not to affect a work function of the gate
stack.
8. The gate stack of claim 1, wherein the barrier layer has a
thickness of between about 1 and 50 molecular layers.
9. The gate stack of claim 1, wherein the barrier layer has a
thickness of between about 2 and 20 molecular layers.
10. The gate stack of claim 1, wherein the barrier layer has a
thickness of between about 2 and 4 molecular layers.
11. The gate stack of claim 1, wherein the barrier layer is
conductive.
12. The gate stack of claim 1, wherein the gate electrode is
comprised of a material selected from the group consisting of
polysilicon, poly-SiGE, W, TiN, TaN, Al, Ni, and Ti.
13. The gate stack of claim 1, wherein the gate dielectric is a
high k material.
14. The gate stack of claim 13, wherein the high k material has a
dielectric constant greater than 5.
15. The gate stack of claim 13, wherein the gate dielectric is
comprised of a material selected from the group consisting of
HfO.sub.2, ZrO.sub.2, TiO.sub.2, Ta.sub.2O.sub.5, strontium
titanate (ST), barium titanate (BT), barium strontium titanate
(BST), lead zirconium titanate (PZT) and strontium bismuth
tantalite (SBT).
16. The gate stack of claim 13, wherein the gate dielectric
comprises a laminate of multiple layers.
17. A gate stack in an integrated circuit comprising a substrate, a
high k dielectric layer, a gate electrode and a barrier layer
located between the dielectric layer and the gate electrode,
wherein the barrier layer has a thickness between 2 and 20
molecular layers.
18. The gate stack of claim 17, additionally comprising an
interfacial layer between the substrate and the high k dielectric
layer.
19. The gate stack of claim 18, wherein the interfacial layer is
about 5 .ANG. thick.
20. The gate stack of claim 18, wherein the interfacial layer
comprises a native oxide.
21. The gate stack of claim 18, wherein the interfacial layer
comprises a material selected from the group consisting of aluminum
oxide and lanthanide oxides.
22. The gate stack of claim 17, wherein the barrier layer has a
thickness between 2 and 4 molecular layers.
23. The gate stack of claim 17, wherein the barrier layer comprises
a nanolaminate structure.
24. The gate stack of claim 17, wherein the high k material
comprises HfO.sub.2.
25. The gate stack of claim 24, wherein the barrier layer comprises
HfN.
26. The gate stack of claim 17, wherein the substrate comprises a
material selected from the group consisting of silicon and
GaAs.
27. The gate stack of claim 17, wherein the substrate is an
epitaxial layer.
28. The gate stack of claim 17, wherein the barrier layer is
thicker than the dielectric layer.
Description
REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional of U.S. application
No. 10/430,811, filed May 5, 2003 and claims priority under 35
U.S.C. .sctn. 119(e) to U.S. provisional application No. 60/430,960
filed Dec. 3, 2002. The present application is also related to U.S.
application No. 10/430,703, filed May 5, 2003, the disclosure of
which is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] This invention relates generally to the field of
semiconductor manufacturing and in particular to the field of
forming transistor gate stacks in integrated circuits.
BACKGROUND OF THE INVENTION
[0003] Semiconductor devices are continuously improved to enhance
device performance. For example, both smaller device size and
higher speed of operation are highly desirable performance targets.
Transistors also have been continuously reduced in size. The
ability to construct smaller gate structures for complementary
metal oxide semiconductor (CMOS) transistors makes it possible to
pack more transistors on the same surface area. With the smaller
gate structures, the thickness of the gate dielectric has also
substantially decreased to 3 nm and below in today's technologies.
The principal elements of a typical MOS device are illustrated in
FIG. 1a. The device generally includes a semiconductor substrate
101 on which a gate stack is disposed.
[0004] The gate stack typically comprises an interfacial layer 109
between the silicon substrate and the gate dielectric layer, gate
dielectric layer 110 and a gate electrode 114 disposed on the gate
dielectric layer 110. In some circumstances (such as when using a
conventional silicon oxide gate dielectric), the interfacial layer
109 may be absent. The gate electrode 114 acts as a conductor. An
input signal is typically applied to the gate electrode 114 via a
gate terminal (not shown). Heavily doped source/drain regions 102
are formed in the semiconductor substrate 101 and are connected to
source/drain terminals (not shown). A channel region 103 is formed
in the semiconductor substrate beneath the gate electrode 114 and
separates source/drain regions 102. The channel is typically
lightly doped with a dopant of a type opposite to that of the
source/drain regions 102. The gate electrode 114 is separated from
the semiconductor substrate 101 by the gate dielectric layer 110.
The insulating gate dielectric layer 110 is provided to prevent
electrical current from flowing directly between the gate electrode
114 and the source/drain regions 102 or the channel region 103.
[0005] In the process for producing the gate stack in an IC, the
gate dielectric layer is deposited according to any thin film
deposition method and the gate electrode is deposited over the
dielectric layer. The gate dielectric materials currently
investigated are characterized by a high dielectric constant (i.e.
high-k material). The gate electrode layer is deposited of a
material having low electrical resistance. It is desired that the
process for depositing the gate electrode is fast to minimize the
time of the manufacturing. Polysilicon is generally used as the
gate electrode material. However, problems arise since a depletion
layer is formed at the polysilicon-dielectric interface, increasing
the equivalent oxide thickness of the gate stack. Therefore, other
electrode materials with low resistivity are desired. Furthermore,
thin film processes that are compatible with the process for
depositing the high-k dielectric layer are needed.
[0006] The properties of the transistor critically depend on the
thickness and quality of the gate dielectric layer 110. Therefore,
the dielectric layer, and even the interfacial layer and the
channel region are very sensitive to any impurities diffusing from
the gate electrode layer. Furthermore, the gate dielectric layer is
exposed to detrimental circumstances, when the process for
producing the gate electrode layer comprises use of oxygen or
oxygen containing precursors or when use of hydrogen plasma or
other method where hydrogen radicals are involved is desired after
the deposition of the gate dielectric layer.
[0007] In U.S. Pat. No. 6,383,879, Kizilyalli et al. describe the
use of a metal etch barrier film, deposited by conventional
techniques, between the gate dielectric layer and the gate
electrode. However, this gate barrier is a high-k dielectric film,
which will despite of its high-k value negativity contribute to the
effective electrical thickness of the gate dielectric. In U.S. Pat.
No. 6,225,168, Gardner et al. describe formation of a gate
dielectric layer and a gate barrier layer by subsequent oxidation
and nitridation of a deposited Ti or Ta layer. However, thickness
control in this rather complicated process sequence is
difficult.
[0008] The ultra thin dielectric structure of an interfacial layer
and a high-k gate dielectric layer is highly sensitive to oxygen.
Oxygen can easily penetrate, for instance through a HfO.sub.2 layer
of 20-30 .ANG., increasing the thickness of the interfacial
SiO.sub.2 layer between the silicon substrate and the high-k
dielectric layer. A small increase in thickness of the interfacial
SiO.sub.2 layer can degrade the equivalent oxide thickness (EOT)
enormously.
[0009] The deposition of a polysilicon gate electrode directly over
the HfO.sub.2 gate dielectric damages in part the gate oxide.
Therefore, a silicon nitride cap or a silicon oxynitride cap is
deposited over the gate oxide. However, such silicon compounds are
known to increase the EOT value. In the future, smaller and smaller
equivalent oxide thickness (EOT) values are called for and, at the
same time, from a process integration point of view a polysilicon
gate would be preferred. To avoid the depletion effect caused by
polysilicon and the increase in EOT caused by the use of a silicon
compound as a barrier, a metal or metal nitride barrier film is
desirable over the dielectric instead or a silicon compound
layer.
[0010] Accordingly, what is needed in the art is a- method of
forming a gate barrier film on a gate dielectric film that method
avoids the problems described above.
SUMMARY OF THE INVENTION
[0011] It is an object of the present invention to provide an
improved method of manufacturing a high performance MOS device and
in particular, high performance transistor gate stacks.
[0012] In accordance with one aspect of the present invention, a
method is provided for manufacturing semiconductor devices, wherein
the method comprises forming a gate dielectric layer over a
semiconductor substrate; forming a barrier layer over the gate
dielectric layer by an ALD type process; and forming a gate
electrode layer over the barrier layer.
[0013] In accordance with another aspect of the invention, the
preferred embodiments provide a barrier layer between two or more
materials. Preferably, one of the materials is a gate dielectric in
a semiconductor device and the other of the materials is a gate
electrode in a semiconductor device.
[0014] The method of the present invention facilitates the use of
hydrogen plasma, high energy hydrogen radials and ions, other
reactive radicals, reactive oxygen and oxygen-containing reactants
in the processing steps subsequent to the deposition of the gate
dielectric layer of the device. Such reactants can be advantageous
for patterning gate electrodes or for tailoring work function of
gate electrodes, particularly for CMOS circuits.
[0015] The barrier layer provides several functions and is
preferably highly conductive. The barrier layer prevents diffusion
of impurities from the gate electrode into the gate dielectric
layer. Furthermore, the barrier layer serves to prevent the
material underneath the barrier film reacting with the
surroundings. For example, it prevents further oxidation of an
underlying oxide during subsequent processing and thus prevents a
resulting increase in equivalent oxide thickness (EOT). Many of the
processes for formation of the gate electrode involve use of
oxygen, which increases the thickness of an interfacial layer
between the substrate and the gate dielectrics. This is a
particular concern when the dielectric material is a good oxygen
conductor, such as HfO.sub.2.
[0016] The barrier layer also serves to protect the dielectric
layer from sputtering damage and etch damage during subsequent
processing steps or any damage caused by hydrogen plasma, hydrogen
radials or any other high-energy ions.
[0017] The barrier layer is preferably deposited directly on top of
the gate dielectric layer. According to preferred embodiments of
the present invention the barrier layer is deposited using an
atomic layer deposition (ALD) type process including
plasma-enhanced ALD, wherein neither direct plasma is utilized
within the deposition chamber, nor highly reactive hydrogen
radicals or ions are formed. More specifically, the ALD process for
forming the barrier layer is performed essentially in the absence
of plasma and reactive hydrogen radials and ions. In the
illustrated embodiment, the highest allowed concentration of
hydrogen radicals and ions in the reactant vapor is determined as a
molar ratio of the hydrogen radicals and ions to the actual
reactant. For example, the highest allowed concentration of
hydrogen radicals and ions in the reactant vapor may be equal to or
less than 10% of the actual reactant. According to one preferred
embodiment the method is a thermal ALD method.
[0018] The present invention makes it possible to use oxygen as a
precursor in the deposition of metal gates that determine the work
function of the device in practice. The intervening barrier film
also allows the use of hydrogen plasma in the form of either direct
or remote plasma in the deposition of the gate electrode over the
gate dielectric. It allows the elimination of polysilicon carrier
depletion without affecting the work function provided by a
polysilicon gate electrode. Furthermore, the barrier film formed
according to the preferred embodiments prevents the electrode
material from reacting with the gate dielectric material, which
would change and eventually destroy the transistor. In all the
aforementioned cases, the barrier layer deposited is preferably
ultra thin and, at the same time, it forms a uniform cover over the
entire surface of the gate dielectric.
[0019] Furthermore, the properties of the interface between the
gate dielectric layer and the barrier film are easily controlled in
the preferred embodiments. As the thickness of the gate dielectric
layer scales to 3 nm or below, the properties of the upper gate
dielectric interface are significant for the performance of the
device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1a is a schematic cross-section showing a state of the
art transistor gate stack, according to the prior art.
[0021] FIG. 1b shows a state of the art gate stack including a gate
barrier film, constructed in accordance with a preferred embodiment
of the present invention.
[0022] FIG. 2 shows a flow chart generally illustrating the
formation of a gate stack comprising a barrier layer between the
gate electrode and the high k dielectric in accordance with a
preferred embodiment of the invention.
[0023] FIG. 3 shows a flow chart of a particular ALD process for
the production of a barrier layer between a dielectric layer and a
gate electrode, in accordance with another preferred embodiment of
the invention.
[0024] FIG. 4 shows a HRTEM photo of a gate structure that was made
by thermal ALD without any pre-deposition treatment of the gate
dielectric.
[0025] FIG. 5 shows a HRTEM photo of a gate structure that was made
by thermal ALD with a NH.sub.3 pre-deposition treatment of the gate
dielectric.
[0026] FIG. 6 shows a HRTEM photo of a gate structure that was made
by PEALD without any pre-deposition treatment of the gate
dielectric.
[0027] FIG. 7 shows a HRTEM photo of a gate structure that was made
by PEALD with nitrogen/hydrogen-plasma pre-deposition treatment of
the gate dielectric.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0028] While illustrated in the context of transistor gate stacks,
the skilled artisan will readily find application for the
principles and advantages disclosed herein to other situations
where similar electrical and physical properties at an interface
are desired.
[0029] FIG. 1b shows a gate dielectric layer 110 located between an
overlying gate electrode 114 and the substrate 101. To improve the
reliability of the transistor, the gate dielectric layer 110 is
separated from the gate electrode 114 by a gate barrier film 112,
as shown in FIG. 1b. Such a barrier film 114 prevents detrimental
reactions. Such detrimental reactions may include, but are not
limited to, a chemical reaction or a diffusion of impurities, such
as molecules, atoms or ions from the solid phase one side of the
high-k material to the solid phase on the other side of the high-k
material. For example, one concern with high-k dielectric
materials, such as HfO.sub.2, is their weak properties as diffusion
barriers for dopant such as boron. Boron can penetrate through the
high-k layer to the transistor channel and change the doping level
of the transistor channel.
[0030] The barrier layer 112 inhibits the diffusion of impurities
from the gate electrode 114 into the gate dielectric layer 110 or
even into the channel region 103. For the barrier layer 112 to
function effectively as diffusion barrier, at least one molecular
layer is desired, preferably between about 1 and 50 molecular
layers, more preferably between about 2 and about 20 molecular
layers, and most preferably between about 2 and 4 molecular
layers.
[0031] The barrier layer 112 is highly conductive in order not to
increase the effective electrical thickness of the gate dielectric.
Examples of suitable materials are TiN, TaN, HfN,
HfSi.sub.xN.sub.y, TiSi.sub.xN.sub.y, TaSi.sub.xN.sub.y, WNC and
HfAl.sub.xN.sub.y or any other material that forms an efficient
barrier and does not react with the underlying gate dielectric
material during deposition or during subsequent processing steps.
More preferably the barrier layer comprises HfN or
WN.sub.xC.sub.y.
[0032] The substrate 101 typically comprises silicon or GaAs, and
can be a wafer or an epitaxial layer. Materials for the gate
electrode 114 are well known in the art and include polycrystalline
silicon (polysilicon), poly-SiGe, W, TiN, TaN, Al, Ni and Ti. The
hotter metals are particularly preferred for circuits in which
careful tuning of the work function is needed, e.g., for CMOS
circuits in which different transistor gates across the circuit
require different work functions.
[0033] The gate dielectric layer 110 is typically characterized by
a high-k value. The gate dielectric maybe made of any material
known in the art. Examples of high-k materials known in the art are
hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), titanium
dioxide (TiO.sub.2), tantalum oxide (Ta.sub.2O.sub.5), strontium
titanate (ST), barium titanate (BT), barium strontium titanate
(BST), lead zirconium titanate (PZT) and strontium bismuth
tantalite (SBT). The dielectric layer may comprise multiple
materials, for example, a ternary structure or a laminate of
multiple layers, such as Ta.sub.2O.sub.5-TiO.sub.2. Preferred gate
dielectrics comprise ZrO.sub.2 or HfO.sub.2.
[0034] An interfacial layer 109 is often present in the substrate
and the gate dielectric layer. The interfacial layer typically
comprises SiO.sub.2 or SiO.sub.xN.sub.y and it is about 5 .ANG.
thick (e.g., 3-12 .ANG.). In one embodiment the interfacial layer
comprises a native oxide. In another embodiment, the interfacial
layer comprises aluminum oxide or lanthanide (rare earth) oxide.
Other material and arrangements for the gate stack are well known
to the skilled artisan.
[0035] The preferred processes for depositing the gate electrode
include an ALD process, wherein molecular oxygen is used as a
second precursor together with the metal cyclopentadienyl compounds
of p-type metals, such as Ru, Pt, or IT (see U.S. patent appl. No.
10/066,315, the disclosure of which is incorporated herein by
reference). The other processes include also p-type metals like Ni
and Co, which are deposited from corresponding metal
betadiketonates and ozone with ALD and reduced into elemental metal
(see U.S. Pat. No. 6,482,740, the disclosure of which is
incorporated herein by reference).
[0036] Other preferred processes for producing the gate electrode
114 are thin film processes where direct or remote hydrogen plasma
is used. On the other hand, hydrogen plasma has been shown to be
detrimental, especially to an ultra thin high k (e.g., HfO.sub.2)
gate dielectric, which fact has limited the use hydrogen plasma in
the deposition processes of metal films as gate electrodes directly
on the gate oxide.
[0037] The present invention provides a barrier layer between two
or more materials. Preferably, one of the materials is a high
dielectric constant (high-k) material, such as HfO.sub.2 or
ZrO.sub.2. The high-k material preferably has a dielectric constant
greater than 5. More preferably the high-k material has a
dielectric constant greater than about 10. Such high-k materials
include oxides of group 3 (for example Y, La and Gd), group 4 (Ti,
Zr, Hf) and group 5 elements (V, Nb, Ta), as well as more complex
oxides. Thus, high-k materials can include lanthanide (rare earth)
oxides of group 3 elements, such as yttrium oxide (k'"12),
lanthanum oxide (k.apprxeq.21), neodymium oxide (k.apprxeq.16), and
cerium dioxide (k.apprxeq.15). In other arrangements, it will be
understood that the high-k material can comprise multiple
materials, either as a ternary structure or a laminate of multiple
high-k material layers.
[0038] In context of the present invention, "an ALD type process"
generally refers to a process for producing thin films over a
substrate, in which process a solid thin film is formed molecular
layer by molecular layer due to self-saturating chemical reactions
on heated surfaces. In the process, vapor phase reactants, i.e.
precursors, are conducted into a reaction chamber of an ALD type of
a reactor and contacted with a substrate located in the chamber to
provide a surface reaction. The pressure and the temperature of the
reaction chamber are adjusted to a range where physisorption (i.e.
condensation of gases) and thermal decomposition of the precursors
are avoided. Consequently, only up to one monolayer (i.e. an atomic
layer or a molecular layer) of material is deposited at a time
during each pulsing cycle. The actual growth rate of the thin film,
which is typically presented as .ANG. per pulsing cycle, depends,
for example, on the number of available reactive surface sites on
the surface and bulkiness of the chemisorbing molecules. Gas phase
reactions between precursors and any undesired reactions of
byproducts are inhibited because material pulses are separated from
each other by time and the reaction chamber is purged with an
inactive gas (e.g. nitrogen or argon) between material pulses to
remove surplus gaseous reactants and reaction byproducts from the
chamber. The principles of ALD type processes have been presented
by T. Suntola, e.g. in the Handbook of Crystal Growth 3, Thin Films
and Epitaxy, Part B: Growth Mechanisms and Dynamics, Chapter 14,
Atomic Layer Epitaxy, pp. 601-663, Elsevier Science B.V. 1994, the
disclosure of which is incorporated herein by reference.
[0039] In context of the present application, "a reaction space"
designates generally a reactor or a reaction chamber in which the
conditions can be adjusted so that deposition of a thin film is
possible.
[0040] In context of the present application, "an ALD type reactor"
means a reactor where the reaction space is in fluid communication
with an inactive gas source and at least two precursor sources that
can be pulsed in alternated steps whereby vapor phase reactants are
kept separated, the reaction space is in fluid communication with a
vacuum generator (e.g. a vacuum pump), and the temperature and
pressure of the reaction space and the flow rates of gases can be
adjusted to a range that makes it possible to grow thin films by
ALD type processes.
[0041] One example of an ALD type process applicable in performing
the preferred embodiments is an ALD process utilizing remote
plasma. In the process, the plasma is formed outside the reaction
chamber and pulsed as a reactant pulse into the reaction chamber.
The equipment is configured to optimize neutral excited species
delivery and minimize ion delivery to the substrate. However,
radicals of the precursor may be present.
[0042] "Thermal ALD" refers to an ALD method where plasma is not
used for activating reactants but the substrate temperature is high
enough for overcoming the energy barrier (activation energy) during
collisions between the chemisorbed species on the surface and
reactant molecules in the gas phase so that up to a molecular layer
of thin film grows on the substrate surface during each ALD pulsing
sequence.
[0043] The barrier layer 112 is primarily composed of a different
material than the gate electrode 114. In one embodiment the barrier
layer comprises a metal that is also present in the underlying
dielectric layer. For example, the barrier layer 112 may comprise a
metal nitride while the dielectric 110 comprises an oxide of the
same metal. In a particular embodiment the dielectric layer
comprises HfO.sub.2 and the overlying layer comprises HfN. In a
particular embodiment, a thin HfN barrier layer is deposited
immediately after the deposition of HfO.sub.2 in the same reaction
space.
[0044] In a further embodiment, the barrier layer 112 comprises TiN
processed by ALD using TiC.sub.4 and NH.sub.3 the precursors.
According to another embodiment, the barrier layer 112 comprises
TaN deposited, for instance, using TaCl.sub.5, Zn and NH.sub.3. Zn
is introduced as a separate reducing agent in between the pulse of
the metal compound and the pulse of NH.sub.3. Instead of zinc,
other reducing agents, such as various silicon and boron compounds,
can be used. According to one more embodiment of the present
invention, the barrier layer 112 comprises tungsten nitride carbide
(WN.sub.xC.sub.y), which is deposited, for instance, from WF.sub.6,
triethyl boron (TEB) and NH.sub.3, wherein TEB is used as a
reducing agent and for gettering halogen from the metal source
chemical (e.g. fluorine from absorbed species of WF.sub.6).
[0045] In other embodiments the barrier layer 112 comprises a
nanolaminate structure of a ternary complex. In one embodiment the
gate dielectric barrier 112 is a nanolaminate structure comprising
a plurality of thin layers of different materials. Preferably, the
nanolaminate structure comprises amorphous layers. Nanolaminates
similar to those described in WO 01/29893, incorporated herein by
reference, could be used.
[0046] A barrier layer 112 thicker than about 100 .ANG. will likely
affect and possibly even define the work function of the gate.
Thus, in terms of absolute thickness, the barrier layer preferably
has a thickness of less than or equal to about 100 .ANG., more
preferably less than or equal to about 80 .ANG. and most preferably
less than or equal to about 30 .ANG.. However, if it is desired to
have the work function determined by the barrier layer 112, a
thicker layer, greater than 100 .ANG. may be used. The barrier
layer 112 may be thinner than the dielectric layer or thicker than
the dielectric layer.
[0047] In thermal ALD, the deposition temperature of metals and
metal nitrides is typically higher than in the deposition of high-k
dielectric layers due to high activation energy required for
removing the ligands of the precursors. This leads to a low number
of reactive sites on the high-k dielectric surface. In order to
provide good surface coverage and to prevent the change in the
reaction mode of the metal compound at the beginning of the metal
on metal nitride deposition, the first metal-containing pule is
preferably conducted before raising the temperature to the desired
barrier layer deposition temperature. For instance, in case of TiN
deposition from TiCL.sub.4 and NH.sub.3 the first TiC.sub.4 pulse
is introduced at the lower temperature than 300.degree. C., more
preferably at 250.degree. C. and most preferably below 200.degree.
C. during the stabilization time of the high-k surface. After the
first pulse the temperature is increased to the final reaction
temperature of the TiN process being more 350.degree. C. In extreme
case the temperature can also be cycled between the reaction
temperature of the metal compound reaction (adsorption) and that of
the removing agent of the ligand (ligand gettering or ligand
exchange), in this case NH.sub.3. One more example is also the
deposition of hafnium nitride (HfN). In the reactor for the
dielectric growth, the deposition cycle is completed with the
HfCL.sub.4 pulse and then the temperature is increased to the
reaction temperature of the ligand removing agent, in this case
NH.sub.3, in the same reactor or in a separate reactor.
[0048] In one embodiment the surface of the dielectric layer 110 is
treated by physical or chemical means prior to the deposition of
the barrier layer to modify the surface to better comply with the
subsequent processing steps. According to one more embodiment the
barrier layer is treated after its deposition to remove impurities
incorporated in the layer during the deposition.
[0049] A process flow chart indicating the preferred embodiment
with both the pre-deposition treatment and the post-deposition
treatment is shown in FIG. 3.
Pre-Deposition Treatment
[0050] If the dielectric material comprises an oxide, for example
hafnium dioxide (HfO.sub.2), the surface of the dielectric layer
will comprise reactive hydroxyl (OH) groups. If the subsequent
deposition of a barrier layer, such as a metal nitride, is begun by
introduction of a metal source chemical pulse (e.g., TiC.sub.4), up
to amolecular layer of metal oxide will grow on the surface and the
equivalent oxide thickness of the dielectric layer increases.
[0051] Thus, in one embodiment an oxide dielectric layer is treated
to replace OH groups on the surface with N, NH and/or NH.sub.2
groups prior to barrier layer deposition. A process flow chart
indicating a nitrogen pre-treatment step is shown in FIG. 3.
Following such treatment the first metal source chemical pulse will
react with the NH and/or NH.sub.2 groups on the surface and a metal
nitride layer up to one molecular layer will grow on the surface of
the dielectric layer. As a result, the equivalent oxide thickness
of the high-k layer does not increase. In a particular embodiment a
high-k oxide surface is treated with ammonia (NH.sub.3) or
hydrazine (N.sub.2H.sub.4) gas. Preferably, the treatment is
continued for about one minute (60 s.+-.10 s) at about 350.degree.
C.
[0052] The pre-deposition treatment may be part of the process by
which the barrier layer is deposited. For example, a TiN barrier
film may be deposited from separated TiCl.sub.4 and NH.sub.3 pulses
in an ALD process. The process may be started with a long pulse of
NH.sub.3, thus replacing the surface OH groups with NH and/or
NH.sub.2 groups. Preferably the first NH.sub.3 pulse is greater
than 10 seconds, more preferably greater than 20 seconds (e.g.,
about 60 seconds) in length. Subsequent NH.sub.3 pulses may be of
shorter duration.
[0053] According to another embodiment the high k oxide surface is
treated with radicals. In a particular embodiment the dielectric
surface is treated with NH or NH.sub.2 radicals for example for
greater than 10 seconds, more preferably greater than 20 seconds,
(e.g., about 60 seconds). The radicals may be generated, for
example, thermally from hydrazine. Surface treatment of high-k
dielectrics prior to conductor deposition is described, for
example, in U.S. patent application No. 09/944,734, also published
as WO 02/43115, the disclosure of which is hereby incorporated
herein by reference.
Post-Deposition Treatment
[0054] The gate dielectric barrier may comprise impurities
following its formation. For example, if the barrier comprises a
metal nitride that was deposited from a metal halide, the metal
nitride film may contain some halide impurities. If a metal nitride
film was deposited from organometallic source chemicals, the film
may contain some carbon impurities that have not formed conductive
carbides with metals. Impurities may be removed from the barrier
layer material by post-deposition treatment.
[0055] A process flow chart indicating the post-treatment step to
volatilize impurities from the barrier layer is shown in FIG. 3. In
one embodiment a metal nitride layer is treated with hydrogen
plasma to remove residual halides and/or carbon. According to
another embodiment, a metal nitride barrier layer is annealed at a
temperature that is higher than the deposition temperature of the
metal nitride and is lower than the crystallization temperature of
the metal nitride. Ammonia (NH.sub.3) gas can optionally be present
in the gas phase during annealing so that volatile impurities more
efficiently leave the gate dielectric barrier.
[0056] Following the deposition of the gate dielectric barrier
layer, a gate electrode is deposited by any method known in the
art, including CVD, PVD, ALD, etc. The gate electrode may comprise
some impurities following its formation, particularly if metal
halide or organometallic source chemicals are used. As discussed
above for the barrier layer, these impurities may be removed by
optional plasma treatment and/or annealing following the gate
electrode deposition. In one embodiment, formation of the gate
electrode included incorporation of oxygen into the layer to tailor
work function, as disclosed in the application entitled METHOD OF
FORMING AN ELECTRODE WITH ADJUSTED WORK FUNCTION, the disclosure of
which is incorporated herein above under the heading "Reference to
Related Applications."
EXAMPLE
[0057] Substrates consisted of wafers that had native oxide on the
silicon surface, the native oxide comprising a thin chemical
silicon oxide made with an IMEC-clean.RTM.. Hafnium dioxide thin
films having thickness of 3-5 nm were deposited at 300.degree. C.
by thermal ALD on the substrates.
[0058] Titanium nitride (TiN) barrier thin films were deposited on
top of the atomic layer deposited hafnium dioxide thin films (FIGS.
4-7). The TiN thin films were deposited in a Pulsar.RTM.2000
ALCVD.TM. reactor (ASM Microchemistry Oy of Espoo, Finland). In one
set of experiments, TiN was deposited by thermal ALD from titanium
tetrachloride (TiC.sub.4) and ammonia (NH.sub.3) at higher
temperatures, preferably 350.degree. C. In another set of
experiment TiN was deposited by plasma enhanced ALD using
TiCl.sub.4 and nitrogen/hydrogen remote plasma at lower
temperatures. The thin films were characterized using standard
techniques.
[0059] The average growth rate of titanium nitride deposited by
thermal ALD was 0.02 nm/cycle. Films were very uniform and had a
stoichiometry of TiN.sub.1.10. There was about 0.5-atomic-% of
residual chlorine in the films. Films were oxidized in the air up
to a depth of approximately 25 nm, with a resulting oxygen
concentration of about 30 atomic-% at the film surface. Films were
polycrystalline cubic titanium nitride. It was observed that 5 nm
thick films consisted of many different crystal orientation phases
and also amorphous phases. Thicker films (over 50 nm) consisted
primarily of <111> crystal orientation. Resistivity was found
to depend on the thickness of the film and varied from about 440
.mu..OMEGA.cm to about 1600 .mu..OMEGA.cm.
[0060] The average growth rate of titanium nitride films deposited
by remote plasma ALD was about 0.03 nm/cycle. The films comprised
from about 2 to about 6 atomic-% of residual chlorine. The
concentration of titanium in the films was approximately 50
atomic-% indicating nearly stoichiometric TiN. Films comprised
polycrystalline cubic titanium nitride. Even 5 nm thick films were
very crystalline despite the low growth temperature. Thicker films
(over 50 nm) consisted mostly of <200> crystal orientation.
Resistivity of the films varied in the range of 170 .mu..OMEGA.cm
to about 430 .mu..OMEGA.cm.
[0061] The work function of the titanium nitride electrode was
determined to be 4.8 eV. Full coverage of titanium nitride on the
hafnium dioxide surface was achieved within about 10 to about 20
deposition cycles.
[0062] Although this invention has been described in terms of
certain preferred embodiments, other embodiments that are apparent
to those of ordinary skill in the art are also within the scope of
this invention. It will be appreciated by those skilled in the art
that various omissions, additions and modifications may be made to
the processes described above without departing from the scope of
the invention, and all such modifications and changes are intended
to fall within the scope of the invention, as defined by the
appended claims.
* * * * *