U.S. patent application number 10/975845 was filed with the patent office on 2005-04-21 for thin film semiconductor device and its substrate sheet as well as the method for production thereof.
This patent application is currently assigned to Advanced LCD Technologies Development Center, Co, Ltd.. Invention is credited to Abe, Hiroyuki, Koseki, Hideo, Matsumura, Masakiyo, Oana, Yasuhisa, Warabisako, Mitsunori, Yamamoto, Yoshitaka.
Application Number | 20050085002 10/975845 |
Document ID | / |
Family ID | 19052554 |
Filed Date | 2005-04-21 |
United States Patent
Application |
20050085002 |
Kind Code |
A1 |
Matsumura, Masakiyo ; et
al. |
April 21, 2005 |
Thin film semiconductor device and its substrate sheet as well as
the method for production thereof
Abstract
A thin film semiconductor device and a method for producing it
are described. In the thin film layer of semiconductor of the
device, a plurality of large size single-crystalline grains of
semiconductor are formed in a regulated configuration, and each of
single crystalline grains is equipped with one unit of electric
circuit having a gate electrode, a source electrode and drain
electrode. Such regulated arrangement of large size
single-crystalline grains in the semiconductor layer is realized by
a process including a step of irradiating the layer of amorphous or
polycrystalline semiconductor with energy beam such as excimer
laser so that maximum irradiation intensity points and minimum
irradiation intensity points are arranged regulatedly. The device
can have a high mobility such as about 500 cm.sup.2/V sec.
Inventors: |
Matsumura, Masakiyo;
(Yokohama-Shi, JP) ; Oana, Yasuhisa;
(Yokohama-Shi, JP) ; Abe, Hiroyuki; (Yokohama-Shi,
JP) ; Yamamoto, Yoshitaka; (Yokohama-Shi, JP)
; Koseki, Hideo; (Yokohama-Shi, JP) ; Warabisako,
Mitsunori; (Yokohama-Shi, JP) |
Correspondence
Address: |
MORRISON & FOERSTER LLP
1650 TYSONS BOULEVARD
SUITE 300
MCLEAN
VA
22102
US
|
Assignee: |
Advanced LCD Technologies
Development Center, Co, Ltd.
Yokohama-Shi
JP
|
Family ID: |
19052554 |
Appl. No.: |
10/975845 |
Filed: |
October 29, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10975845 |
Oct 29, 2004 |
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10192850 |
Jul 11, 2002 |
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6828178 |
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Current U.S.
Class: |
438/67 ;
148/33.2; 205/674; 257/66; 257/E21.134; 257/E21.413; 257/E21.415;
257/E29.286; 257/E29.293; 438/149; 438/150 |
Current CPC
Class: |
H01L 29/66772 20130101;
H01L 27/1218 20130101; H01L 21/02678 20130101; H01L 29/66757
20130101; H01L 21/67373 20130101; H01L 21/67775 20130101; H01L
21/67772 20130101; H01L 29/78675 20130101; H01L 21/67379 20130101;
H01L 21/02532 20130101; H01L 27/1274 20130101; H01L 21/02686
20130101; H01L 27/1285 20130101; H01L 27/1296 20130101; H01L
29/78654 20130101 |
Class at
Publication: |
438/067 ;
438/149; 438/150; 257/066; 205/674; 148/033.2 |
International
Class: |
H01L 029/10; H01L
029/76; H01L 031/036; H01L 021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 17, 2001 |
JP |
2001-218370 |
Claims
1-29. (canceled)
30. A substrate sheet for thin film semiconductor device
comprising: a base layer of insulation materials, a thin film layer
of semiconductor formed on the base layer, and a plurality of
single-crystalline semiconductor grains formed in the thin film
layer of semiconductor, said plurality of single-crystalline
semiconductor grains being arranged in a matrix-arrayed
configuration in the thin film layer of semi-conductor in a mode
such that each of the single-crystalline grains adjoin to the next
single-crystalline grains with being interposed by boundary areas
formed in between the grains and, each of said single-crystalline
semiconductor grains having the grain size of at least 2 .mu.m.
31. A substrate sheet for thin film semiconductor devices of claim
30, wherein a control layer for heat-conduction and crystallization
is formed in between the base layer and the thin film layer of
semiconductor.
32. A thin film semiconductor devices of claims 30 or 31, wherein a
control layer for heat-conduction and crystallization is formed on
the thin film layer of semiconductor.
33. A thin film semiconductor device comprising: a base layer of
insulation materials, a thin film layer of semiconductor formed on
the base layer, and a plurality of single-crystalline semiconductor
grains formed in the thin film layer of semiconductor, said
plurality of single-crystalline semiconductor grains being arranged
in a matrix-arrayed configuration in a mode such that each of the
single-crystalline grains adjoin to the next single-crystalline
grains with being interposed by boundary areas formed in between
the grains, and each of said single-crystalline semiconductor
grains having the grain size of at least 2 .mu.m, and being
equipped with an electric circuit having a gate electrode, a source
electrode and a drain electrode.
34. A thin film semiconductor device comprising: a base layer of
insulation materials, a thin film layer of semiconductor formed on
the base layer, and a plurality of single-crystalline semiconductor
grains formed in the thin film layer of semiconductor, said
plurality of single-crystalline semiconductor grains being arranged
in a matrix-arrayed configuration in a mode such that each of the
single-crystalline grains adjoin to the next single-crystalline
grains with being interposed by boundary areas formed in between
the grains, each of said single-crystalline semiconductor grains
having the grain size of at least 2 .mu.m, and electric circuit
being arranged over the plurality of single-crystalline grains in a
mode of CMOS type.
Description
[0001] A thin film semiconductor device having arrayed
configuration of semiconductor crystals and a method for producing
it.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a thin film semiconductor
device and a semiconductor substrate sheet to be used in the
semiconductor device as well as a method for producing them.
[0003] As is well known, a thin film semiconductor device or thin
film transistor (TFT) comprises a substitute, in which a thin film
layer of semiconductor materials such as silicon is formed on a
base layer of insulation materials such as non-alkaline glass, or
quarts glass. In the thin film layer of semiconductor, a plurality
of channel consisting of a source area and a dry area are formed
and each of channels is equipped with a gate electrode. Generally,
the thin film layer of semiconductor consists of amorphous or
polycrystalline silicon. However, a TFT using a substrate
comprising a thin layer of amorphous silicon cannot be used for a
device which requires a high speed operation owing to its extreme
low mobility (usually, approximately less than 1 cm.sup.2/V sec).
Therefore, recently, a substrate comprising a thin film layer of
polycrystalline silicon is used in order to increase the mobility.
Nevertheless, even in a case of using such substrate, the
improvement of mobility is limited because of such phenomenon at
the time of operation as dispersion of electron at boundaries
between crystal grains, owing to the fact that the polycrystalline
thin film consists of numerous crystalline grains of extreme small
size.
[0004] Thus, it has been tried to obtain a substrate having a thin
film layer which makes it possible to increase mobility by avoiding
disadvantageousness such as electron dispersion, by means of making
the size of polycrystalline silicon to be large. For instance, it
has been tried to obtain a thin film layer having a semiconductor
grains of about 1 .mu.m size and having a mobility of about 100
cm.sup.2/V sec., by annealing a layer of polycrystalline silicon a
high temperature furnace. However, the above process has a
disadvantage that inexpensive glass sheets such as sodium glass
sheets clot be used and expensive quartz glass sheets which can
bear high temperature should be used as the process requires an
annealing by extreme high temperature such as over 1000.degree. C.
A substrate using such extensive materials is not suited for
producing a device of wide size screens in view of costs.
[0005] Some other trials has been proposed in order to obtain a
thin layer which consists of polycrystalline semiconductor of large
size grains, by means of irradiating a thin film of amorphous or
polycrystalline semiconductor with energy beams such as excimer
laser, instead of using high temperature annealing. By this method,
it is possible to enlarge the size of a crystal grain, by using
inexpensive glass sheets as the base layer.
[0006] Nevertheless, even by the method using irradiation of
excimer laser, the size of obtained crystal grain could not exceed
1 .mu.m and it is inevitable that sizes of grains become uneven.
For instance, in the specification of JPA 2001-127301, there is
described a technology for obtaining a thin film layer of
polycrystalline semiconductor of large size crystal grains
comprising following steps; that is, polycrystalizing a thin film
of amorphous silicon by a melt recystallization method, for
example, using excimer laser irradiation, then depositing a thin
layer of amorphous silicon on the recrystallized layer and,
crystallizing the whole layers by solid phase growing method,
thereby growing original polycrystalline gram to large size grains.
However, in the above technique, it is suggested that the maximum
size of obtained crystal grain is about 1000 nm (1 .mu.m) and sizes
are uneven (cf. FIGS. 2 to 5 in the above specification).
[0007] Furthermore, there is an important problem, which has been
neglected in the technique of semiconductor device comprising
polycrystalline semiconductor that is, the problem of arrangement
mode of crystal grains. In the thin layer of polycrystalline
semiconductor produced by previous techniques, the arrangement mode
of crystal grains in the two-dimensional direction is utterly
random. No trial for making such arrangement of crystal grains to
be a regulated mode has been made. But, randomness of arrangement
of crystal grains causes a serous disadvantage.
[0008] That is, it would be needless to say that the numerous units
of transistor circuits formed in a thin film semiconductor device
have to be arranged in a regulated mods such as geometrical
arrangement mode. Therefore, when the sizes of crystal grains are
uneven and the arrangement thereof are random (not regulated) in a
thin film layer, an unit circuit of one transistor is inevitably
set in such a modem to extend to a plurality of crystal grains of
various sizes and positions (cf. FIG. 6). This would bring such
result that the mobility and the electron transfer mode of each
unit circuit are different one another, and this in turn would
bring a bad influence to the quality of the device. As the result,
when characteristics of every unit circuits differs each other, a
device cannot but be designed on the whole by being based on the
low level characteristics. This is an important problem to be
solved.
SUMMARY OF THE INVENTION
[0009] It is an object of the present invention to provide a
substrate sheet for thin film semiconductor devices, in which a
plurality of large size single crystalline grains of semiconductor
are formed in a regulated arrangement mode such as a matrix-arrayed
configuration, thereby making it possible to use it as the
substrate sheet for a thin film semiconductor device in which an
unit circuit comprising a source electrode, a drain electrode and a
gate electrode is formed on each of crystal grain.
[0010] It is further object of the present invention to provide a
thin film semiconductor device, which has a high mobility without
being influenced by disadvantage such as unevenness of crystal
grain size or electron dispersion occurred in crystal grain
boundaries, by meat of setting an unit circuit comprising a source
electrode, a drain electrode and a gate electrode on each of
crystal gains which are arranged regulatedly in such mode as a
matrix-arrayed configuration in the thin film layer of
semiconductor.
[0011] It is another object of the present invention to provide a
process for producing a substrate sheet for, a thin firm
semiconductor devices in which a plurality of large size single
crystalline grains of semiconductor are formed in a regulated
arrangement mode such as a matrix-arrayed configuration.
[0012] It is another further object of the present invention to
provide a process for producing a thin film semiconductor device in
which an unit circuit comprising a source electrode, a drain
electrode and a gate electrode are firmed on each of crystal grains
which are arranged regulatedly in such mode as a matrix-arrayed
configuration in the thin film layer of semiconductor.
[0013] Thus, the substrate sheet for thin film semiconductor device
of the present invention comprises; a base layer of insulation
materials, a thin film layer of semiconductor formed on the base
layer, a plurality of single-crystalline semiconductor rains formed
in the thin film layer of semiconductor and, said plurality of
single-crystalline semiconductor grains being arranged in a
regulated configuration such as a matrix-arrayed configuration in
the tin film layer of semiconductor.
[0014] The film semiconductor device of the present invention
comprises; a base layer of insulation materials, a thin film layer
of semiconductor formed on the base layer, a plurality of
single-crystalline semiconductor grains formed in the thin film
layer of semiconductor, said plurality of single-crystalline
semiconductor grains being arranged in a regulated configuration
such as a matrix-arrayed configuration and, each of said
single-crystalline semiconductor grains being equipped with an
electric circuit comprising a gate electrode, a source electrode
and a drain electrode.
[0015] The method for producing a substrate sheet for thin film
semiconductor devices according to the present invention comprises
following steps; namely,
[0016] (a) forming a thin film semiconductor layer of
non-single-crystalline semiconductor such as amorphous or
polycrystalline semiconductor on a base layer of insulation
materials and,
[0017] (b) crystallizing or recrystallizing said
non-single-crystalline semiconductor to produce a plurality of
single-crystalline semiconductor grains by irradiating it with
energy beams, said irradiation being carried out so that irradiated
points to which maximum irradiation intensity is given and
irradiated points to which minimum irradiation intensity is given
are arranged in a regulated configuration such as a matrix-arrayed
configuration.
[0018] The process for producing a thin film semiconductor device
of the present invention comprises following steps; namely,
[0019] (a) forming a thin film semiconductor layer of amorphous or
polycrystalline semiconductor on a base layer of insulation
materials,
[0020] (b) crystallizing or recrystallizing said amorphous or
polycrystalline semiconductor to produce a plurality of
single-crystalline semiconductor grain by irradiating it with
energy beams, said irradiation being carried out so that irradiated
points to which maximum irradiation intensity is given and
irradiated points to which minimum irradiation intensity is given
are arranged in a regulated configuration such as a matrix-arrayed
configuration,
[0021] (c) forming a gate electrode on each of single-crystalline
grains in the thin film semiconductor layer, which has been
produced by said step (b) and,
[0022] (d) fabricating an electric circuit in each of said
single-crystalline semiconductor grains by forming a source
electrode and a drain electrode therein.
BRIEF DESCRIPTION OF DRAWINGS
[0023] FIG. 1 is pattern diagrams showing steps of one embodiment
of the process according to the present invention for manufacturing
a thin film semiconductor device.
[0024] FIG. 2 is a pattern diagram for illustrating one embodiment
of distribution state energy beam intensity in two-dimensional
directions in the irradiation step according to the process of the
present invention.
[0025] FIG. 3 is a pattern diagram illustrating a profile of
variation of energy beam intensity between a maximum value and a
minimum value in the process according to the present
invention.
[0026] FIG. 4 is a pattern diagram illustrating an alignment state
of single crystalline grains after finishing the irradiation of
energy beams in the process according to the present invention.
[0027] FIG. 5 is the pattern diagrams illustrating embodiments of
the positional relationship of electrodes with crystal grams in the
thin film semiconductor device of the present invention.
[0028] FIG. 6 is a pattern diagram illustrating the positional
relationship of electrodes with crystal grains in the thin film
semiconductor devices.
[0029] FIG. 7 is a pattern diagram illustrating the pattern of
configuration of maximum intensity irradiation points and minimum
intensity irradiation points such as mentioned in FIGS. 2 through
4, with a three-dimensional model pattern.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
[0030] In the thin film semiconductor device of the present
invention, it is preferred to use a glass sheet hag a strain point
not exceeding 700.degree. C. as the material of base layer of
substrate sheet. But, it is possible to use various kinds
insulation materials other than glass, for example, ceramics or
plastic films having appropriate heat resistance.
[0031] On the above base layer, a thin film of semiconductor in
which single crystalline semiconductor grains are arranged in a
regulated arrangement mode such as a matrix-arrayed mode is formed.
The formation of the thin film layer is carried out by depositing a
layer of semiconductor of non-single crystalline character on the
base layer, and then, by changing the deposited layer to a layer of
polycrystalline semiconductor which includes large size crystal
grains, by means of irradiation of energy beams such as er laser
beam.
[0032] As the semiconductor of non-single crystalline character,
amorphous semiconductor or polycrystalline semiconductor consisting
of small size polycrystalline grains may be used. By the process
according to the present invention, any type of the above
semiconductor can be changed to a thin film semiconductor of the
preset invention, by crystallizing or recrystallizing them. It is
desired that the thickness of thin film semiconductor layer is 10
through 200 nm, especially 50 through 150 nm.
[0033] Usually, when a semiconductor layer of the above non-single
crystalline character is formed on the base layer a thin control
layer for adjusting heat-conduction and crystallization-orientation
consisting of such materials as silicon oxide, silicon nitride
(SiNx) is formed between the base layer and the semiconductor
layer. This layer has such functions as to block the diffusion of
impurities such as glass components from the base layer to the
semiconductor layer and to bring the intentional uniformity of heat
distribution of the semiconductor layer for controlling the
orientation of crystals. The thickness thereof is desired to be 20
through 1000 nm, especially 200 through 300 nm.
[0034] It is also usual to form the second control layer for
adjusting heats conduction and crystallization further on the above
non-single crystalline semiconductor layer (the first control
layer). This second control layer has a function same as the first
control layer, namely, to bring the uniformity of heat distribution
and to control the orientation of crystals in the semiconductor
layer in the process of crystallization by irradiation. Materials
such as silicon-oxide, silicon-nitride, silicon-oxi-nitride or
silicon-carbonate (SiC) can be used therefor. The thickness of the
layer is desired to be 50 through 500 nm, especially 100 through
800 nm.
[0035] When the above two control layers are formed, the thin film
semiconductor layer is formed between the two control layers. In
this case, firstly the material of the first control layer is
deposited as a thin M1 on the base layer of insulation material,
then, the material of thin film of non-single crystalline
semiconductor is deposited on the first control layer, and further,
the material of the second control layer is deposited on the above
semiconductor layer. Thereafter, the irradiation of energy beams
from the upper side is carried out to crystallize or recrystallize
the layer of non-single crystalline material.
[0036] Now referring to (a) through (d) in FIG. 1, which shows an
embodiment of each stages of the process according to the present
invention, (a) shows the first stage of deposition of layers, where
the first control layer 20 for adjusting heat-conduction and
crystallization is deposited on the base layer 10, and non-single
crystalline layer 30 of amorphous or polycrystalline semiconductor
is deposited on the first control layer 20. Further, second control
layer 40 is deposited on the non-single crystalline layer 30.
[0037] As shown in (b), non-single crystalline layer 30 shown in
(a) is changed to a layer consisting of single-crystalline area 50
and non-single crystalline area 51, by irradiation of energy
beams.
[0038] It is of course that (b) shows the sectional pattern view of
one single-crystalline area and a substrate sheet of the present
invention comprises of a plurality of such single-crystalline
semiconductor area.
[0039] Next, as shown in (c), gate electrode 60 is formed on the
substrate sheet and, source area 70 and drain area 71 are formed in
the single crystalline semiconductor area 50 by implanting donor
impurities 75 such as phosphorous ions there into, using gate
electrode 60 as the implantation-mask.
[0040] Further, as shown in (d), an insulation layer 80 of such
material as silicon oxide is deposited on the second control layer
40 and, after perforating contact-holes through the second control
layer 40 and the insulation layer 80, source electrode 90 and drain
electrode 91 are formed by deposition of Aluminum (Al)/Molybdenum
(Mo) into the contact-holes and by patterning it, thereby
completing a thin film semiconductor device.
[0041] In the above step (b), it is preferable to use the excimer
laser irradiation as the means for irradiation. However,
irradiation means other than the excimer laser, for example, pulsed
argon lasers or YAG lasers, may be used.
[0042] In order to obtain a thin film semiconductor layer in which
single crystalline semiconductor grains are arranged in a regulated
alignment mode such as a matrix-arrayed configuration mode by
irradiation of energy beams, the irradiation should be carried out
in such energy intensity distribution mode as in which the
irradiation energy intensity changes successively in
two-dimensional directions between the maximum value and the
minimum value at every predetermined intervals, and maximum points
and minimum points appear one after another in order. In other
words, the irradiation should be carried out so that irradiated
points to which maximum irradiation intensity is given and
irradiated points to which minimum irradiation intensity is given
are arranged in a regulated configuration such as a matrix-arrayed
configuration mode.
[0043] For example, as shown in FIGS. 2, 3 and 7, the irradiation
is carried out in the intensity distribution mode in which
irradiation energy repeats such change as "maximum value
(Emax).fwdarw.minimum value(Emin).fwdarw.maximum value(Emax)"
two-dimensionally (in the x, y both directions) in a rectangle
region of 5.times.5 mm, at every intervals of 10 .mu.m. The above
change of irradiation energy intensity can be realized by bringing
the variation of the irradiation energy intensity distribution,
using a phase shift mask. And, it is desirable that the mode of
change between the maximum value and the minimum value is a
successive change substantially as shown in FIG. 3.
[0044] Determination of the degree of the maximum value and the
minimum value to how much value may be based on the film thickness
of the non crystalline semiconductor layer as well as the film
thickness and the thermal conductivity of the first and the second
control layers. For example, the minimum energy intensity may be
determined to be an intensity which bogs the temperature which
doesn't melt the thin film semiconductor during the irradiation
period, and the maximum value may be determined to be an intensity
which is necessary and sufficient to melt the thin film
semiconductor during the irradiation period. A melting threshold
level (Emth) should be exited between the maximum value (Emax) and
the minimum value (Emin), as shown in the FIG. 3.
[0045] It is of course that the face shape of the irradiation beam
is not limited to a square shape of 5.times.5 mm as mentioned above
and a be venous polygon shapes. Further, the arrangement mode of
maximum value points and minimum value points is not limited to the
rectangular lattice mode and may be various shape modes, for
example, the mode of delta shaped lattice.
[0046] By carrying out the irradiation of energy beams to the thin
firm semiconductor, areas to which the minimum energy intensity
(namely, the intensity less than the melting threshold value) is
irradiated are not completely melted, and therefore, the crystal
nucleus are first formed in this areas. Then, crystals become to
grow in the two dimensional direction towards the ax point, as
shown by arrows mentioned in FIG. 4. On the other hand, in areas of
maximum energy intensity points where the temperature becomes
highest and in areas which become to be region of crystal growth,
the formation of minor size or fine size crystals or boundaries of
large size crystal are resulted, owing to mutual jamming of growing
crystals having different direction of growth. Thus, as the result,
a substrate sheet of thin film semiconductor comprising a plurality
of single crystalline semiconductor, whim are formed at areas
nearby the melting threshold points and each of which bas a crystal
size over 4 .mu.m, can be obtained (cf. FIG. 4).
[0047] The size of the single crystal can be adjusted by varying
the intervals between maximum point of irradiation energy. For
instance, when the irradiation of XeCl excimer laser of 308 nm wave
length is carried out by making the intervals between maximum
intensity point to be 12 .mu.m, a substrate sheet of thin M
semiconductor, in which single crystal grains of nearly 5 .mu.m
size are arranged regularly, can be obtained. It is desirable that,
as the substrate sheet to be used for the thin film semiconductor
device of the present invention, the size of each single crystal
grain in the substrate sheet is not less than 2 .mu.m.
[0048] Then, on each of single crystalline grains in the thin film
semiconductor substrate sheet obtained by the process as mentioned
above, the electrode materials such as Molybdenum-Tungsten alloy
(MoW) is deposited with, an appropriate thickness (for example, 300
nm), thereby forming a gate electrode. Then, after forming a source
area and a drain area respectively using the gate electrode as the
implantation-mask, an isolating-interlayer, with insulation
materials such as silicon oxide, which covers the gate electrode is
formed. Further, after forming contact holes by perforating through
the second control layer at the position above the source area and
the drain area, electrode materials such as aluminium/Molybdenum
are deposited and patterned in the contact hole.
[0049] Thus, as shown in (a) and (b) of FIG. 5, a thin film
semiconductor device, in which one unit electric circuit in each of
single crystals is arranged regulatedly, can be obtained. A thin
film semiconductor device of this type can have a high mobility (or
example, over 300 cm.sup.2/V.sec) exceeding the mobility of
conventional devices in which a substrate sheet comprising
polycrystalline semiconductor film is used.
[0050] It is possible to omit the setting of electrodes for some of
single crystals or to set plural units of circuit for one single
crystal. Further, though the above explanation is described on the
production of a thin film transistor of N-channel type, it is
possible to apply the technique of the present invention to a
transistor of CMOS type, by making partial masking and doping
impurities one after another. It is also possible, instead of using
the second control layer as the gate insulator, to remove the
second control layer by etching after forming the layer of single
crystals, and forming a new gate insulation layer at the removed
portions. "Islands separation", by using etching method before or
after the crystallization process, may be carried out, when there
is a possibility of occurrence of current leakage between adjoining
transistors.
EXAMPLE
[0051] A non-alkali grass sheet, manufactured by Corning Glass
Works, with the outside dimension of 400.times.500 mm, the
thickness of 0.7 m and the strain point of 650.degree. C. was
prepared as the base layer. On the surface of the base layer, the
first control layer of 200 nm thickness for adjusting heat
conduction and crystallization was formed by depositing silicon
oxide (SiO.sub.2) with plasma CVD method On the first control
layer, a layer of amorphous silicon with 50 nm thickness was
deposited, and further, the second control layer of silicon oxide
with 200 nm thickness was a deposited an the amorphous silicon
layer. These forming of layers by the deposition of materials were
carried out successively in a condition not exposed to the
atmosphere.
[0052] Next, after annealing and dehydrating the layer of amorphous
silicon, crystallized it by the irradiation of pulsed excimer laser
beam of 308 nm wave length from the upper side.
[0053] The irradiation was carried out by using and an unit of
excimer laser beam in which the beam face was so shaped as to a
rectangle of 5.times.5 mm and given with intensity distribution
therein by using a phase shift mask. The mode of intensity
distribution was such that 250 thousands of maximum value points
were arrayed at 10 .mu.m intervals in the form of square-lattice,
in the rectangle of 5.times.5 mm. The melting threshold value was
approximately 0.5 J/cm.sup.2, the maximum value and minimum value
of laser beam intensity were 1.8 J/cm.sup.2 and 0.1 J/cm.sup.2
respectively.
[0054] The excimer laser irradiation by the above mode was carried
out towards the whole surface to be irradiated, by moving the
position of irradiation stepwise at 5 mm intervals.
[0055] After finishing irradiation, the irradiated sample was
subjected to be etching treatment by using SECCO etching method and
to observation of the crystal size and the shape of grain-boundary
in the irradiated layer. As the result of observation by using an
electron microscope, it was confirmed that a substrate sheet in
which grains of single crystal of nearly 4 .mu.m size were arrayed
in a matrix lattice form was obtained.
[0056] Next, on the second control layer, a layer of
Molybdenum-Tungsten alloy (MoW) was deposited with 300 nm thickness
by a sputtering method and patterning it, at the position
corresponding to each single crystal, to from a gate electrode.
Then source areas and drain areas were formed by implanting
phosphorous ions using the gate electrode as the mask, and the
interlayer insulator was formed by deposing silicon oxide by a
plasma CVD method. Further, contact holes were perforated in the
second control layer and interlayer insulator and, by forming
alumna films in contact holes, completed a thin film semiconductor
device. It was confirmed that this device shows the average
mobility of 496 cm.sup.2/V.sec.
* * * * *