U.S. patent application number 10/969705 was filed with the patent office on 2005-03-24 for structure and method for eliminating metal contact to p-well of n-well shorts or high leakage paths using polysilicon liner.
Invention is credited to Divakaruni, Ramachandra, Mandelman, Jack, Yang, Haining.
Application Number | 20050062133 10/969705 |
Document ID | / |
Family ID | 32711926 |
Filed Date | 2005-03-24 |
United States Patent
Application |
20050062133 |
Kind Code |
A1 |
Divakaruni, Ramachandra ; et
al. |
March 24, 2005 |
Structure and method for eliminating metal contact to P-well of
N-well shorts or high leakage paths using polysilicon liner
Abstract
A short or high leakage path from a metal contact to a P-well
can occur when a contact via mask is misaligned with an active area
mask, in combination with an overetch into the isolation oxide of
an isolation trench which forms a divot in the isolation oxide,
exposing the contact junction depletion region or even a P-well on
the active area sidewall. This problem is prevented by using an N+
doped polysilicon liner, wherein an outdiffusion of N+ dopant from
the poly liner forms an N+ halo extension in the active area
silicon, providing a reverse biased junction between the metal
contact stud and the P-well. The complementary structure and method
of an N-well and P+ dopant are also disclosed
Inventors: |
Divakaruni, Ramachandra;
(Ossining, NY) ; Mandelman, Jack; (Flatrock,
NC) ; Yang, Haining; (Wappingers Falls, NY) |
Correspondence
Address: |
Steven Fischman, Esq.
Sculty, Scott, Murphy & Presser
400 Garden City Plaza
Garden City
NY
11530
US
|
Family ID: |
32711926 |
Appl. No.: |
10/969705 |
Filed: |
October 20, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10969705 |
Oct 20, 2004 |
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10345468 |
Jan 15, 2003 |
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6831006 |
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Current U.S.
Class: |
257/544 ;
257/E21.507; 257/E21.652; 257/E21.658; 438/597 |
Current CPC
Class: |
H01L 27/10888 20130101;
H01L 27/10864 20130101; H01L 21/76897 20130101 |
Class at
Publication: |
257/544 ;
438/597 |
International
Class: |
H01L 029/00; H01L
021/44 |
Claims
1-8. (Cancelled).
9. A semiconductor device which uses metal contact studs while
preventing shorts from metal contacts to P-well active areas,
wherein each contact via for each metal contact has an adjacent N+
outdiffusion region forming a reverse biased NP junction to the
active area which is self aligning to an interface between the
contact via and the active area to prevent a short or high leakage
path between the contact via and the active area.
10. The semiconductor device of claim 9, further including an N+
doped poly liner formed on sidewalls of each contact via.
11-18. (Cancelled)
19. A semiconductor device which uses metal contact studs while
preventing shorts from metal contacts to N-well active areas,
wherein each contact via for each metal contact has an adjacent P+
outdiffusion region forming a reverse biased PN junction to the
active area which is self aligning to an interface between the
contact via and the active area to prevent a short between the
contact via and the active area.
20. The semiconductor device of claim 19, further including a P+
doped poly liner formed on sidewalls of each contact via.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates generally to a structure and
method for eliminating metal contacts to P-well or N-well shorts
when using metal studs, and more particularly eliminates metal
contacts to P-well shorts when using metal contact studs by using
an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant
from the polysilicon forms an N+ halo extension in the active area
silicon, providing a reverse biased junction between the metal
contact stud and the P-well. The present invention also relates to
the complementary structure and method of eliminating bitline
diffusion to N-well shorts when using metal contact studs.
SUMMARY OF THE INVENTION
[0002] Accordingly, it is a primary object of the present invention
to provide a structure and method for eliminating metal contacts to
P-well or N-well shorts when using metal studs.
[0003] The present invention prevents a short from a metal stud to
a P-well which can occur when a contact mask is misaligned with an
active area (AA) mask, in combination with an overetch into the
isolation oxide of an isolation trench which forms a divot in the
isolation oxide, exposing the bitline junction depletion region or
even a P-well on the active area mask sidewall to the metal stud.
The present invention prevents this problem by using N+ doped
polysilicon studs, wherein an outdiffusion of N+ dopant from the
stud forms an N+ halo extension in the silicon, providing a reverse
biased junction between the stud and the P-well. The present
invention also relates to the complementary structure and method of
eliminating metal contacts to N-well shorts when using metal
studs.
[0004] In accordance with the teachings herein, the present
invention provides the following advantages over the currently
practiced, prior art technology:
[0005] it eliminates metal contacts to P-well or N-well shorts when
using metal contact studs in a semiconductor device such as an
embedded-DRAM or regular DRAM;
[0006] it provides contacts in a support which are self aligned to
M0 metallurgy. This enables smaller support contacts and denser
layouts;
[0007] it requires no additional masks or masking steps.
[0008] The present invention also provides a structure and method
for eliminating metal contacts to N-well shorts when using metal
studs. The present invention prevents a short from a metal stud to
an N-well which can occur when a CB (contact bitline) contact mask
is misaligned with an active area mask, in combination with an
overetch into the isolation oxide of an isolation trench which
forms a divot in the isolation oxide, exposing the bitline junction
depletion region or even an N-well on the active area mask sidewall
to the metal stud. The present invention prevents this problem by
using P+ doped polysilicon studs, wherein an outdiffusion of P+
dopant from the stud forms a P+ halo extension in the silicon,
providing a reverse biased junction between the stud and the
N-well.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The foregoing objects and advantages of the present
invention may be more readily understood by one skilled in the art
with reference being had to the following detailed description of
several embodiments thereof, taken in conjunction with the
accompanying drawings wherein like elements are designated by
identical reference numerals throughout the several views, and in
which:
[0010] FIG. 1 illustrates a plan view of a prior art vertical
transistor memory array, and FIG. 1Y is a sectional view along
sectional arrows Y-Y in FIG. 1, and FIGS. 1 and 1Y illustrate a
problem with metal contacts to P-well shorting in the prior
art.
[0011] FIGS. 2 and 2Y are plan and sectional views of a memory
array similar to FIGS. 1 and 1Y, and illustrate that the present
invention incorporates an N+ doped poly liner or layer in the CB
(contact bitline) via.
[0012] FIG. 3 illustrates a plan view of a vertical transistor
memory array which can be generally formed using known prior art
process methods, and FIGS. 3X and 3Y are sectional views through
the memory array of FIG. 3 taken along respective sectional arrows
X-X and Y-Y.
[0013] FIGS. 4 and 4Y correspond generally to FIGS. 3 and 3Y and
illustrate the structure after a bitline contact via is etched in
the DRAM/eDRAM array and is misaligned with the active area P-well,
and FIG. 4S is a sectional view of the supports region on the
peripheral area of the chip at this stage of the process.
[0014] FIGS. 5Y and 5S correspond to FIGS. 4Y and 4S, and
illustrate the structure after the N+ poly liner is deposited, and
an anti-reflecting coating ARC and photoresist are successively
deposited on top of the N+ poly liner.
[0015] FIGS. 6Y and 6S correspond to FIGS. 5Y and 5S, while FIG.
6SP is a top plan view of FIG. 6S and illustrates the vertically
extending line (conductor) of the first metal line mask opening,
while FIGS. 6Y and 6S illustrate the structure after the ARC is
opened by RIE (reactive ion etching) using the photoresist as a
mask in both the array and supports regions of FIGS. 6Y and 6S.
[0016] FIGS. 7Y and 7S show the structure after the N+ poly liner
is etched using the ARC and the photoresist as a mask by an RIE
process in both the array and supports regions of FIGS. 7Y and
7S.
[0017] FIGS. 8Y and 8S illustrate an alternative process wherein
the N+ poly liner is removed from the via sidewalls by an isotropic
poly etch, however leaving the divot still filled with doped poly
silicon.
[0018] FIGS. 9Y and 9S illustrate the structure after the ARC and
photoresist are stripped by ashing.
[0019] FIGS. 10Y and 10S illustrate the structure after the first
metal line mask pattern is formed by RIE using the patterned N+
poly liner as a protective hard mask.
[0020] FIG. 11SP is a top plan view of the supports region similar
to FIG. 6SP, and illustrates a vertically extending line opening
(for a conductor) in the first metal line (M0) mask, and also
illustrates a rectangular opening CS PR (contact to support
photoresist) in a mask which is wider than the vertically extending
line opening in the M0 mask, which compensates for any misalignment
as shown in FIG. 11S.
[0021] FIGS. 12Y, 12S and 12SP illustrate the structure after the
formation of the contact vias in the array and supports regions and
the formation of the lines connecting the vias.
DETAILED DESCRIPTION OF THE INVENTION
[0022] The use of metal (e.g. tungsten) bitline contact studs is
highly desirable for many semiconductor device technologies, such
as DRAM technologies, particularly embedded-DRAM technologies, to
reduce electrical resistance and to promote high speed charge
transfer and signal development. However, a frequent occurrence of
high junction leakage between metal contacts and P-wells has been
observed when metal contact studs have been employed.
[0023] FIG. 1 illustrates a plan view of a prior art vertical
transistor memory array, and FIG. 1Y is a sectional view along
sectional arrows Y-Y in FIG. 1, and FIGS. 1 and 1Y illustrate a
problem with metal contacts to P-well shorting in the prior art.
FIG. 1 illustrates a memory array having a plurality of horizontal
wordlines WL, a plurality of vertical active areas AA (silicon),
and a top poly DT. FIG. 1Y is a sectional view and shows a top
layer of tetraethylorthosilicate (TEOS), a layer of boron
phosphorous doped silicate glass (BPSG), a layer of heavily doped
N+ XA above an active area AA of a P-well, isolation trenches IT
formed of isolation oxide, and a tungsten CB stud in a bitline
contact CB via which is misaligned to the right with respect to the
AA P-well.
[0024] FIGS. 1 and 1Y show that a short from a metal contact to a
P-well is created when a CB bitline contact mask is misaligned with
an active area AA mask, in combination with an overetch into the
isolation oxide of an isolation trench IT. The overetch forms a
divot 12 in the isolation oxide, exposing the bitline junction
depletion region or even a P-well on the active area AA mask
sidewall to the metal bitline.
[0025] The present invention prevents this problem from occurring
by using N+ doped polysilicon studs, since an outdiffusion of N+
dopant from the stud forms an N+ halo extension in the silicon,
providing a reverse biased junction between the stud and the
P-well.
[0026] FIGS. 2 and 2Y are plan and sectional views of a memory
array similar to FIGS. 1 and 1Y, and illustrate that the present
invention incorporates an N+ doped poly liner or layer in the CB
via.
[0027] FIG. 2Y illustrates how the N+ doped poly liner fills the
divot and forms a local N+ outdiffusion region. The poly liner does
not have to completely fill the divot since the N+ doped poly liner
also prevents the metal from contacting a sidewall of the active
area.
[0028] A variation of this structure can remove the N+ doped poly
liner from the walls of the CB via by using an isotropic etch,
leaving N+ doped poly in the divot.
[0029] FIG. 3 illustrates a plan view of a vertical transistor
memory array which can be generally formed using known prior art
process methods, and FIGS. 3X and 3Y are sectional views through
the memory array of FIG. 3 taken along respective sectional arrows
X-X and Y-Y. FIGS. 3, 3X and 3Y illustrate a top layer of
tetraethylorthosilicate (TEOS), a layer of boron phosphorous doped
silicate glass (BPSG), a gate conductor (GC) Cap (e.g. silicon
nitride), GC metal (e.g. tungsten), GC spacer (e.g. silicon
nitride), GC poly DT, a layer of array top oxide, a layer of
heavily doped N+ XA above an active area (AA) P-well, and isolation
trenches (IT). FIG. 3X is illustrated only to show the structure of
the vertical transistor array, and not to show the structure of the
present invention.
[0030] In the following explanations of the Figures, unless
otherwise noted, Figure n corresponds to a top plan view of the
structure similar to FIG. 3 at different stages of the production
process, Figure nY corresponds to a sectional view of the structure
taken along sectional arrows Y-Y similar to FIG. 3Y at different
stages of the production process, Figure nS corresponds to a
sectional view of the supports (S) region on the peripheral area of
the chip at different stages of the production process, and Figure
nSP corresponds to a top plan (P) view of the supports (S) region
at different stages of the production process.
[0031] FIGS. 4 and 4Y correspond generally to FIGS. 3 and 3Y, and
illustrate the structure after a bitline contact via 42 is etched
in the DRAM/eDRAM array and is misaligned with the active area
P-well. As a result of the misalignment, a divot 44 is formed on
the side of the AA P-well after the contact via 42 is etched. The
divot 44 is illustrated in the sectional view 4Y and shown as a
shadowed region in the plan view of FIG. 4.
[0032] Pursuant to the present invention, after the contact via is
etched, a layer or liner of N+ doped poly silicon 46 is deposited
on the memory array and in the contact via and divot. As the wafer
is annealed at elevated temperatures during the followed process
steps, the dopant out-diffuses into the AA P-well, forming an N+
outdiffusion region 48. The interface of the N+ outdiffusion region
48 with the AA forms a reverse biased N-P junction which is self
aligning to the interface of the bitline contact via and the AA,
which prevents a short from the metal contact to the AA P-well.
[0033] FIG. 4S is a sectional view of the supports region on the
peripheral area of the chip at this stage of the process, which is
illustrated to demonstrate some of the advantages of the present
invention as explained in greater detail hereinbelow.
[0034] FIGS. 5Y and 5S correspond to FIGS. 4Y and 4S, and
illustrate the structure after an anti-reflective coating ARC and
photoresist are successively deposited on top of the N+ poly liner.
The first metal line mask (M0) pattern is then formed in the
photoresist on the array region of FIG. 5Y and in the supports
region of FIG. 5S, with the ARC preventing light from being
reflected and protecting the underlying structure.
[0035] FIGS. 6Y and 6S correspond to FIGS. 5Y and 5S, while FIG.
6SP is a top plan view of FIG. 6S and illustrates the vertically
extending line (conductor) of the M0 mask opening. FIGS. 6Y and 6S
illustrate the structure after the M0 ARC is opened by RIE
(reactive ion etching), using the M0 photoresist as a mask in both
the array and supports regions of FIGS. 6Y and 6S.
[0036] FIGS. 7Y and 7S show the structure after the N+ poly liner
is etched using the M0 ARC and the M0 photoresist as a mask by a
RIE process in both the array and support regions of FIGS. 7Y and
7S.
[0037] FIGS. 8Y and 8S illustrate an alternative process wherein
the N+ poly liner 36 is removed from the via sidewalls by an
isotropic poly etch, however leaving the divot still filled with
doped poly silicon, with the wider CB tungsten stud (because of the
removed N+ poly liner) providing improved conductivity and lowered
resistance. Moreover, the N+ poly liner can react with the CB
tungsten to form tungsten silicide.
[0038] FIGS. 9Y and 9S illustrate the structure after the M0 ARC
and M0 photoresist are stripped by ashing.
[0039] FIGS. 10Y and 10S illustrate the structure after the M0
pattern is formed by RIE using the patterned N+ poly liner as a
protective hard mask. The RIE process is selective to the oxide
etch. Note in FIG. 10S that the TEOS is only half etched in the
supports area.
[0040] FIG. 11SP is a top plan view of the supports region similar
to FIG. 6SP, and illustrates a vertically extending line opening
(for a conductor) in the M0 mask. FIG. 11SP also illustrates a
rectangular opening CS PR (contact to support photoresist) in a
mask which is wider than the vertically extending line opening in
the M0 mask, which compensates for any misalignment as shown in
FIG. 11S. The contact via is patterned and etched in the supports
region using known process methods. The array is masked using
photoresist, and after the contact via is etched, the photoresist
is stripped. The N+ poly liner functions as a hard mask which
limits the contact via opening only within the M0 mask pattern.
Accordingly, the contact via is thus self aligned to the M0 mask
pattern, which allows denser patterning in the supports area. The
CS via is thus aligned to the Si substrate.
[0041] FIGS. 12Y, 12S and 12SP illustrate the structure after the
formation of the contact vias in the array and in the supports and
the formation of the lines connecting the vias. In this process,
Ti/TiN liner and W metal are deposited using known methods. The
wafer is then CMPed (chemical mechanical polished) to remove excess
W metal and Ti/TiN liner from the wafer surface (damascene
process), leaving conducting metal in the lines, supports and
array. The wafer is then processed for BEOL wirings using art known
methods.
[0042] The present invention also provides a structure and method
for eliminating metal contacts to N-well shorts when using metal
studs. The present invention prevents a short from a metal stud to
an N-well which can occur when a CB bitline contact mask is
misaligned with an active area mask, in combination with an
overetch into the isolation oxide of an isolation trench which
forms a divot in the isolation oxide, exposing the bitline junction
depletion region or even an N-well on the active area mask sidewall
to the metal stud. The present invention prevents this problem by
using P+ doped polysilicon studs, wherein an outdiffusion of P+
dopant from the stud forms a P+ halo extension in the silicon,
providing a reverse biased junction between the stud and the
N-well. The process steps of this embodiment are complementary
copies of the steps of FIGS. 2-12.
[0043] The same problem may be present, but has not yet been
identified, in vertical MOSFETs. In vertical MOSFET arrays, the
storage node diffusion is buried, enabling the use of metal bitline
contacts with very low junction leakage. Accordingly, the present
invention can possibly be used to improve on a process not even
considered by the state of the art.
[0044] While several embodiments and variations of the present
invention are described in detail herein, it should be apparent
that the disclosure and teachings of the present invention will
suggest many alternative designs to those skilled in the art.
* * * * *