U.S. patent application number 10/654038 was filed with the patent office on 2005-03-03 for apparatus and method for high density multi-chip structures.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Farrar, Paul A..
Application Number | 20050046034 10/654038 |
Document ID | / |
Family ID | 34218000 |
Filed Date | 2005-03-03 |
United States Patent
Application |
20050046034 |
Kind Code |
A1 |
Farrar, Paul A. |
March 3, 2005 |
Apparatus and method for high density multi-chip structures
Abstract
Devices and methods are described including a multi-chip
assembly. Embodiments of multi-chip assemblies are provided that
uses both lateral connection structures and through chip connection
structures. One advantage of this design includes an increased
number of possible connections. Another advantage of this design
includes shorter distances for interconnection pathways, which
improves device performance and speed.
Inventors: |
Farrar, Paul A.; (Bluffton,
SC) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
34218000 |
Appl. No.: |
10/654038 |
Filed: |
September 3, 2003 |
Current U.S.
Class: |
257/777 ;
257/E25.011 |
Current CPC
Class: |
H01L 2225/06551
20130101; H01L 23/5226 20130101; H01L 2225/06524 20130101; H01L
2924/0002 20130101; H01L 2225/06527 20130101; H01L 25/18 20130101;
H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L 25/0657
20130101; H01L 25/0652 20130101 |
Class at
Publication: |
257/777 |
International
Class: |
H01L 023/48 |
Claims
What is claimed is:
1. A multi-chip assembly, comprising: a number of chips, including:
at least one memory chip; at least one logic chip; a number of chip
edge connection structures adapted to couple selected chips in the
number of chips; and a number of through chip connection structures
adapted to couple selected chips in the number of chips.
2. The multi-chip assembly of claim 1, wherein the number of chips
are formed substantially into a cube assembly.
3. The multi-chip assembly of claim 2, wherein at least one logic
chip is attached to an external side of the cube assembly.
4. The multi-chip assembly of claim 1, further including a polymer
insulation layer between at least two chips in the number of
chips.
5. The multi-chip assembly of claim 4, wherein the polymer
insulation layer includes a polyimide insulation layer.
6. The multi-chip assembly of claim 4, wherein the polymer
insulation layer includes cells of a gaseous component within the
layer.
7. The multi-chip assembly of claim 4, wherein the polymer
insulation layer is a hydrophilic polymer.
8. The multi-chip assembly of claim 1, further including a number
of corner connections that connect at least two chips that are
oriented at an angle to each other.
9. A multi-chip assembly, comprising: a number of chips, including:
at least one memory chip; at least one logic chip; a number of chip
edge connection structures adapted to couple selected chips in the
number of chips; and a number of through chip coaxial connections
adapted to couple selected chips in the number of chips.
10. The multi-chip assembly of claim 9, wherein the number of chips
are formed substantially into a cube assembly.
11. The multi-chip assembly of claim 10, wherein at least one logic
chip is attached to an external side of the cube assembly.
12. The multi-chip assembly of claim 9, further including a foamed
polymer insulation layer between at least two chips in the number
of chips.
13. The multi-chip assembly of claim 12, wherein the foamed polymer
insulation layer includes a polynorbornene insulation layer.
14. The multi-chip assembly of claim 12, further including a
hydrophilic layer attached to the foamed polymer insulation
layer.
15. A multi-chip assembly, comprising: a number of chips,
including: at least one memory chip; at least one logic chip; a
number of chip edge connection structures adapted to couple
selected chips in the number of chips; and a number of through chip
optical waveguide connections adapted to couple selected chips in
the number of chips.
16. The multi-chip assembly of claim 15, wherein the number of
chips are formed substantially into a cube assembly.
17. The multi-chip assembly of claim 16, wherein at least one logic
chip is attached to an external side of the cube assembly.
18. The multi-chip assembly of claim 15, further including a foamed
polymer insulation layer between at least two chips in the number
of chips.
19. The multi-chip assembly of claim 18, wherein the foamed polymer
insulation layer includes a hydrophilic polymer.
20. The multi-chip assembly of claim 18, further including a
hydrophilic layer attached to the foamed polymer insulation
layer.
21. The multi-chip assembly of claim 20, wherein the hydrophilic
layer includes methane radicals.
22. An information handling system, comprising: a display; an input
controller; a multi-chip assembly, including a number of chips,
including: at least one memory chip; at least one logic chip; a
number of chip edge connection structures adapted to couple
selected chips in the number of chips; a number of through chip
connection structures adapted to couple selected chips in the
number of chips; and a bus connecting the display, the input
controller, and the multi-chip assembly.
23. The information handling system of claim 22, wherein the number
of chips are formed substantially into a cube assembly.
24. The information handling system of claim 23, wherein at least
one logic chip is attached to an external side of the cube
assembly.
25. The information handling system of claim 24, wherein at least
one logic chip includes a processor chip.
26. A method of forming a multi-chip assembly, comprising: forming
a number of chip edge connection structures in selected chips of a
number of chips; forming a number of through chip connection
structures in selected chips of the number of chips; and
interconnecting portions of the number of chips using the chip edge
connection structures and the through chip connection structures,
wherein at least one logic chip and at least one memory chip are
included in the number of chips.
27. The method of claim 26, wherein forming a number of chip edge
connection structures and forming a number of through chip
connection structures includes forming at least one chip edge
connection structure and at least one through chip connection
structure on each chip in the number of chips.
28. The method of claim 26, wherein forming a number of through
chip connection structures includes forming a number of coaxial
conductor structures.
29. The method of claim 26, wherein forming a number of through
chip connection structures includes forming a number of optical
waveguide structures.
30. The method of claim 26, further including forming an insulator
layer between two adjacent chips in the number of chips.
31. The method of claim 30, wherein forming an insulator layer
includes forming a polymer insulator layer that includes a number
of cells of gaseous components.
32. The method of claim 26, wherein interconnecting portions of the
number of chips includes forming the number of chips in a cube
structure.
33. The method of claim 32, wherein interconnecting portions of the
number of chips in the cube structure includes interconnecting a
number of memory chips with at least one logic chip on an outside
face of the cube structure.
34. A method of forming a multi-chip assembly, comprising: forming
a number of chip edge connection structures in selected chips of a
number of chips; forming a number of through chip connection
structures in selected chips of the number of chips; reducing the
thickness of at least one chip in the number of chips; and
interconnecting portions of the number of chips using the chip edge
connection structures and the through chip connection structures,
wherein at least one logic chip and at least one memory chip are
included in the number of chips.
35. The method of claim 34, further including forming an insulator
layer between two adjacent chips in the number of chips.
36. The method of claim 35, further including forming a hydrophilic
layer coupled to an exterior surface of the insulator layer.
37. The method of claim 35, wherein forming an insulator layer
includes forming a polymer insulator layer that includes a number
of cells of gaseous components.
38. The method of claim 37, wherein forming a polymer insulator
layer that includes a number of cells of gaseous components
includes utilizing a supercritical fluid to form the number of
cells of gaseous components.
39. The method of claim 34, wherein interconnecting portions of the
number of chips includes forming the number of chips in a cube
structure.
40. The method of claim 39, wherein interconnecting portions of the
number of chips in the cube structure includes interconnecting a
number of memory chips with at least one logic chip on an outside
face of the cube structure.
41. A method of forming a multi-chip assembly, comprising: forming
a number of chip edge connection structures in selected chips of a
number of chips; forming a number of through chip connection
structures in selected chips of the number of chips; forming an
insulator layer between two adjacent chips in the number of chips,
the insulating layer including cells of a gaseous component; and
interconnecting portions of the number of chips using the chip edge
connection structures and the through chip connection structures,
wherein at least one logic chip and at least one memory chip are
included in the number of chips.
42. The method of claim 41, further including forming a hydrophilic
layer coupled to an exterior surface of the insulator layer.
43. The method of claim 42, wherein forming a hydrophilic layer
coupled to an exterior surface of the insulator layer includes
coupling methane radicals to an exterior surface of the insulator
layer.
44. The method of claim 41, further including reducing the
thickness of at least one chip in the number of chips.
45. The method of claim 41, wherein forming an insulator layer
between two adjacent chips includes utilizing a supercritical fluid
to form the cells of a gaseous component.
46. The method of claim 45, wherein utilizing a supercritical fluid
to form the cells of a gaseous component includes utilizing
supercritical carbon dioxide to form the cells of a gaseous
component.
47. A multi-chip assembly, comprising: a number of chips,
including: at least one memory chip; at least one logic chip; means
for coupling edges of selected chips in the number of chips; and
means for coupling through a thickness of selected chips in the
number of chips.
48. The multi-chip assembly of claim 47, wherein the means for
coupling edges of selected chips in the number of chips includes
metal traces.
49. The multi-chip assembly of claim 47, wherein the means for
coupling through a thickness of selected chips in the number of
chips includes coaxial conductors.
50. The multi-chip assembly of claim 47, wherein the means for
coupling through a thickness of selected chips in the number of
chips includes optical waveguides.
Description
TECHNICAL FIELD
[0001] This invention relates to semiconductor chips and chip
assemblies. Specifically this invention relates to multi-chip
structures and methods of forming multi-chip structures.
BACKGROUND
[0002] An ever present goal in the semiconductor industry has been
to decrease the size of devices, and to increase the performance of
devices. However, both of these goals present large technical
hurdles as the two goals are often in conflict with each other.
[0003] As the minimum feature size achievable in semiconductor
manufacturing decreases, the capacitive coupling between adjacent
metal lines becomes a significant impediment to achieving higher
performance. Further, as the minimum feature size decreases the
number of devices potentially achievable in a given area increases,
as a second power function. The number of wiring connections is
increasing at least as rapidly. In order to accommodate the
increased wiring, the chip designer would like to shrink the space
between adjacent lines to the minimum achievable dimension. This
has the unfortunate effect of increasing the capacitive load.
[0004] One way to accommodate the increased wiring and reduce
capacitive load is to substitute lower dielectric constant
materials for the insulating material. A common insulating material
to date is SiO.sub.2, which has a dielectric constant of around 4,
is now used in most very large scale integrated circuit (VLSI)
chips. Another way to accommodate the increased wiring and reduce
capacitive load is to shorten the distance between devices by more
dense packaging.
[0005] What is needed is a device design and method that improves
the performance and reduces the size of a multi-chip assembly.
Specifically, devices and methods are needed that utilize improved
insulating materials. Further, devices and methods are needed that
utilize improved dense packaging configurations.
SUMMARY
[0006] The above mentioned problems such as the need for increased
wiring connections, the need for decreased capacitive coupling, and
the need for more dense packaging are addressed by the present
invention and will be understood by reading and studying the
following specification.
[0007] A multi-chip assembly is shown. In one embodiment, the
multi-chip assembly includes a number of chips. At least one memory
chip and at least one logic chip are included in the number of
chips. The multi-chip assembly also includes a number of chip edge
connection structures used to couple selected chips in the number
of chips. The multi-chip assembly also includes a number of through
chip connection structures used to couple selected chips in the
number of chips.
[0008] An information handling system is also shown. In one
embodiment, the information handling system includes a display and
an input controller. The information handling system also includes
a multi-chip assembly. In one embodiment, the multi-chip assembly
includes a number of chips. At least one memory chip and at least
one logic chip are included in the number of chips. The multi-chip
assembly also includes a number of chip edge connection structures
used to couple selected chips in the assembly of chips. The
multi-chip assembly also includes a number of through chip
connection structures used to couple selected chips in the assembly
of chips. The information handling system also includes a bus
connecting the display, the input controller, and the multi-chip
assembly.
[0009] A method of forming a multi-chip assembly is also shown. The
method includes forming a number of chip edge connection structures
in selected chips of a assembly of chips. The method also includes
forming a number of through chip connection structures in selected
chips of the number of chips. The method further includes
interconnecting portions of the assembly of chips using the chip
edge connection structures and the through chip connection
structures, wherein at least one logic chip and at least one memory
chip are included in the assembly of chips.
[0010] Other embodiments include, but are not limited to operations
such as thinning of the chips used to form the multi-chip assembly,
and including foamed polymers as insulating layers between chips in
the multi-chip assembly.
[0011] These and other embodiments, aspects, advantages, and
features of the present invention will be set forth in part in the
description which follows, and in part will become apparent to
those skilled in the art by reference to the following description
of the invention and referenced drawings or by practice of the
invention. The aspects, advantages, and features of the invention
are realized and attained by means of the instrumentalities,
procedures, and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates an information handling system according
to an embodiment of the invention.
[0013] FIG. 2A illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0014] FIG. 2B illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0015] FIG. 2C illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0016] FIG. 2D illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0017] FIG. 2E illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0018] FIG. 2F illustrates a chip in a stage of manufacture
according to an embodiment of the invention.
[0019] FIG. 2G illustrates a chip and carrier in a stage of
manufacture according to an embodiment of the invention.
[0020] FIG. 2H illustrates a chip and carrier in a stage of
manufacture according to an embodiment of the invention. FIG. 2I
illustrates a chip in a stage of manufacture according to an
embodiment of the invention.
[0021] FIG. 2J illustrates a top view of a chip in a stage of
manufacture according to an embodiment of the invention.
[0022] FIG. 3 illustrates a multi-chip assembly according to an
embodiment of the invention.
[0023] FIG. 4 illustrates another multi-chip assembly according to
an embodiment of the invention.
DETAILED DESCRIPTION
[0024] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention.
[0025] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers, such as silicon-on-insulator (SOI), etc. that have been
fabricated thereupon. Both wafer and substrate include doped and
undoped semiconductors, epitaxial semiconductor layers supported by
a base semiconductor or insulator, as well as other semiconductor
structures well known to one skilled in the art. The term conductor
is understood to include semiconductors, and the term insulator or
dielectric is defined to include any material that is less
electrically conductive than the materials referred to as
conductors.
[0026] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims, along with the full scope of equivalents to which such
claims are entitled.
[0027] An example of an information handling system such as a
personal computer is included to show an example of a high level
device application for the present invention. FIG. 1 is a block
diagram of an information handling system 1 incorporating at least
one multi-chip assembly 4 in accordance with one embodiment of the
invention. Information handling system 1 is merely one example of
an electronic system in which the present invention can be used.
Other examples, include, but are not limited to personal data
assistants (PDA's), cellular telephones, aircraft, satellites,
military vehicles, etc.
[0028] In this example, information handling system 1 comprises a
data processing system that includes a system bus 2 to couple the
various components of the system. System bus 2 provides
communications links among the various components of the
information handling system 1 and can be implemented as a single
bus, as a combination of busses, or in any other suitable
manner.
[0029] Multi-chip assembly 4 is coupled to the system bus 2.
Multi-chip assembly 4 can include any circuit or combination of
circuits. In one embodiment, multi-chip assembly 4 includes a
processor 6 which can be of any type. As used herein, "processor"
means any type of computational circuit, such as but not limited to
a microprocessor, a microcontroller, a graphics processor, a
digital signal processor (DSP), or any other type of processor or
processing circuit.
[0030] In one embodiment, a memory chip 7 is included in the
multi-chip assembly 4. Those skilled in the art will recognize that
a wide variety of memory chips may be used in the multi-chip
assembly 4. Acceptable types of memory chips include, but are not
limited to Dynamic Random Access Memory (DRAMs) such as, SDRAMs,
SLDRAMs, RDRAMs and other DRAMs. Static Random Access Memory
(SRAMs), including VRAMs and EEPROMs, may also be used in the
implementation of the present invention.
[0031] In one embodiment, additional logic chips 8 other than
processor chips are included in the multi-chip assembly 4. An
example of a logic chip 8 other than a processor includes an analog
to digital converter. Other circuits on logic chips 8 such as
custom circuits, an application-specific integrated circuit (ASIC),
etc. are also included in one embodiment of the invention.
[0032] Information handling system 1 can also include an external
memory 11, which in turn can include one or more memory elements
suitable to the particular application, such as one or more hard
drives 12, and/or one or more drives that handle removable media 13
such as floppy diskettes, compact disks (CDs), digital video disks
(DVDs), and the like.
[0033] Information handling system 1 can also include a display
device 9 such as a monitor, additional peripheral components 10,
such as speakers, etc. and a keyboard and/or controller 14, which
can include a mouse, trackball, game controller, voice-recognition
device, or any other device that permits a system user to input
information into and receive information from the information
handling system 1.
[0034] FIG. 2A shows a chip 200 in a stage of processing. The chip
200 includes a semiconductor substrate 210. In one embodiment, the
semiconductor substrate 210 includes silicon. Other suitable
semiconductor substrates 210 include alternate semiconducting
materials such as gallium arsenide, or composite substrate
structures such as silicon-on-insulator structures.
[0035] A number of devices 220 are shown in schematic form, located
on or within the substrate 210. One common device 220 includes a
transistor, however the invention is not so limited. In one
embodiment, devices 220 further include devices such as diodes,
capacitors, etc. A number of through chip connection structures 230
is also shown. In one embodiment, the through chip connection
structures 230 are formed using a preferential etching process such
as anodic etching to create a through chip channel with a high
aspect ratio. In one embodiment, the channels are insulated by
oxidation and later filled with a conductor such as a metal fill
material to conduct signals through the chip 200. In one
embodiment, the metal fill material includes aluminum metal.
[0036] In one example of anodic etching, a bottom surface of the
substrate 210 is coupled to voltage source by a positive electrode.
Further, a negative electrode is coupled to a voltage source and is
placed in a bath of 6% aqueous solution of hydrofluoric acid (HF)
on a surface of the substrate 210.
[0037] In operation, the anodic etch etches high aspect ratio holes
through substrate 210 at the location of etch pits. The voltage
source is turned on and provides a voltage across positive and
negative electrodes. Etching current flows from the surface to the
positive electrode. This current forms the high aspect ratio holes
through the substrate 210. An anodic etching process is described
in V. Lehmann, The Physics of Macropore Formation in Low Doped
n-Type Silicon, J. Electrochem. Soc., Vol. 140, No. 10, pp.
2836-2843, October 1993, which is incorporated herein by
reference.
[0038] In one embodiment, at least one through chip connection
structure 230 includes a coaxial conductor 232. In one embodiment,
using methods such as anodic etching, the connection structures 230
and/or coaxial conductors 232 have an aspect ratio in the range of
approximately 100 to 200. Conventionally, a semiconductor wafer
used to form an integrated circuit has a thickness in the range of
approximately 500 to 1000 microns. Thus, the through chip
connection structures 230 and coaxial conductors 232 can be
fabricated with a width that is in the range from approximately 2.5
microns up to as much as approximately 10 microns. Even smaller
through chip connections can be made in chips which are to be
produced from wafers which are to be thinned after completion of
the semiconductor processing. In this case, the small holes are
processed, including the appropriate filling, to a depth which
equals the thickness of the wafer after thinning. The wafers are
thinned and connections are then made to the exposed through
connections.
[0039] Coaxial conductors 232 include a center conductor 238 that
is surrounded by insulator, e.g., oxide, 236. Further, outer
conductor 234 surrounds insulator 236. Coaxial conductor 232 is
shown in cross section in FIG. 2A. Outer conductor 234 comprises,
for example, a metal layer that is deposited within a high aspect
ratio via. Alternatively, outer conductor 234 may comprise a
portion of the substrate 210 that has been doped with impurities to
render it conductive.
[0040] In one embodiment, at least one through chip connection
structure 230 includes an optical waveguide. One embodiment of an
optical waveguide includes a reflective layer that is formed on
inner surface of high aspect ratio holes. In one embodiment, the
reflective layer includes a metallic mirror that is deposited with
a self-limiting deposition process. This produces a reflective
surface for an optical waveguide that is substantially uniform. In
one embodiment, the optical waveguide has a center void that is
essentially filled with air.
[0041] A two-step, selective process is used in one embodiment to
deposit tungsten as a portion of the reflective layer. This is a
low-pressure chemical vapor deposition (LPCVD) process. In this
process, atoms in the substrate 210, e.g., silicon, are replaced by
tungsten atoms in a reaction gas of WF.sub.6. This is referred to
as a "silicon reduction process." The limiting thickness of this
process is approximately 5 to 10 nanometers. This thickness may not
be sufficient for a reflective layer. Thus, a second reduction
process can be used to complete the deposition of tungsten. This
second reduction step uses silane or polysilane and is thus
referred to as a "silane reduction." The silane reduction process
also uses WF.sub.6. In one embodiment, when tungsten is used for
the reflective layer, a thin film of a material with a higher
reflectivity is deposited on the tungsten material. For example, an
aluminum film can be deposited at low temperature, e.g., in the
range from 180.degree. to 250.degree. Celsius.
[0042] In one embodiment, several varieties of through chip
connection structures 230, such as examples decribed above, are
used on a single chip, or within a multi-chip assembly. In one
embodiment, one type of through chip connection structure 230 is
selected and used throughout each single chip 200, or a multi-chip
assembly.
[0043] FIG. 2B shows a first insulator layer 240 attached to the
chip 200 to isolate the number of devices 220 on a surface of the
chip 200. Suitable insulator layers 240 include, but are not
limited to oxides, or polymers such as polyimide.
[0044] In FIG. 2C, a number of vias or contacts 250 are formed
through the first insulator layer 240 to communicate with the
number of devices 220 and the through chip connection structures
230. In one embodiment, a photolithographic process is used to
pattern and remove selected portions of the first insulator layer
240 to form the vias or contacts 250.
[0045] FIG. 2D shows a lateral connection structure 260. The
lateral connection structure 260 is utilized for interconnecting
selected devices 220 and/or connecting selected through chip
connection structures 230. In one embodiment, the lateral
connection structure 260 includes a metalized layer such as a metal
trace line. In larger scale embodiments, a large network of lateral
connection structures 260 such as metalized lines are used to
connect devices on the chip 200 and form integrated circuits. In
one embodiment, at least one end 262 of a lateral connection
structure 260 is located adjacent to an edge 202 of the chip
200.
[0046] FIG. 2E shows a second insulator layer 270 attached to the
chip 200 to isolate the lateral connection structure or structures
260. In one embodiment, the second insulator layer 270 includes a
polymer layer. In one embodiment, a suitable polymer includes a
polyimide. Some polyimides are able to withstand exposure to
temperatures in a range from approximately 250-620.degree. C.
Endurance of the second insulator layer 270 at high temperatures is
important because in some processes, the chip 200 is exposed to
high processing temperatures before final manufacturing is
complete. Suitable polyimides that posess a variety of physical
properties include, but are not limited to, Type I, Type III, and
Type V polyimides.
[0047] Other suitable polymeric materials include, for example,
parylene, polynorbornenes and fluorinated polymers. Parylene-N has
a melting point of 420.degree. C., a tensile modulus of 2.4 GPa,
and a yield strength of 42 MPa. One class of polynorbornene
includes Avatrel.TM. polymer available from BF Goodrich, Cleveland,
Ohio, USA. In one embodiment, silane is added to polynorbornenes to
further lower the dielectric constant.
[0048] In addition to polymeric matrix materials, aerogels, such as
silica aerogel, may be utilized to provide porous insulating
material of the various embodiments. Aerogels are generally a gel
material that forms a porous matrix when liquid or solvent in the
gel is replaced by air or another gaseous component. Aerogels
generally experience only minimal volumetric change upon such
curing.
[0049] For embodiments that include a polymeric second insulator
layer 270, the polymeric material is generally cured, or
crosslinked, following formation. For one embodiment, curing can
include an optional low temperature bake to drive off most of the
solvents that may be present in the polymer prior to crosslinking.
Other conventional polymers can be cured by exposing them to
visible or ultraviolet light. Still other conventional polymers can
be cured by adding curing (e.g., crosslinking) agents to the
polymer.
[0050] FIG. 2F shows a number of connection structures 280 formed
through the second insulator layer 270 to complete a signal pathway
for the through chip connection structures 230. As shown in FIG.
2F, the chip 200 now contains at least two types of connection
structures. One type includes the through chip connection
structures 230, which are designed to transmit signals
substantially along direction 272. Another type includes the
lateral connection structures 260, which are designed to transmit
signals substantially along direction 262.
[0051] In one embodiment, selected through chip connection
structures 230 are isolated from lateral connection structures 260,
and only transmit signals through the chip 200. In one embodiment,
selected through chip connection structures 230 are coupled to
selected lateral connection structures 260 to communicate signals
both through the chip 200 and laterally across the chip 200. One of
ordinary skill in the art, having the benefit of the present
disclosure will appreciate that a number of interconnection designs
and combinations incorporating both through chip connection
structures 230 and lateral connection structures 260 are possible
depending on a given integrated circuit design and multi-chip
assembly design.
[0052] FIG. 2G shows the chip 200 mounted to a carrier 204. In one
embodiment, the carrier 204 is used to facilitate thinning of the
chip 200. A beginning thickness 212 of the chip 200 is indicated.
In one embodiment, the carrier includes a sacrificial silicon
wafer. Various methods are possible for attaching the chip 200 to
the surface of the carrier 204. In one embodiment, the chip 200 is
attached to the carrier using a water soluble epoxy, which
facilitates removal of the chip 200 at a later stage of
manufacturing. The chip 200 is shown mounted with a backside facing
upwards and exposed for a thinning operation.
[0053] FIG. 2H shows the chip 200 after a thinning process. The
chip 200 has been thinned to a thickness as indicated by 214. Any
of a number of acceptable thinning processes can be used. In one
embodiment, the chip 200 is thinned using chemical mechanical
polishing (CMP) techniques. In one embodiment, a deep implant of p+
carriers is implanted sufficient to a depth within the substrate
210 that is deeper than a maximum depth of the number of devices
220. In one embodiment, the through chip connection structures 230
are formed to a depth that is deeper than the depth of the p+ deep
implant. The thinning process can then be set to stop at the depth
from the backside of the chip 200 where the p+ layer is contacted.
Using variations of this embodiment, the through chip connection
structures 230 are exposed during the thinning process. Other
embodiments are included that do not use the p+ deep implant and
chip thinning technique.
[0054] In one embodiment, the second insulator layer 270 includes
cells of gaseous components. In one embodiment, an average cell
size is less than 0.1 microns. In one embodiment, as shown in FIG.
2I, a polymer second insulator layer 270 is foamed to form cells of
gaseous components. FIG. 2H shows the second insulator layer 270
with a thickness 274. In one embodiment, the thickness 274 is
approximately 0.7 microns thick. FIG. 21 shows a second thickness
276 of the second insulator layer 270 after a foaming process. The
chip 200 in FIG. 2I is shown without a carrier 204. In one
embodiment, the second thickness 276 is approximately 2.1 microns
thick.
[0055] In one embodiment, the foaming process is performed after
the chip is thinned, as described above, although the invention is
not so limited. The cells function to further reduce the dielectric
constant. An increase in thickness of the second insulator layer
270 also reduces unwanted capacitive effects. Depending on the
process used to foam the polymer in the second insulator layer 270,
the cells may include air, or other gasses such as carbon
dioxide.
[0056] In one embodiment, a supercritical fluid is utilized to
convert at least a portion of the polymeric material, into a foamed
polymeric material. Such use of supercritical fluids facilitates
formation of sub-micron cells in the foamed polymeric material. A
gas is determined to be in a supercritical state (and is referred
to as a supercritical fluid) when it is subjected to a combination
of pressure and temperature above its critical point, such that its
density approaches that of a liquid (i.e., the liquid and gas
states are indistinguishable). A wide variety of compounds and
elements can be converted to the supercritical state in order to be
used to form the second insulator layer 270.
[0057] Suitable supercritical fluids include, but are not limited
to: ammonia (NH.sub.3), an amine (NR.sub.3), an alcohol (ROH),
water (H.sub.2O), carbon dioxide (CO.sub.2), nitrous oxide
(N.sub.2O), a noble gas (e.g., He, Ne, Ar), a hydrogen halide
(e.g., hydrofluoric acid (HF), hydrochloric acid (HCl), hydrobromic
acid (HBr)), boron trichloride (BCl.sub.3), chlorine (Cl.sub.2),
fluorine (F.sub.2), oxygen (O.sub.2) nitrogen (N.sub.2), a
hydrocarbon (e.g., dimethyl carbonate (CO(OCH.sub.3).sub.2),
methane (CH.sub.4), ethane (C.sub.2H.sub.6), propane
(C.sub.3H.sub.8), ethylene (C.sub.2H.sub.4), etc.), a fluorocarbon
(e.g., CF.sub.4, C.sub.2F.sub.4, CH.sub.3F, etc.),
hexafluoroacetylacetone (C.sub.5H.sub.2F.sub.6O.sub.2), and
combinations thereof.
[0058] Although these and other fluids may be used, it is
preferable to have a fluid with a low critical pressure, preferably
below about 100 atmospheres, and a low critical temperature of at
or near room temperature. Further, it is preferred that the fluids
be nontoxic and nonflammable. Likewise, the fluids should not
degrade the properties of the polymeric material. For one
embodiment, supercritical fluid C0.sub.2 is utilized, due to the
relatively inert nature of C0.sub.2 with respect to most polymeric
materials as well as other materials utilized in integrated circuit
fabrication.
[0059] A selected polymer in one embodiment of a second insulator
layer 270 is exposed to the supercritical fluid for a sufficient
time period to foam at least a portion of the polymeric material.
In one embodiment, the chip 200 is placed in a processing chamber,
and the temperature and pressure of the processing chamber are
elevated above the temperature and pressure needed for creating and
maintaining the particular supercritical fluid. After the second
insulator layer 270 is exposed to the supercritical fluid for a
sufficient period of time to saturate the polymeric material with
supercritical fluid, the flow of supercritical fluid is stopped and
the processing chamber is depressurized. Upon depressurization, the
foaming of the polymeric material occurs as the supercritical state
of the fluid is no longer maintained, and cells are formed in the
polymeric material.
[0060] One of ordinary skill in the art, having the benefit of the
present disclosure will recognize that other foaming techniques may
be used in place of or in combination with that described herein in
accordance with the present invention. For example, foams may also
be formed by use of block co-polymers.
[0061] In one embodiment, polymer materials such as embodiments of
the second insulator layer 270, include hydrophilic polymers. The
use of a hydrophilic polymer is advantageous because moisture is
attracted away from metal or semiconductor devices in the chip 200
where water could cause corrosion damage. In one embodiment, in
contrast to choosing a hydrophilic polymer, a hydrophilic treatment
is added to whatever polymer or insulator layer is selected. In one
embodiment, the hydrophilic treatment includes introduction of
methane radicals to a surface of the insulator layer. In one
embodiment, the methane radicals are created using a high frequency
electric field. By utilizing an additional treatment process, the
insulator layer can be selected based on other material properties
such as dielectric constant, and the additional desirable property
of a hydrophilic nature can be added to the chosen material.
[0062] FIG. 2J shows the chip 200 from another angle to further
illustrate possible locations of structures in the chip 200 as
described above. The number of devices 220 are shown, with the
lateral connection structure 260 coupling to the illustrated
devices 220. The lateral connection structure 260 includes an end
262 that is adjacent to a chip edge as described above. The number
of through chip connection structures 230 are shown in various
locations on the chip 200. As described above, selected through
chip connection structures 230 such as individual structure 231 are
coupled to other circuitry such as the lateral connection structure
260. As an example a selected through chip connection structure 230
is shown as a coaxial structure 232. As described above, coaxial
structures 232 are one possible embodiment of through chip
connection structures 230.
[0063] In one embodiment, selected chip connection structures,
including through chip connection structures 230 and lateral
connection structure 260 are coupled to terminal metals to
facilitate later connection to other chips. In one embodiment,
terminal metals include ZrNiCuAu pads and solder applied to
aluminum contact metal.
[0064] FIG. 3 illustrates one example of a multi-chip assembly 300
using embodiments of chips as described in embodiments above. A
number of chips 310 are shown coupled together to form an assembly.
In FIG. 3, the assembly 300 includes a cube like assembly, although
the invention is not so limited. Other geometries of multi-chip
assemblies are possible, such as rectangular assemblies, or other
complex geometries that utilize through chip connection structures
and lateral connection structures are within the scope of the
invention.
[0065] A number of chip edge connections 320 are illustrated. In
one embodiment, the chip edge connections 320 are formed by
removing material from the edges of chips 310 to expose lateral
connection structures as described in embodiments above. In one
embodiment, removing material includes etching back the edges of
the chips 310. A number of chip edge interconnects 330 are also
shown coupling selected chip edge connections 320. In one
embodiment, the chip edge interconnects 330 include metal trace
lines.
[0066] In one embodiment, the number of chips 310 include both
memory chips such as DRAM, SRAM, or flash chips. In one embodiment,
the number of chips 310 also includes at least one logic chip. As
discussed above, logic chips include processor chips, or other
specialized logic chips such as analog to digital converter chips.
In one embodiment, a processor chip is included as a logic chip,
and is located on an external surface of the multi-chip assembly
300. Location on an external surface is advantageous because
cooling is enhanced on external surfaces of the multi-chip assembly
300. Logic chips such as processor chips tend to generate large
amounts of heat compared to memory chips, therefore location of
logic chips on external surfaces is desired. In some embodiments,
multiple logic or processor chips are included, and external
surfaces may not be available for all logic chips. In embodiments
such as these, logic chips may be located internal to the
multi-chip assembly 300.
[0067] Although not visible in FIG. 3, the multi-chip assembly 300
includes chips with both lateral connection structures and through
chip connection structures as described in embodiments above. The
use of both lateral connection structures and through chip
connection structures is advantageous because more pathways are
available for the chips 310 in the multi-chip assembly 300 to
communicate with each other. If only edge connections were used,
the number of connections would be limited to the space on the edge
of the chips. Using embodiments described above, a multi-chip
assembly 300 is able to also utilize through chip connection
structures to increase the number of connections between chips.
[0068] Further, the distance of a connection between selected
regions from one chip to another is significantly reduced using
embodiments described above. In many instances, a connection
pathway directly through the middle of a chip using a through chip
connection is significantly shorter than connecting out to an edge
of one chip, then back into another chip from that chip edge.
Shorter connection pathways lead to increased speed and performance
of multi-chip assemblies 300.
[0069] FIG. 4 shows an embodiment of a multi-chip assembly 400. A
number of chips 410 are shown coupled together to form the assembly
400. In the Figure, the multi-chip assembly 400 is shown attached
to a surface 402 such as a motherboard. A number of chip edge
connections 420 are illustrated. In one embodiment, the chip edge
connections 420 are formed by removing material from the edges of
chips 410 to expose lateral connection structures as described in
embodiments above. In one embodiment, removing material includes
etching back the edges of the chips 410. A number of chip edge
interconnects 430 are also shown coupling selected chip edge
connections 420. In one embodiment, the chip edge interconnects 430
include metal trace lines.
[0070] Similar to embodiments discussed above, in one embodiment at
least one logic chip, such as a processor, is included in the
number of chips 410. In FIG. 4, a logic chip is shown coupled to
the top of the multi-chip assembly 400. A second number of chip
edge interconnects 440 is shown coupling to this logic chip. The
second number of chip edge interconnects 440 illustrate one
possible connection method to connect chips that are orthogonal to
each other. Although the figure illustrates orthogonal chips, other
angles apart from 90 degrees are possible between chips of the
multi-chip assembly 400.
[0071] Also illustrated in FIG. 4 is a corner connection structure
450. In one embodiment, the corner connection structure includes a
first conducting pillar 452, a second conducting pillar 454 and a
solder ball 456. Other embodiments of corner connection structures
are also included within the scope of the invention. Acceptable
devices and methods are described in commonly assigned U.S. Pat.
No. 6,552,424 which is incorporated herein by reference in its
entirety.
Conclusion
[0072] Using devices and methods as described above, a multi-chip
assembly is provided that uses both lateral connection structures
and through chip connection structures. One advantage of this
design includes an increased number of possible connections.
Another advantage of this design includes shorter distances for
interconnection pathways, which improves device performance and
speed. Numerous other advantages are provided by embodiments
described above, including but not limited to: decreased capacitive
coupling from improved isolation structures and materials;
decreased corrosion probability due to hydrophilic materials;
improved cooling due to locations of logic chips; reduced assembly
size due to thinning of chips; etc.
[0073] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. It is to be understood that the above
description is intended to be illustrative, and not restrictive.
Combinations of the above embodiments, and other embodiments will
be apparent to those of skill in the art upon reviewing the above
description. The scope of the invention includes any other
applications in which the above structures and fabrication methods
are used. The scope of the invention should be determined with
reference to the appended claims, along with the full scope of
equivalents to which such claims are entitled.
* * * * *