U.S. patent application number 10/943661 was filed with the patent office on 2005-02-10 for method for making a semiconductor device having a high-k gate dielectric.
Invention is credited to Arghavani, Reza, Chau, Robert, Doczy, Mark.
Application Number | 20050032318 10/943661 |
Document ID | / |
Family ID | 27753118 |
Filed Date | 2005-02-10 |
United States Patent
Application |
20050032318 |
Kind Code |
A1 |
Chau, Robert ; et
al. |
February 10, 2005 |
Method for making a semiconductor device having a high-k gate
dielectric
Abstract
A method for making a semiconductor device is described. That
method comprises forming on a substrate a dielectric layer that has
a dielectric constant that is greater than the dielectric constant
of silicon dioxide. The dielectric layer is modified so that it
will be compatible with a gate electrode to be formed on the
dielectric layer, and then a gate electrode is formed on the
dielectric layer.
Inventors: |
Chau, Robert; (Beaverton,
OR) ; Arghavani, Reza; (Aloha, OR) ; Doczy,
Mark; (Beaverton, OR) |
Correspondence
Address: |
Mark Seeley
c/o BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
7th Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025
US
|
Family ID: |
27753118 |
Appl. No.: |
10/943661 |
Filed: |
September 16, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10943661 |
Sep 16, 2004 |
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10618226 |
Jul 11, 2003 |
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10618226 |
Jul 11, 2003 |
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10082530 |
Feb 22, 2002 |
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6617209 |
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Current U.S.
Class: |
438/287 ;
257/E21.272; 257/E21.274; 257/E21.281 |
Current CPC
Class: |
H01L 21/02181 20130101;
H01L 21/28238 20130101; Y10S 438/974 20130101; H01L 21/28194
20130101; H01L 21/02186 20130101; Y10S 438/906 20130101; H01L
21/3105 20130101; H01L 21/28185 20130101; H01L 29/517 20130101;
H01L 21/02189 20130101; H01L 21/02178 20130101 |
Class at
Publication: |
438/287 |
International
Class: |
H01L 021/336 |
Claims
What is claimed is:
1. A method for making a semiconductor device comprising: forming a
high-k gate dielectric layer on a substrate, the high-k gate
dielectric layer including impurities; removing the impurities from
the high-k gate dielectric layer; and then forming a gate electrode
on the high-k gate dielectric layer.
2. The method of claim 1 further comprising forming a sacrificial
layer on the high-k gate dielectric layer, and transporting the
impurities from the high-k gate dielectric layer to the sacrificial
layer.
3. The method of claim 2 wherein the substrate comprises
silicon.
4. The method of claim 3 wherein the high-k gate dielectric layer
is formed by atomic layer chemical vapor deposition, and is between
about 20 angstroms and about 60 angstroms thick.
5. The method of claim 4 wherein the high-k gate dielectric layer
comprises a material selected from the group consisting of hafnium
oxide, zirconium oxide, titanium oxide, and aluminum oxide.
6. The method of claim 5 wherein the sacrificial layer is between
about 10 angstroms and about 50 angstroms thick.
7. The method of claim 6 wherein the sacrificial layer is annealed
by heating that layer at between about 500.degree. C. and about
1,000.degree. C. for between about 5 minutes and about 20
minutes.
8. The method of claim 7 wherein the sacrificial layer is removed
using a wet etch process that is selective for the sacrificial
layer over the material used to make the high-k dielectric
layer.
9. The method of claim 8 wherein the gate electrode comprises
polysilicon.
10. The method of claim 1 wherein the gate electrode is formed
directly on the high-k gate dielectric layer.
Description
[0001] This is a Divisional Application of Ser. No. 10/618,226
filed Jul. 11, 2003, which is presently pending, and which is a
Continuation Application of Ser. No. 10/082,530 filed Feb. 22,
2002, now U.S. Pat. No. 6,617,209.
FIELD OF THE INVENTION
[0002] The present invention relates to methods for making
semiconductor devices, in particular, semiconductor devices that
include high-k gate dielectric layers.
BACKGROUND OF THE INVENTION
[0003] MOS field-effect transistors with very thin gate dielectrics
made from silicon dioxide may experience unacceptable gate leakage
currents. Forming the gate dielectric from certain high-k
dielectric materials, in place of silicon dioxide, can reduce gate
leakage. Such a dielectric may not, however, be compatible with
polysilicon--the preferred material for making the device's gate
electrode. Placing a thin layer of titanium nitride, which is
compatible with many high-k gate dielectrics, between a high-k gate
dielectric and a polysilicon-based gate electrode may enable such a
dielectric to be used with such a gate electrode. Unfortunately,
the presence of such a layer may increase the transistor's
threshold voltage, which is undesirable.
[0004] Accordingly, there is a need for an improved process for
making a semiconductor device that includes a high-k gate
dielectric. There is a need for such a process in which a
polysilicon-based gate electrode is formed on such a gate
dielectric to create a functional device--without causing
undesirable work function shifts. The method of the present
invention provides such a process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIGS. 1a-1d represent cross-sections of structures that may
be formed when carrying out an embodiment of the method of the
present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0006] A method for making a semiconductor device is described.
That method comprises forming on a substrate a dielectric layer
that has a dielectric constant that is greater than the dielectric
constant of silicon dioxide. That dielectric layer is modified so
that it will be compatible with a gate electrode to be formed on
it. A gate electrode is then formed on the dielectric layer. In the
following description, a number of details are set forth to provide
a thorough understanding of the present invention. It will be
apparent to those skilled in the art, however, that the invention
may be practiced in many ways other than those expressly described
here. The invention is thus not limited by the specific details
disclosed below.
[0007] In an embodiment of the method of the present invention, as
illustrated by FIGS. 1a-1d, dielectric layer 101 is formed on
substrate 100. Substrate 100 may include isolation regions, p-type
wells and n-type wells that have been formed in a bulk silicon or
silicon-on-insulator substructure. Substrate 100 may comprise other
materials--which may or may not be combined with silicon--such as:
germanium, indium antimonide, lead telluride, indium arsenide,
indium phosphide, gallium arsenide, or gallium antimonide. Although
several examples of materials from which substrate 100 may be
formed are described here, any material that may serve as a
foundation upon which a semiconductor device may be built falls
within the spirit and scope of the present invention.
[0008] Dielectric layer 101 comprises a material that has a
dielectric constant that is greater than the dielectric constant of
silicon dioxide. Dielectric layer 101 preferably has a dielectric
constant that is at least about twice that of silicon dioxide,
i.e., a dielectric constant that is greater than about 8. When
serving as the gate dielectric for the semiconductor device,
dielectric layer 101 is a "high-k gate dielectric." Some of the
materials that may be used to make high-k gate dielectrics include:
hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon
oxide, titanium oxide, tantalum oxide, barium strontium titanium
oxide, barium titanium oxide, strontium titanium oxide, yttrium
oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc
niobate. Particularly preferred are hafnium oxide, zirconium oxide,
titanium oxide, and aluminum oxide. Although a few examples of
materials that may be used to form dielectric layer 101 are
described here, that layer may be made from other materials that
serve to reduce gate leakage from the level present in devices that
include silicon dioxide gate dielectrics.
[0009] Dielectric layer 101 may be formed on substrate 100 using a
conventional deposition method, e.g., a conventional chemical vapor
deposition ("CVD"), low pressure CVD, or physical vapor deposition
("PVD") process. Preferably, a conventional atomic layer CVD
process is used. In such a process, a metal oxide precursor (e.g.,
a metal chloride) and steam may be fed at selected flow rates into
a CVD reactor, which is then operated at a selected temperature and
pressure to generate an atomically smooth interface between
substrate 100 and dielectric layer 101. The CVD reactor should be
operated long enough to form a layer with the desired thickness. In
most applications, dielectric layer 101 should be less than about
100 angstroms thick, and more preferably between about 20 angstroms
and about 60 angstroms thick.
[0010] As deposited, dielectric layer 101 will include undesirable
impurities, e.g., hydrogen and/or unreacted metal (represented by
dots in FIG. 1a), which render that layer incompatible with
polysilicon. In the method of the present invention, dielectric
layer 101 is modified so that it will be compatible with a gate
electrode to be formed on it. FIGS. 1a-1c illustrate steps that may
be applied to modify dielectric layer 101. First, sacrificial layer
102 is formed on dielectric layer 101 to generate the structure
represented by FIG. 1a. Sacrificial layer 102 preferably is made
from a material that may getter impurities from dielectric layer
101. An example of a suitable material is titanium nitride. Such a
titanium nitride layer may be formed on dielectric layer 101 using
a conventional CVD or PVD process. In a preferred embodiment, such
a process is used to form a titanium nitride layer that is between
about 10 angstroms and about 50 angstroms thick.
[0011] After sacrificial layer 102 is formed on dielectric layer
101, undesirable impurities are transported from dielectric layer
101 to sacrificial layer 102. When sacrificial layer 102 is made
from titanium nitride and dielectric layer 101 comprises a high-k
gate dielectric layer, impurities may be transported from high-k
gate dielectric layer 101 to titanium nitride layer 102 by
annealing titanium nitride layer 102. Titanium nitride layer 102
may be annealed using a rapid thermal anneal process or by heating
that layer in a furnace at between about 500.degree. C. and about
1,000.degree. C. for between about 5 minutes and about 20
minutes.
[0012] FIG. 1b represents a structure in which undesirable
impurities, e.g., hydrogen and unreacted metal (represented by dots
in FIG. 1b), have been transferred from high-k dielectric layer 101
into titanium nitride layer 102. FIG. 1b is not meant to suggest
that annealing titanium nitride layer 102 will cause all
undesirable impurities, initially present in high-k dielectric
layer 101, to be moved into layer 102. Rather, the annealing step
is performed to cause a sufficient number of those impurities to
move from high-k dielectric layer 101 into titanium nitride layer
102 to modify high-k dielectric layer 101 such that it will be
compatible with a gate electrode to be formed on that layer. Thus,
a method that applies an annealing step, which does not remove
all--or even substantially all--of the undesirable impurities from
high-k dielectric layer 101, may still fall within the spirit and
scope of the present invention.
[0013] After the undesirable impurities have been transported from
dielectric layer 101 to sacrificial layer 102, e.g., by annealing
the sacrificial layer, sacrificial layer 102 is removed. When
sacrificial layer 102 is made from titanium nitride and dielectric
layer 101 comprises a high-k gate dielectric layer, titanium
nitride layer 102 may be removed from high-k gate dielectric layer
101 using a conventional wet etch process, which uses a chemistry
that is selective for titanium nitride over the material used to
form the high-k gate dielectric layer.
[0014] Following the removal of sacrificial layer 102, a gate
electrode may be formed on dielectric layer 101. In a preferred
embodiment, the gate electrode may be formed by initially
depositing polysilicon layer 103 on high-k gate dielectric layer
101--generating the FIG. 1c structure. Polysilicon layer 103 may be
deposited using conventional methods and preferably is between
about 2,000 angstroms and about 4,000 angstroms thick. After
etching both layers 103 and 101 to form the FIG. 1d structure,
using conventional techniques, additional steps that are generally
used to complete the gate electrode (e.g., forming a silicide (not
shown) on the upper part of etched polysilicon structure 104) may
be applied. As such steps are well known to those skilled in the
art, they will not be described in more detail here.
[0015] As described above, a sacrificial titanium nitride layer may
enable a high-k gate dielectric to be used with a polysilicon-based
gate electrode. By forming a titanium nitride layer on a high-k
gate dielectric layer, annealing and then removing that layer to
remove undesirable impurities from the high-k gate dielectric, the
embodiment described above enables the resulting device to benefit
from the temporary presence of the titanium nitride layer without
experiencing the work function shifts that permanent placement of
that layer between the high-k gate dielectric and the gate
electrode may cause. Although the embodiment described above is an
example of a process for modifying a dielectric layer to enable it
to be compatible with a gate electrode, the present invention is
not limited to this particular embodiment, but instead contemplates
other processes for modifying dielectric layers to ensure
compatibility with gate electrodes.
[0016] Although the foregoing description has specified certain
steps and materials that may be used in the method of the present
invention, those skilled in the art will appreciate that many
modifications and substitutions may be made. Accordingly, it is
intended that all such modifications, alterations, substitutions
and additions be considered to fall within the spirit and scope of
the invention as defined by the appended claims.
* * * * *