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name:-0.060918807983398
name:-0.0051860809326172
Arghavani; Reza Patent Filings

Arghavani; Reza

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arghavani; Reza.The latest application filed is for "semiconductor devices including cobalt alloys and fabrication methods thereof".

Company Profile
5.55.59
  • Arghavani; Reza - Scotts Valley CA
  • Arghavani; Reza - Aloha OR
  • Arghavani; Reza - Santa Clara CA
  • Arghavani; Reza - Terrace Aloha OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor devices including cobalt alloys and fabrication methods thereof
Grant 11,380,619 - Koike , et al. July 5, 2
2022-07-05
Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
Grant 11,011,379 - Arghavani , et al. May 18, 2
2021-05-18
Semiconductor Devices Including Cobalt Alloys And Fabrication Methods Thereof
App 20200365192 - KOIKE; Junichi ;   et al.
2020-11-19
Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer
Grant 10,796,995 - Koike , et al. October 6, 2
2020-10-06
Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask
Grant 10,741,405 - Peter , et al. A
2020-08-11
Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
Grant 10,559,468 - Arghavani , et al. Feb
2020-02-11
Capped Ald Films For Doping Fin-shaped Channel Regions Of 3-d Ic Transistors
App 20190385850 - Arghavani; Reza ;   et al.
2019-12-19
Semiconductor Devices Including Cobalt Alloys And Fabrication Methods Thereof
App 20190164896 - KOIKE; Junichi ;   et al.
2019-05-30
Selective Self-aligned Patterning Of Silicon Germanium, Germanium And Type Iii/v Materials Using A Sulfur-containing Mask
App 20180342399 - Peter; Daniel ;   et al.
2018-11-29
Capped Ald Films For Doping Fin-shaped Channel Regions Of 3-d Ic Transistors
App 20180269061 - Arghavani; Reza ;   et al.
2018-09-20
Rare earth metal surface-activated plasma doping on semiconductor substrates
Grant 10,068,981 - Kim , et al. September 4, 2
2018-09-04
Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask
Grant 10,043,672 - Peter , et al. August 7, 2
2018-08-07
Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
Grant 9,997,357 - Arghavani , et al. June 12, 2
2018-06-12
Transistor with threshold voltage set notch and method of fabrication thereof
Grant 9,922,977 - Arghavani , et al. March 20, 2
2018-03-20
Selective Self-aligned Patterning Of Silicon Germanium, Germanium And Type Iii/v Materials Using A Sulfur-containing Mask
App 20170287724 - Peter; Daniel ;   et al.
2017-10-05
Rare Earth Metal Surface-activated Plasma Doping On Semiconductor Substrates
App 20170256622 - Kim; Yunsang ;   et al.
2017-09-07
Capped Ald Films For Doping Fin-shaped Channel Regions Of 3-d Ic Transistors
App 20160379826 - Arghavani; Reza ;   et al.
2016-12-29
Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof
App 20160336318 - Arghavani; Reza ;   et al.
2016-11-17
Method to tune TiO.sub.x stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiO.sub.x/Ti based MIS contact scheme for CMOS
Grant 9,478,411 - Thombare , et al. October 25, 2
2016-10-25
Transistor with threshold voltage set notch and method of fabrication thereof
Grant 9,418,987 - Arghavani , et al. August 16, 2
2016-08-16
Integrated etch/clean for dielectric etch applications
Grant 9,396,961 - Arghavani , et al. July 19, 2
2016-07-19
Integrated Etch/clean For Dielectric Etch Applications
App 20160181117 - Arghavani; Reza ;   et al.
2016-06-23
Method To Tune Tiox Stoichiometry Using Atomic Layer Deposited Ti Film To Minimize Contact Resistance For Tiox/ti Based Mis Contact Scheme For Cmos
App 20160056037 - Thombare; Shruti Vivek ;   et al.
2016-02-25
CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
Grant 9,153,486 - Arghavani , et al. October 6, 2
2015-10-06
Capped Ald Films For Doping Fin-shaped Channel Regions Of 3-d Ic Transistors
App 20150249013 - Arghavani; Reza ;   et al.
2015-09-03
Cvd Based Metal/semiconductor Ohmic Contact For High Volume Manufacturing Applications
App 20140308812 - Arghavani; Reza ;   et al.
2014-10-16
Transistor With Threshold Voltage Set Notch And Method Of Fabrication Thereof
App 20140284722 - Arghavani; Reza ;   et al.
2014-09-25
Transistor with threshold voltage set notch and method of fabrication thereof
Grant 8,759,872 - Arghavani , et al. June 24, 2
2014-06-24
Method of forming flash memory with ultraviolet treatment
Grant 8,501,568 - Balseanu , et al. August 6, 2
2013-08-06
Method of forming a non-volatile memory having a silicon nitride charge trap layer
Grant 8,252,653 - Balseanu , et al. August 28, 2
2012-08-28
Semiconductor on insulator
Grant 8,173,495 - Jin , et al. May 8, 2
2012-05-08
Mixing Energized and Non-Energized Gases for Silicon Nitride Deposition
App 20120009803 - Jung; Kee Bum ;   et al.
2012-01-12
Transistor With Threshold Voltage Set Notch And Method Of Fabrication Thereof
App 20110309447 - Arghavani; Reza ;   et al.
2011-12-22
Oxide etch with NH4-NF3 chemistry
Grant 7,955,510 - Arghavani , et al. June 7, 2
2011-06-07
Semiconductor on Insulator
App 20110039377 - Jin; Been-Yih ;   et al.
2011-02-17
Method For Fabrication Of A Semiconductor Device And Structure
App 20110031997 - Or-Bach; Zvi ;   et al.
2011-02-10
Semiconductor on insulator apparatus
Grant 7,875,932 - Jin , et al. January 25, 2
2011-01-25
Low temperature conformal oxide formation and applications
Grant 7,851,385 - Spuller , et al. December 14, 2
2010-12-14
Method of forming non-volatile memory having charge trap layer with compositional gradient
Grant 7,816,205 - Balseanu , et al. October 19, 2
2010-10-19
Non-volatile Memory Having Charge Trap Layer With Compositional Gradient
App 20100096688 - Balseanu; Mihaela ;   et al.
2010-04-22
Non-volatile Memory Having Silicon Nitride Charge Trap Layer
App 20100096687 - BALSEANU; Mihaela ;   et al.
2010-04-22
Flash Memory With Treated Charge Trap Layer
App 20100099247 - Balseanu; Mihaela ;   et al.
2010-04-22
Oxide Etch With Nh4-nf3 Chemistry
App 20100093151 - Arghavani; Reza ;   et al.
2010-04-15
Memory cell having stressed layers
Grant 7,678,662 - Arghavani , et al. March 16, 2
2010-03-16
Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
Grant 7,674,727 - Yuan , et al. March 9, 2
2010-03-09
Semiconductor on insulator apparatus
Grant 7,671,414 - Jin , et al. March 2, 2
2010-03-02
Semiconductor on Insulator Apparatus
App 20100038717 - Jin; Been-Yih ;   et al.
2010-02-18
Apparatus And Method For Reaction Of Materials Using Electromagnetic Resonators
App 20090295509 - Master; Neel S. ;   et al.
2009-12-03
Substrate having silicon germanium material and stressed silicon nitride layer
Grant 7,563,680 - Arghavani July 21, 2
2009-07-21
Method of inducing stresses in the channel region of a transistor
Grant 7,528,051 - Arghavani , et al. May 5, 2
2009-05-05
Low Temperature Conformal Oxide Formation And Applications
App 20090087977 - SPULLER; MATTHEW ;   et al.
2009-04-02
Semiconductor On Insulator Apparatus
App 20080303116 - Jin; Been-Yih ;   et al.
2008-12-11
Semiconductor on insulator apparatus and method
Grant 7,427,538 - Jin , et al. September 23, 2
2008-09-23
Uv Curing Of Pecvd-deposited Sacrificial Polymer Films For Air-gap Ild
App 20080182403 - NOORI; ATIF ;   et al.
2008-07-31
Substrate Having Silicon Germanium Material and Stressed Silicon Nitride Layer
App 20080096356 - Arghavani; Reza
2008-04-24
Metal layer inducing strain in silicon
App 20080061285 - Arghavani; Reza ;   et al.
2008-03-13
Substrate having silicon germanium material and stressed silicon nitride layer
Grant 7,323,391 - Arghavani January 29, 2
2008-01-29
Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
App 20080014730 - Arghavani; Reza ;   et al.
2008-01-17
Low-k spacer integration into CMOS transistors
App 20070202640 - Al-Bayati; Amir ;   et al.
2007-08-30
Method for producing gate stack sidewall spacers
Grant 7,253,123 - Arghavani , et al. August 7, 2
2007-08-07
Memory Cell Having Stressed Layers
App 20070132054 - Arghavani; Reza ;   et al.
2007-06-14
Oxide Etch With Nh4-nf3 Chemistry
App 20070123051 - Arghavani; Reza ;   et al.
2007-05-31
Nitrous Oxide Anneal Of Teos/ozone Cvd For Improved Gapfill
App 20070059896 - Yuan; Zheng ;   et al.
2007-03-15
Method for making a semiconductor device having a high-k gate dielectric
Grant 7,166,505 - Chau , et al. January 23, 2
2007-01-23
Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
Grant 7,141,483 - Yuan , et al. November 28, 2
2006-11-28
Low-thermal-budget gapfill process
Grant 7,087,497 - Yuan , et al. August 8, 2
2006-08-08
Mixing energized and non-energized gases for silicon nitride deposition
App 20060162661 - Jung; Kee Bum ;   et al.
2006-07-27
Substrate having silicon germanium material and stressed silicon nitride layer
App 20060160314 - Arghavani; Reza
2006-07-20
Method for producing gate stack sidewall spacers
App 20060154493 - Arghavani; Reza ;   et al.
2006-07-13
Method for forming a low thermal budget spacer
Grant 7,049,200 - Arghavani , et al. May 23, 2
2006-05-23
Pre-etch implantation damage for the removal of thin film layers
Grant 7,045,073 - Hareland , et al. May 16, 2
2006-05-16
Post treatment of low k dielectric films
Grant 7,018,941 - Cui , et al. March 28, 2
2006-03-28
Method For Forming A Low Thermal Budget Spacer
App 20050266622 - Arghavani, Reza ;   et al.
2005-12-01
Method of inducing stresses in the channel region of a transistor
App 20050255667 - Arghavani, Reza ;   et al.
2005-11-17
Post Treatment Of Low K Dielectric Films
App 20050239293 - Cui, Zhenjiang ;   et al.
2005-10-27
Low-thermal-budget gapfill process
App 20050196929 - Yuan, Zheng ;   et al.
2005-09-08
Stress-tuned, single-layer silicon nitride film
App 20050170104 - Jung, KeeBum ;   et al.
2005-08-04
Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
App 20050124125 - Jin, Been-Yih ;   et al.
2005-06-09
Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
Grant 6,900,481 - Jin , et al. May 31, 2
2005-05-31
Method for making a semiconductor device having a high-k gate dielectric
App 20050032318 - Chau, Robert ;   et al.
2005-02-10
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
Grant 6,809,017 - Arghavani , et al. October 26, 2
2004-10-26
Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
App 20040161903 - Yuan, Zheng ;   et al.
2004-08-19
Pre-etch implantation damage for the removal of thin film layers
App 20040118805 - Hareland, Scott A. ;   et al.
2004-06-24
Method for making a semiconductor device having a high-k gate dielectric
App 20040106287 - Chau, Robert ;   et al.
2004-06-03
Method for making a semiconductor device having a high-k gate dielectric
Grant 6,713,358 - Chau , et al. March 30, 2
2004-03-30
Field effect transistor
Grant 6,707,120 - Aminzadeh , et al. March 16, 2
2004-03-16
Thin dielectric layers and non-thermal formation thereof
App 20040036123 - Keating, Steven J. ;   et al.
2004-02-26
Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
App 20040033678 - Arghavani, Reza ;   et al.
2004-02-19
Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
App 20040033677 - Arghavani, Reza ;   et al.
2004-02-19
Semiconductor on insulator apparatus and method
App 20040031990 - Jin, Been-Yih ;   et al.
2004-02-19
Thin dielectric layers and non-thermal formation thereof
Grant 6,667,232 - Keating , et al. December 23, 2
2003-12-23
Plasma nitridation for reduced leakage gate dielectric layers
Grant 6,667,251 - McFadden , et al. December 23, 2
2003-12-23
Plasma Nitridation For Reduced Leakage Gate Dielectric Layers
App 20030216059 - McFadden, Robert ;   et al.
2003-11-20
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
Grant 6,620,713 - Arghavani , et al. September 16, 2
2003-09-16
Method for making a semiconductor device having a high-k gate dielectric
Grant 6,617,209 - Chau , et al. September 9, 2
2003-09-09
Method for making a semiconductor device having a high-k gate dielectric
Grant 6,617,210 - Chau , et al. September 9, 2
2003-09-09
Method For Making A Semiconductor Device Having A High-k Gate Dielectric
App 20030162377 - Chau, Robert ;   et al.
2003-08-28
Plasma nitridation for reduced leakage gate dielectric layers
Grant 6,610,615 - McFadden , et al. August 26, 2
2003-08-26
Integrated circuit with multiple gate dielectric structures
Grant 6,597,046 - Chau , et al. July 22, 2
2003-07-22
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
App 20030124871 - Arghavani, Reza ;   et al.
2003-07-03
Method and apparatus for dry/catalytic-wet steam oxidation of silicon
App 20030075108 - Arghavani, Reza ;   et al.
2003-04-24
Method and apparatus for dry/catalytic-wet steam oxidation of silicon
Grant 6,514,879 - Arghavani , et al. February 4, 2
2003-02-04
Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
App 20020168826 - Jin, Been-Yih ;   et al.
2002-11-14
Method And Apparatus For Dry/catalytic-wet Steam Oxidation Of Silicon
App 20020052123 - ARGHAVANI, REZA ;   et al.
2002-05-02
Method Of Forming A Thin Gate Dielectric Layers
App 20020003258 - KEATING, STEVEN J. ;   et al.
2002-01-10
N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress
Grant 6,261,925 - Arghavani , et al. July 17, 2
2001-07-17
Advanced trench sidewall oxide for shallow trench technology
Grant 6,153,480 - Arghavani , et al. November 28, 2
2000-11-28
Method of forming gate oxide having dual thickness by oxidation process
Grant 6,124,171 - Arghavani , et al. September 26, 2
2000-09-26
Integrated circuit with multiple gate dielectric structures
Grant 6,087,236 - Chau , et al. July 11, 2
2000-07-11
Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
Grant 5,827,769 - Aminzadeh , et al. October 27, 1
1998-10-27
N.sub.2 O nitrided-oxide trench sidewalls and method of making isolation structure
Grant 5,780,346 - Arghavani , et al. July 14, 1
1998-07-14

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