U.S. patent application number 10/301323 was filed with the patent office on 2003-04-24 for method and apparatus for dry/catalytic-wet steam oxidation of silicon.
This patent application is currently assigned to Intel Corporation. Invention is credited to Arghavani, Reza, Chau, Robert, Dalesky, Ron.
Application Number | 20030075108 10/301323 |
Document ID | / |
Family ID | 23851000 |
Filed Date | 2003-04-24 |
United States Patent
Application |
20030075108 |
Kind Code |
A1 |
Arghavani, Reza ; et
al. |
April 24, 2003 |
Method and apparatus for dry/catalytic-wet steam oxidation of
silicon
Abstract
A configuration of various chemical compound generators coupled
to a furnace provides the environment for formation of extremely
thin oxides of silicon on a wafer. Dichloroethylene is reacted with
oxygen in a first heated reaction chamber and reaction products
therefrom are diluted with a gas such as nitrogen and then
introduced into a vertically oriented furnace maintained at an
elevated temperature and having rotating wafers therein. Hydrogen
and oxygen are catalytically reacted to form steam in a second
heated reaction chamber, the steam is diluted with a gas such as
nitrogen and introduced into the vertical diffusion furnace. In a
further aspect of the present invention, MOSFETs having gate
dielectric layers of extremely thin oxides of silicon are
formed.
Inventors: |
Arghavani, Reza; (Aloha,
OR) ; Chau, Robert; (Beaverton, OR) ; Dalesky,
Ron; (Cornelius, OR) |
Correspondence
Address: |
Michael A. Bernadicou
BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP
Seventh Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025-1026
US
|
Assignee: |
Intel Corporation
|
Family ID: |
23851000 |
Appl. No.: |
10/301323 |
Filed: |
November 20, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10301323 |
Nov 20, 2002 |
|
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|
09466235 |
Dec 17, 1999 |
|
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|
6514879 |
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Current U.S.
Class: |
118/724 ;
257/E21.285 |
Current CPC
Class: |
H01L 21/31662 20130101;
H01L 21/28211 20130101; H01L 29/518 20130101; H01L 21/28185
20130101; H01L 21/28202 20130101; H01L 21/67017 20130101; H01L
21/02255 20130101; H01L 21/02238 20130101 |
Class at
Publication: |
118/724 |
International
Class: |
C23C 016/00 |
Claims
What is claimed is:
1. An apparatus, comprising: a furnace having an opening at one end
to receive a wafer container, and having a showerhead gas receiver
at a second end; a first reaction chamber adapted to receive
1,2-dichloroethylene and oxygen, and having a first output port; a
second reaction chamber adapted to receive O.sub.2, H.sub.2, and
N.sub.2, the second reaction chamber having a catalyst therein, and
a second output port; and a source of diluting gas; wherein the
source of diluting gas and the first output are coupled to the
showerhead through a first pathway, and the second output port is
coupled to the showerhead through a second pathway.
2. The apparatus of claim 1, further comprising a bubbler
containing liquid 1,2-dichloroethylene coupled to the first
reaction chamber.
3. The apparatus of claim 1, further comprising a push mechanism,
coupled to the furnace, adapted to provide rotational velocity to
the wafer container.
4. The apparatus of claim 1, wherein the second pathway comprises
stainless steel tubing fitted with a thermal jacket for maintaining
a desired temperature.
5. The apparatus of claim 1, wherein the catalyst comprises a
material that promotes the formation of steam from O.sub.2 and
H.sub.2 without flaming.
6. The apparatus of claim 1, wherein the diluting gas comprises
N.sub.2.
7. The apparatus of claim 1, further comprising an H.sub.2 detector
coupled to the second output port.
8. A method of forming a dielectric layer on a surface of a
substrate, comprising: maintaining at least one substrate in a
furnace at a temperature of approximately 625.degree. C.; rotating
the at least one substrate; providing diluted HCl, CO.sub.2, and
O.sub.2 to a first end of the furnace; and providing diluted steam
the first end of the furnace.
9. The method of claim 8, wherein diluted HCl, CO.sub.2, and
O.sub.2 is diluted with N.sub.2.
10. The method of claim 8, wherein diluted steam is diluted with
N.sub.2.
11. The method of claim 8, further comprising reacting
1,2-dichloroethylene and oxygen to produce at least HCl and
CO.sub.2.
12. The method of claim 8, further comprising catalytically
reacting O.sub.2 and H.sub.2 in the presence of N.sub.2 at a
temperature of approximately 500.degree. C.
13. The method of claim 8, wherein the at least one substrate
comprises a silicon wafer.
14. The method of claim 8, wherein rotating the at least one
substrate comprises rotating at approximately 3 rpm.
15. The method of claim 8, wherein the at least one substrate
comprises at least 100 silicon wafers each having a diameter of
substantially 200 mm; and wherein the wafers are rotated at
approximately 3 rpm.
16. The method of claim 8, wherein diluted HCl, CO.sub.2, and
O.sub.2 are provided to the furnace at atmospheric pressure.
17. The method of claim 8, wherein providing diluted HCl, CO.sub.2,
and O.sub.2 is substantially stopped prior to providing
diluted.
18. The method of claim 8, wherein the dielectric layer is an oxide
of silicon having a 3.sigma. uniformity of 0.5 angstroms.
19. The method of claim 8, wherein the furnace is vertically
oriented and the first end is the top end.
20. A method of making a field effect transistor, comprising:
providing oxygen and nitrogen to a furnace; pushing one or more
wafers into the furnace; rotating the one or more wafers at
approximately 3 rpm providing HCl, CO.sub.2, N.sub.2, and O.sub.2
to the furnace and maintaining a temperature of approximately
625.degree. C.; providing N.sub.2 and steam, at approximately
180.degree. C., to the furnace; removing the one or more wafers
from the furnace; patterning at least one gate electrode on the one
or more wafers; and forming source/drain terminals substantially
adjacent the gate electrode.
21. The method of claim 20, further comprising nitridizing an oxide
layer on a surface of the wafer prior to patterning at least one
gate electrode on the wafer.
22. The method of claim 20, wherein providing HCl, CO.sub.2,
N.sub.2, and O.sub.2 continues for approximately 2 minutes.
23. The method of claim 20, wherein providing steam and N.sub.2,
continues for approximately 6 minutes.
24. The method of claim 20, further comprising annealing the one or
more wafers.
25. The method of claim 24, wherein annealing comprises maintaining
the one or more wafers at approximately 625.degree. C., in a
nitrogen ambient for approximately 30 minutes.
26. An oxide furnace system, comprising a furnace having a gas
inlet at a first end, and a wafer receiving port at a second end; a
dry chlorinated oxygen generator coupled to the gas inlet; a
catalytic steam generator coupled to the gas inlet; a push
mechanism, aligned with the wafer receiving port, adapted to
provide linear and rotational velocity to a plurality of wafers;
and a temperature-controlled pathway disposed between the catalytic
steam generator and the gas inlet; wherein the dry chlorinated
oxygen generator and the catalytic steam generator are spaced apart
from the furnace and coupled to the gas inlet of the furnace by
plumbing.
27. The oxide furnace of claim 26, further comprising a furnace
controller coupled to the furnace.
28. The oxide furnace of the claim 26, further comprising an
H.sub.2 detector coupled to the output of the catalytic steam
generator.
29. The oxide furnace of claim 26, further comprising an alarm
coupled to the H.sub.2 detector.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to semiconductor
structures and manufacturing. More particularly, the invention
relates to extremely thin dielectric layers and the methods and
apparatus for the formation thereof.
[0003] 2. Background
[0004] Advances in semiconductor manufacturing technology have led
to the integration of millions of circuit elements, such as
transistors, on a single integrated circuit (IC). In order to
integrate increasing numbers of circuit elements onto an integrated
circuit it has been necessary to reduce the line widths of the
various parts that make up an integrated circuit. Not only have
interconnect line widths become smaller, but so have the dimensions
of metal-oxide-semiconductor field effect transistors
(MOSFETs).
[0005] MOSFETs are also sometimes referred to as insulated gate
field effect transistors (IGFETs). Most commonly, these devices are
referred to simply as FETs, and are so referred to in this
disclosure.
[0006] Transistor scaling typically involves more than just the
linear reduction of the FET width and length. For example, both
source/drain (S/D) junction depth and gate dielectric thickness are
also typically reduced in order to produce a FET with the desired
electrical characteristics.
[0007] Over the years, a substantial amount of research and
development in the field semiconductor manufacturing has been
dedicated to providing reduced thickness dielectric layers, as
mentioned above. However, to be suitable for use as a MOSFET gate
dielectric layer, these reduced thickness dielectric layers are
typically required to provide certain electrical characteristics.
For example, the dielectric layer should have a low density of
interface states, a low density of defects, and a dielectric
breakdown voltage high enough for use with the desired voltages
that the MOSFET will encounter during operation. Furthermore, such
a reduced thickness dielectric layer should be manufacturable with
great uniformity and repeatability.
[0008] What is needed is an extremely thin dielectric layer
suitable for use as the gate dielectric layer in a MOSFET, and what
is further needed are apparatus and methods for repeatably making
such ultra-thin dielectric layers.
SUMMARY OF THE INVENTION
[0009] Briefly, a configuration of various chemical compound
generators coupled to a furnace provides the environment suitable
for repeatably forming extremely thin oxides of silicon on a wafer
with a high degree of uniformity.
[0010] In a further aspect of the present invention, MOSFETs having
gate dielectric layers of extremely thin oxides of silicon are
formed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a schematic representation of a furnace and
associated chemical compound generators coupled thereto in
accordance with the present invention.
[0012] FIG. 2 is a flow diagram of a process in accordance with the
present invention.
[0013] FIG. 3 is a flow diagram of a process in accordance with the
present invention.
DETAILED DESCRIPTION
[0014] Terminology
[0015] The terms, chip, integrated circuit, monolithic device,
semiconductor device or component, microelectronic device or
component, and similar terms and expressions are often used
interchangeably in this field. The present invention is applicable
to all the above as they are generally understood in the field.
[0016] Historically, the material most commonly used in the
semiconductor industry to form the gate insulator layer of a FET is
silicon dioxide. Thus, the gate insulator layer is frequently
referred to simply as the gate oxide. The expression gate
dielectric is also used to describe the gate insulator layer.
[0017] The term "gate" is context sensitive and can be used in two
ways when describing integrated circuits. Gate refers to a circuit
for realizing an arbitrary logical function when used in the
context of a logic gate. However, as used herein, gate refers to
the insulated gate terminal of a three terminal FET when used in
the context of transistor circuit configurations or formation of
transistor structures. The expression "gate terminal" is generally
interchangeable with the expression "gate electrode". A FET can be
viewed as a four terminal device when the semiconductor body is
considered, for the purpose of describing illustrative embodiments
of the present invention, the FET will be described using the
traditional gate-drain-source, three terminal model.
[0018] Polycrystalline silicon is a nonporous form of silicon often
formed by chemical vapor deposition from a silicon source gas, or
other methods, and has a structure that contains crystallites or
domains with large-angle grain boundaries, twin boundaries, or
both. Polycrystalline silicon is often referred to in this field as
polysilicon, or sometimes more simply as poly.
[0019] Source/drain terminals refer to the terminals of a FET,
between which conduction occurs under the influence of an electric
field, subsequent to the inversion of the semiconductor surface
under the influence of a vertical electric field resulting from a
voltage applied to the gate terminal. Generally, the source and
drain terminals are fabricated such that they are geometrically
symmetrical. With geometrically symmetrical source and drain
terminals it is common to simply refer to these terminals as
source/drain terminals, and this nomenclature is used herein.
Designers often designate a particular source/drain terminal to be
a "source" or a "drain" on the basis of the voltage to be applied
to that terminal when the FET is operated in a circuit.
[0020] Overview
[0021] An arrangement of equipment, and methods of operation are
disclosed for the formation of extremely thin oxides of silicon on
a wafer. These oxides are formed with a high degree of uniformity
both within wafer and wafer-to-wafer, and are electrically suitable
for use as a gate dielectric layer.
[0022] In accordance with the present invention, a configuration of
equipment for forming extremely thin oxides of silicon with
excellent uniformity, both within wafer, and wafer-to-wafer,
includes a first heated reaction chamber coupled to an O.sub.2
source and a 1,2-dichloroethylene (DCE) source, such as, for
example, a bubbler. The first reaction chamber has an output port
coupled through a first pathway to a showerhead arrangement of a
furnace. The first pathway is also coupled to a source of a
diluting gas, such as, for example, nitrogen. A second heated
reaction chamber having a metal catalyst therein is coupled to an
O.sub.2 source, an H.sub.2 source, and an N.sub.2 source. The
second reaction chamber has an output port coupled to the
showerhead arrangement of a furnace. The furnace is typically
vertically oriented. In this orientation, the showerhead is
typically at the top end of the furnace. The bottom end of the
furnace typically has an opening through which it receives a
container of wafers. Such a furnace is sometimes referred to in
this industry as a vertical diffusion furnace (VDF) regardless of
whether it is used for a diffusion operation or some other high
temperature operation.
[0023] A method of forming a dielectric having a thickness of
approximately 10 angstroms (1.0 nm) or less on a silicon substrate
includes placing wafers into a furnace and performing a dry
chlorinated oxidation operation, and a wet oxidation with steam.
The wafers are rotated at approximately 3 rpm during the dry and
wet oxidations and the furnace is maintained at approximately
625.degree. C. In accordance with the present invention, both the
dry and wet oxidation operations require the preparation of gases
external to the furnace. In one reaction chamber, a reaction of
1,2-dichloroethylene and oxygen at elevated temperatures produces,
primarily, HCl and CO.sub.2, which together with other reaction
products, O.sub.2, and N.sub.2, are passed to the showerhead of the
furnace to begin the dry oxidation operation. In another reaction
chamber, H.sub.2 and O.sub.2 are catalytically combined to form
steam. The steam, together with nitrogen, is passed to the
showerhead of the furnace to begin the wet oxidation operation. In
this way, a dry/catalytic steam oxidation is accomplished.
[0024] Oxide Furnace Example
[0025] A first illustrative embodiment of the present invention is
described below in connection with FIG. 1. As shown in FIG. 1, a
vertically oriented furnace 102 has a showerhead arrangement 104,
or more simply showerhead 104, at a top portion thereof so as to
enable the introduction of various gases into furnace 102. A push
mechanism 106 is used to push a wafer container 108 into furnace
102, and to move wafer container 108 back out again. Push mechanism
106 is adapted so that it may provide a rotational velocity to
wafer container 108. Showerhead 104 is coupled to input plumbing
110. Input plumbing 110, in turn, is coupled to stainless steel
plumbing 126, and to plumbing 114. Plumbing 114 is coupled to a
diluting gas source 117 through plumbing 116. Plumbing 114 is
further coupled to reaction chamber 112. Reaction chamber 112 is
coupled to a 1,2-dichloroethylene (DCE) source 118, and an O.sub.2
source 122. DCE source 118, in the illustrative embodiment of FIG.
1, is a bubbler which is further coupled to receive an N.sub.2
carrier gas via plumbing 120. Stainless steel plumbing 126, which
is adapted to maintain a particular temperature range, is coupled
to reaction chamber 124. Reaction chamber 124 is coupled to H.sub.2
source 128, O.sub.2 source 130, and N.sub.2 source 132. Those
skilled in the art and having the benefit of this disclosure will
appreciate that plumbing as used herein may be implemented as
tubing, and that such tubing may be made from any of various
materials suitable for the gases and temperatures used.
[0026] Reaction chamber 112 is adapted to receive DCE and O.sub.2
and heat these gases. Reaction products such as HCl and CO.sub.2,
as well as unreacted O.sub.2 exit reaction chamber 112 through
plumbing 114. This stream of gases is then combined with at least
one other gas in order to dilute the gases exiting from reaction
chamber 112. In one embodiment of the present invention, N.sub.2 is
used to achieve this dilution. In this context, N.sub.2 is referred
to herein as a diluting gas.
[0027] Reaction chamber 124 is adapted to receive H.sub.2 and
O.sub.2, and catalytically combine the H.sub.2 and O.sub.2 to
produce steam. Reaction chamber 124 is further adapted to receive a
diluting gas, in this case N.sub.2. Additionally, reaction chamber
124 is adapted to couple the steam to plumbing 126. An H.sub.2
detector may be coupled to the output of reaction chamber 124. The
H.sub.2 detector may be coupled to an alarm such that when a
predetermined amount of H.sub.2 is detected an alarm is activated
which notifies one or more operators, or may alternatively notify
other equipment, that an unacceptable level of H.sub.2 is contained
in the gases which exit reaction chamber 124.
[0028] Furnace 102 is adapted to heat the wafers and gases
introduced thereinto, and to maintain a particular temperature or
temperature gradient. As indicated above, wafers 109 are introduced
into furnace 102 by push mechanism 106 which delivers wafer
container 108 into furnace 102. A furnace controller 150 is coupled
to furnace 102 and push mechanism 106 and provides the control
signals for setting and maintaining various temperatures for
programmed times, as well as for providing control signals to push
mechanism 106 which determine push rates, pull rates, and rotation
speeds. Furnace controllers are well-known in this field and not
described in further detail hereafter.
[0029] Oxide Formation Example
[0030] A first exemplary process for the formation of an oxide of
silicon suitable for use as a MOSFET gate dielectric is described
in conjunction with FIG. 2.
[0031] In this illustrative embodiment of the present invention,
prior to beginning the dry and wet oxidation operations, the wafers
are loaded in a wafer container, sometimes referred to as a boat,
the boat is placed into a load lock chamber of the furnace, the
load lock door is closed, the chamber is evacuated and purged with
N.sub.2. The boat is then pushed into the furnace tube with a 0.1
slpm O.sub.2 flow and 9.9 slpm N.sub.2 flow. The furnace
temperature is then ramped up from approximately 500.degree. C. to
approximately 625.degree. C. with a gas mixture flow of 0.1 slpm
O.sub.2, and 9.9 slpm N.sub.2. Pushing the wafers into the furnace
under these conditions forms a first amount of oxide on the surface
of the wafers. This oxide is sometimes referred to as a push oxide
because it forms while the wafers are being pushed into the
furnace. The container of wafers is pushed into a vertically
oriented furnace. Such a wafer container typically contains
approximately 125 silicon wafers, with each wafer typically having
a diameter of 200 mm (sometimes referred to in this field as eight
inch wafers). Those skilled in the art will recognize that other
wafer sizes, or a different number of wafers may be used with
embodiments of the present invention. The wafer container is pushed
into the furnace at a rate of approximately 500 mm per minute with
the furnace at approximately 500.degree. C., and a gas flow into
the furnace of 0.1 slpm O.sub.2, and 9.9 slpm N.sub.2 being
provided. The furnace temperature is then ramped up from
500.degree. C. to 625.degree. C., and a gas mixture flow of 0.1
slpm O.sub.2, and 9.9 slpm N.sub.2 is provided.
[0032] As shown in FIG. 2, in accordance with the present
invention, the 200 mm wafers are rotated, and in this exemplary
embodiment given a rotational velocity of approximately 3 rpm, and
their temperature is maintained at approximately 625.degree. C.
(block 202). It is preferable to maintain temperature control of
the furnace such that the gradient is less than or equal to
2.degree. C. from one end of the furnace to the other. A first gas
mixture including HCl, CO.sub.2, and O.sub.2, diluted with nitrogen
is provided to the furnace from a showerhead arrangement at the top
of the vertically-oriented furnace (block 204). This operational
phase is referred to as a dry oxidation. The dry oxidation takes
place for approximately 2 minutes. The wafers are rotated and
maintained at this temperature, i.e., 625.degree. C., with the
first gas mixture provided at atmospheric pressure for a period of
approximately 2 minutes, as mentioned above. The first gas mixture
is obtained from the reaction of 1,2-dichloroethylene and oxygen at
approximately 800.degree. C. The 1,2-dichloroethylene is typically
provided to a reaction chamber, in which it is combined with
oxygen, from a bubbler using nitrogen as a carrier gas. HCl, and
CO.sub.2, are produced during this reaction. Nitrogen is fed
through the bubbler at approximately 0.29 slpm, and O.sub.2 is fed
to the reaction chamber at approximately 2.71 slpm. The reaction
products are combined with molecular nitrogen to dilute their
concentration and piped to the showerhead of the furnace. The
diluting nitrogen is supplied at a flow rate of approximately 20
slpm.
[0033] Still referring to FIG. 2, a second gas mixture is provided
to the furnace (block 206). This second gas mixture is formed by
the catalytic reaction of hydrogen and oxygen in the presence of
nitrogen at approximately 500.degree. C. Hydrogen is supplied to
the catalytic reaction chamber at the rate of approximately 0.5
slpm, oxygen is supplied at the rate of approximately 0.98 slpm,
and the diluting nitrogen is supplied at approximately 20 slpm. The
second gas mixture includes steam, which is created by the reaction
of hydrogen and oxygen, as well as nitrogen, and any unreacted
precursor gases. This operational phase is referred to as a wet
oxidation. The wet oxidation takes place for approximately 6
minutes. The second gas mixture is transferred to the furnace via
plumbing, such as for example stainless steel tubing. In one
embodiment of the present invention the second gas mixture is
maintained at 180.degree. C. as it passes through the stainless
steel tubing on its way to the showerhead of the furnace. No
significant amount of H.sub.2 exits the catalytic reaction
chamber.
[0034] Although the furnace is maintained at approximately
625.degree. C. in the illustrative embodiment of the present
invention, it is possible to maintain a temperature gradient
through the furnace such that, for example, one end of the furnace
is cooler and the other end is hotter. As is well-known in this
field, modern furnace controllers provide users with the ability to
program such temperature gradients, specifying times and
temperatures.
[0035] Subsequent to the wet oxidation, the wafers are annealed in
N.sub.2 for approximately 30 minutes. Then the wafers are pulled
out of the furnace. In this illustrative embodiment, the time taken
for loading the wafers, pushing them into the furnace, completing
the dry and wet oxidation operations, annealing, pulling the wafers
out of the furnace and unloading is approximately 3.5 hours.
[0036] A second exemplary process for the formation of an oxide of
silicon suitable for use as a MOSFET gate dielectric is described
in conjunction with FIG. 3, and includes forming a gate electrode
and source/drain terminals needed to complete a MOSFET. It will be
appreciated that apparatus and methods in accordance with the
present invention can produce gate dielectric layers suitable for
both PFETs and NFETs.
[0037] Referring to FIG. 3, oxygen and nitrogen are provided to a
vertically oriented furnace and wafers are pushed into the furnace
at a rate of approximately 500 mm per minute (block 302) as the
temperature is maintained at approximately 500.degree. C. The
furnace temperature is then ramped from approximately 500.degree.
C. to approximately 625.degree. C. (304). The wafers are typically
in a container and the container is pushed into the furnace by a
mechanism which is also adapted to rotate the wafers by rotating
the container. A container of approximately 125 eight-inch wafers
is rotated at approximately 3 rpm. After the wafers are in the
furnace, a dry oxidation operation is performed (block 306) in
which a first gas mixture including HCl, CO.sub.2, N.sub.2, and
O.sub.2 is provided to the furnace, and a temperature of
approximately 625.degree. C. is maintained. The HCl and CO.sub.2
are produced external to the furnace in a reaction chamber in which
dichloroethylene and oxygen react at approximately 800.degree. C.
After approximately 2 minutes, the flow of the first gas mixture is
stopped and a second gas mixture is provided to the furnace (block
308). The second gas mixture includes catalytically produced steam
along with molecular nitrogen. The steam is maintained at
approximately 180.degree. C. as it is piped from the external
catalytic reaction chamber to the furnace. After approximately 6
minutes, the flow of the second gas mixture is stopped and the
wafers are subjected to a 30 minute anneal in a nitrogen ambient
(block 310). Subsequently, the wafers are removed from the furnace
(block 312).
[0038] Still referring to FIG. 3, after the oxide dielectric layer
has been formed, conventional processing operations may be
performed in order to form a gate electrode over the dielectric
layer, and to form source/drain terminals substantially aligned
with the gate electrode (block 314). For example, a layer of
polysilicon may be formed of the oxide, patterned with a gate mask,
to form one or more gate electrodes. Source/drain terminal
formation can be accomplished by any of a number of well-known
methods. For example, a first ion implantation, aligned to the gate
electrode to form a source/drain extension can be performed,
followed by formation of sidewall spacers along laterally opposed
sides of a gate electrode, and followed in turn by a second ion
implantation to form the deep portions of the source/drain
terminals. Those skilled in the art will recognize that both NFETs
and PFETs can be formed in this way. The type of dopant ions
implanted depends of the type of transistor being formed. For
example, PFETs have p-type source/drains which can be formed by
dopants such as boron or indium. Similarly, NFETs have n-type
source/drains which can be formed by dopants such as phosphorus,
arsenic or antimony.
[0039] Various other layers of insulators and conducting material
are formed above the gate level, as is well understood in the field
of semiconductor manufacturing and integrated circuit design.
CONCLUSION
[0040] Embodiments of the present invention provide extremely thin
dielectric layers. Dielectric layers less than or equal to
approximately 11 angstroms, which are suitable for use as the gate
insulating layer for FETs, are created in a dry/catalytic steam
oxidation process which provides a uniformity 0.5 angstrom at
3.sigma..
[0041] It will be recognized by those skilled in the art and having
the benefit of this disclosure that the present invention is
applicable to the formation of both n-channel FETs (NFETs) and
p-channel FETs (PFETs).
[0042] The present invention may be implemented with various
changes and substitutions to the illustrated embodiments. For
example, the present invention may be practiced with not only with
silicon wafers as substrates, but also with other substrates,
including but not limited to such substrates as silicon on
insulator (SOI) Various other carrier and diluting gases may be
substituted for nitrogen and provide substantially similarly
results, however, nitrogen is typically preferred because it is
much less expensive than other substantially inert gases.
Furthermore, those skilled in the art and having the benefit of the
present disclosure will recognize that times, temperatures, and
rotational speeds may need to be varied to accommodate different
size wafers (e.g., 300 mm diameter wafers) or different numbers of
wafers in the furnace. Variation of these parameters in view of the
present disclosure would be an undertaking which does not require
undue experimentation by those skilled in the art.
[0043] Although specific embodiments, including specific equipment,
parameters, methods and materials have been described, it will be
readily understood by those skilled in the art and having the
benefit of this disclosure, that various other changes in the
details, materials, and arrangements of the materials and steps
which have been described and illustrated in order to explain the
nature of this invention may be made without departing from the
principles and scope of the invention as expressed in the subjoined
claims.
* * * * *