U.S. patent application number 10/637360 was filed with the patent office on 2005-02-10 for deep trench etching using hdp chamber.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Chang, Cheng-Cheng, Chang, Fa-Yuan, Chen, Shih-Feng, Fang, Buh-Kuan.
Application Number | 20050029221 10/637360 |
Document ID | / |
Family ID | 34116604 |
Filed Date | 2005-02-10 |
United States Patent
Application |
20050029221 |
Kind Code |
A1 |
Chang, Fa-Yuan ; et
al. |
February 10, 2005 |
Deep trench etching using HDP chamber
Abstract
A process for etching deep trenches in a substrate for purposes
such as the fabrication of microelectromechanical systems (MEMS),
for example, on the substrate. The two-step process includes first
etching a tapered trench having a tapered profile and enhanced
sidewall passivation in a substrate along a protective mask which
defines the desired trench profile on the substrate surface. Next,
the tapered trench is trimmed by high-density plasma in an
isotropic etching step to provide a straight-profile deep trench
with minimum sidewall passivation.
Inventors: |
Chang, Fa-Yuan; (Taipei
City, TW) ; Fang, Buh-Kuan; (Taipei City, TW)
; Chen, Shih-Feng; (Sanchong, TW) ; Chang,
Cheng-Cheng; (Hsin-Chu, TW) |
Correspondence
Address: |
TUNG & ASSOCIATES
Suite 120
838 W. Long Lake Road
Bloomfield Hills
MI
48302
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
|
Family ID: |
34116604 |
Appl. No.: |
10/637360 |
Filed: |
August 9, 2003 |
Current U.S.
Class: |
216/2 |
Current CPC
Class: |
B81C 1/00619
20130101 |
Class at
Publication: |
216/002 |
International
Class: |
C23F 001/00 |
Claims
What is claimed is:
1. A process for forming a deep trench in a substrate, comprising
the steps of: providing an etch chamber; placing said substrate in
said etch chamber; etching a tapered trench in said substrate by
subjecting said substrate to a first etching step; and etching said
tapered trench to form said deep trench by subjecting said
substrate to a second etching step.
2. The process of claim 1 wherein said first etching step includes
providing a pressure of about 4.about.20 mT in said etch
chamber.
3. The process of claim 2 wherein said first etching step includes
applying a bias power of about 10.about.100 W and a source power of
about 100.about.800 W to said etch chamber.
4. The process of claim 3 wherein said first etching step includes
flowing HBr and CF.sub.4 into said etch chamber.
5. The process of claim 1 wherein said second etching step includes
providing a pressure of about 5.about.20 mT in said etch
chamber.
6. The process of claim 5 wherein said second etching step includes
applying a bias power of about 10.about.200 W and a source power of
about 500-1200 W to said etch chamber.
7. The process of claim 6 wherein said second etching step includes
flowing HBr, O.sub.2 and SF.sub.6 into said etch chamber.
8. A process for forming a deep trench in a substrate, comprising
the steps of: providing an etch chamber having a cathode and a
chamber wall; placing said substrate in said etch chamber;
maintaining said cathode at a temperature of about 10.about.45
degrees C. and said chamber wall at a temperature of about
50.about.100 degrees C.; etching a tapered trench in said substrate
by subjecting said substrate to a first etching step; and etching
said tapered trench to form said deep trench by subjecting said
substrate to a second etching step.
9. The process of claim 8 wherein said first etching step includes
providing a pressure of about 4.about.20 mT in said etch
chamber.
10. The process of claim 9 wherein said first etching step includes
applying a bias power of about 10.about.100 W and a source power of
about 100.about.800 W to said etch chamber.
11. The process of claim 10 wherein said first etching step
includes flowing HBr and CF.sub.4 into said etch chamber.
12. The process of claim 11 wherein said second etching step
includes providing a pressure of about 5.about.20 mT in said etch
chamber.
13. The process of claim 12 wherein said second etching step
includes applying a bias power of about 10.about.200 W and a source
power of about 500-1200 W to said etch chamber.
14. The process of claim 13 wherein said second etching step
includes flowing HBr, O.sub.2 and SF.sub.6 into said etch
chamber.
15. A process for forming a deep trench in a substrate, comprising
the steps of: providing a high density plasma etch chamber having a
cathode and a chamber wall; placing said substrate in said etch
chamber; etching a tapered trench in said substrate by subjecting
said substrate to a first etching step; and etching said tapered
trench to form said deep trench by subjecting said substrate to a
second etching step.
16. The process of claim 15 wherein said first etching step and
said second etching step includes maintaining said cathode at a
temperature of about 10.about.45 degrees C. and said chamber wall
at a temperature of about 50.about.100 degrees C.
17. The process of claim 15 wherein said first etching step
includes providing a pressure of about 4.about.20 mT in said etch
chamber, applying a bias power of about 10.about.100 W and a source
power of about 100.about.800 W to said etch chamber, and flowing
HBr and CF.sub.4 into said etch chamber.
18. The process of claim 17 wherein said first etching step and
said second etching step includes maintaining said cathode at a
temperature of about 10.about.45 degrees C. and said chamber wall
at a temperature of about 50.about.100 degrees C.
19. The process of claim 17 wherein said second etching step
includes providing a pressure of about 5.about.20 mT in said etch
chamber, applying a bias power of about 10.about.200 W and a source
power of about 500-1200 W to said etch chamber, and flowing HBr,
O.sub.2 and SF.sub.6 into said etch chamber.
20. The process of claim 19 wherein said first etching step and
said second etching step includes maintaining said cathode at a
temperature of about 10.about.45 degrees C. and said chamber wall
at a temperature of about 50.about.100 degrees C.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to etching of circuit patterns
on semiconductor wafer substrates in the fabrication of integrated
circuits on the substrates. More particularly, the present
invention relates to a process for etching deep trenches in
substrates using an HDP chamber in the fabrication of
microelectromechanical systems (MEMS), for example.
BACKGROUND OF THE INVENTION
[0002] Integrated circuits are formed on a semiconductor substrate,
which is typically composed of silicon. Such formation of
integrated circuits involves sequentially forming or depositing
multiple electrically conductive and insulative layers in or on the
substrate. Etching processes may then be used to form geometric
patterns in the layers or vias for electrical contact between the
layers. Some electronic devices, for example, particular types of
sensors, actuators, electronics, optics, etc., have cost and
performance advantages when manufactured from semiconductor
materials on a miniature scale using microelectromechanical systems
(MEMS) technology. Such miniature electronic devices can be formed
with micromechanical structures such as membranes, cantilevered
beams, microbridges, tethered proof masses, micro hotplates,
micromirrors, etc., which are integrated with transduction
mechanisms such as piezoresistors, p-n junctions, field effect
transistors (FETs), piezoelectric films, etc. In order for these
miniature electronic devices to perform accurately, the
micromechanical structures must be fabricated with precise
dimensional control.
[0003] One example of a well-known MEMS device is a microscopic
gimbaled mirror mounted on a substrate. A gimbaled mirror is a
device that may pivot on a hinge about an axis. By pivoting about
an axis, a gimbaled mirror can redirect light beams to varying
positions. Typically, MEMS gimbaled mirrors are arranged in an
array on a single silicon wafer substrate.
[0004] Fabrication of micro-mirror array chips used in an MEMS
device requires precise alignment between the MEMS structure and
other optical components such as optical fiber arrays or laser
arrays. During the fabrication of the device, it is often necessary
to bond one part of the MEMS device found on one wafer to another
part of the device that is formed on a different wafer.
Conventionally, these multiple layers of a MEMS device are aligned
using a "flip chip" optical alignment system to align two wafers,
or two parts, to each other. Fixtures are used to hold the wafers
together, after which the wafers are attached to each other.
[0005] Fabrication of MEMS structures frequently requires etching
of deep (20 .mu.m) trenches in the silicon substrate on which the
structures are fabricated. The wafer is then diced into separate
chips along the deep trenches. In plasma etching, a gas is first
introduced into a reaction chamber and then plasma is generated
from the gas. This is accomplished by dissociation of the gas into
ions, free radicals and electrons by using an RF (radio frequency)
generator, which includes one or more electrodes. The electrodes
are accelerated in an electric field generated by the electrodes,
and the energized electrons strike gas molecules to form additional
ions, free radicals and electrons, which strike additional gas
molecules, and the plasma eventually becomes self-sustaining. The
ions, free radicals and electrons in the plasma react chemically
with the layer material on the semiconductor wafer to form residual
products which leave the wafer surface and thus, etch the material
from the wafer. Plasma intensity depends on the type of etchant gas
or gases used, as well as the etchant gas pressure and temperature
and the radio frequency generated at the electrode. If any of these
factors changes during the process, the plasma intensity may
increase or decrease with respect to the plasma intensity level
required for optimum etching in a particular application. Decreased
plasma intensity results in decreased, and thus incomplete,
etching. Increased plasma intensity, on the other hand, can cause
overetching and plasma-induced damage of the wafers. Plasma-induced
damage includes trapped interface charges, material defects
migration into bulk materials, and contamination caused by the
deposition of etch products on material surfaces. Etch damage
induced by reactive plasma can alter the qualities of sensitive IC
components such as Schottky diodes, the rectifying capability of
which can be reduced considerably. Heavy-polymer deposition during
oxide contact hole etching may cause high-contact resistance.
[0006] A typical conventional process for etching a deep trench in
a substrate is shown in FIGS. 1A and 1B. A photoresist mask 12 in
the form of the desired trench pattern to be etched is first
deposited on the substrate 10. The photoresist mask 12 is typically
a polyimide having a thickness of about 24 .mu.m. As shown in FIG.
1A, a dielectric trench 14, typically having a depth of 58,000
angstroms and an etch profile of 90 degrees, is then etched in the
photoresist mask 12. As shown in FIG. 1B, a substrate trench 16 is
then etched in the substrate 10 beneath the photoresist mask 12,
typically to a depth of about 20 .mu.m, to define the deep trench
18. Like the dielectric trench 14, the substrate trench 16
typically has an etch profile of 90 degrees.
[0007] Etching of deep trenches in silicon wafers during the
fabrication of MEMS devices requires a high etch rate, high
selectivity and a vertical trench sidewall profile. Typically, the
etch process is carried out using either the well-known Bosch
process, which may be carried out in plasma etchers available from
Alcatel, Plasma-therm and Surface technology systems, or cryo
process which involves super-low temperatures of up to -110 C. Best
results are typically obtained using the Bosch process, although
the cryo process provides satisfactory results. However, the cryo
process is difficult to maintain and both the Bosch process and the
cryo process requires the use of specialized types of etchers which
are quite expensive. Accordingly, a new and improved process is
needed for etching of deep trenches in substrates using a general
purpose etch chamber, such as a DPS (Decoupled Plasma Source) HDP
(High Density Plasma) etch chamber available from Applied
Materials, Inc., of Santa Clara, Calif.
[0008] An object of the present invention is to provide a new and
improved process for etching deep trenches in substrates.
[0009] Another object of the present invention is to provide a deep
trench etching process which is inexpensive.
[0010] Still another object of the present invention is to provide
a deep trench etching process which is suitable for the fabrication
of microelectromechanical (MEM) devices.
[0011] Yet another object of the present invention is to provide a
process for etching deep trenches which is characterized by a high
etch rate.
[0012] A still further object of the present invention is to
provide a two-step process for the etching of deep trenches in a
substrate.
[0013] Another object of the present invention is to provide a deep
trench etching process which may be carried out in a general
purpose etching chamber.
[0014] Still another object of the present invention is to provide
a novel deep trench etching process which includes etching of a
tapered profile and sidewall trimming by isotropic etching of a
substrate.
SUMMARY OF THE INVENTION
[0015] In accordance with these and other objects and advantages,
the present invention is generally directed to a novel process for
etching deep trenches in a substrate for purposes such as the
fabrication of microelectromechanical systems (MEMS), for example,
on the substrate. The two-step process includes first etching a
tapered trench having a tapered profile and enhanced sidewall
passivation in a substrate along a protective mask which defines
the desired trench profile on the substrate surface. Next, the
tapered trench is trimmed by high-density plasma in an isotropic
etching step to provide a straight-profile deep trench with minimum
sidewall passivation. The deep trench etch process may be carried
out in a conventional general-purpose etching chamber without the
need for more specialized etch chambers traditionally used for the
purpose.
[0016] In a preferred embodiment, a general purpose DPS (Decoupled
Plasma Source) HDP (High Density Plasma) etch chamber available
from Applied Materials, Inc., (AMAT) of Santa Clara, Calif., is
used as the etch chamber for carrying out the process of the
present invention. However, it is understood that other types of
general purpose etch chambers may be used to carry out the process.
The AMAT etch chamber is capable of sustaining low chamber
pressures for long ion MFP, as well as high plasma density, which
facilitates a high etch rate.
[0017] In a preferred embodiment, HBr/CF.sub.4 is used as the
etchant in the first step to etch the tapered trench having the
tapered sidewalls. In the second step, a high-density
SF.sub.6/HBr/O.sub.2 plasma is used in combination with a chamber
pressure on the order of about 5.about.20 mT to facilitate a high
silicon etch rate. The cathode temperature, controlled by backside
helium, is selected to impart a uniform etch profile to the deep
trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The invention will now be described, by way of example, with
reference to the accompanying drawings, in which:
[0019] FIG. 1A is a cross-sectional view of a substrate
illustrating etching of a dielectric trench in a photoresist layer
on the substrate as a first step in a conventional process for
forming a deep trench in the substrate;
[0020] FIG. 1B is a cross-sectional view of a substrate
illustrating etching of an Si trench in the substrate as a second
step in a conventional process for forming a deep trench in the
substrate;
[0021] FIG. 2 is a schematic of a conventional etch chamber used in
implementation of the process of the present invention;
[0022] FIG. 3A is a cross-sectional view of a substrate,
illustrating etching of a tapered trench in the substrate according
to a first step in implementation of the process of the present
invention;
[0023] FIG. 3B is a cross-sectional view of a substrate,
illustrating trimming of the tapered trench using isotropic etching
according to a second step in implementation of the process of the
present invention; and
[0024] FIG. 4 is a process flow diagram summarizing sequential
steps in carrying out the process of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] The present invention includes a process for the etching of
deep trenches in a substrate such as during the fabrication of MEMS
(microelectromechanical systems) on the substrate. The process is a
two-step method which includes a first step of etching a tapered
trench having tapered sidewalls with sidewall passivation in the
substrate, followed by a second step of isotropic etching or
trimming of the tapered sidewalls to form the deep trench typically
having a depth of about 20 .mu.m and less sidewall passivation.
[0026] The process may be carried out using a general purpose etch
system such as a DPS (Decoupled Plasma Source) HDP (High Density
Plasma) etch chamber available from Applied Materials, Inc., (AMAT)
of Santa Clara, Calif. Such a chamber is capable of sustaining low
chamber pressures which facilitate long ion MFP, as well as high
plasma density which facilitates a high etch rate. However, it is
understood that the process of the present invention may be carried
out in other types of etch chambers known by those skilled in the
art.
[0027] Throughout the process, backside He pressure is maintained
at a temperature of typically about 4.about.12T to maintain a
cathode temperature of typically about 10.about.45 degrees C.
Typical chamber wall temperature is about 50.about.100 degrees C.
Typically, the first step of the process is carried out under
chamber pressures of about 20 mT, with a bias power of about
10.about.100 W and a source power of about 100.about.800 W. The HBr
is introduced into the chamber at a flow rate of about 0.about.20
sccm, and the CF.sub.4 is introduced into the chamber at a flow
rate of about 10.about.100 sccm, for about 2 minutes.
[0028] The second step of the process is carried out under chamber
pressures of typically about 5.about.20 mT, with a bias power of
typically about 10.about.200 W and a source power of typically
about 500.about.1200 W. The HBr, O.sub.2, and SF.sub.6 are
introduced into the chamber at a flow rate of typically about
10.about.50 sccm, about 50.about.100 sccm and about 30.about.100
sccm, respectively.
[0029] Variation of the process parameters contributes to various
trench sidewall profiles. For example, an increase in chamber
pressure during the first process step imparts a bowed or curved
configuration to the tapered sidewalls. Lower chamber wall
temperatures sustained during the second step tend to
correspondingly reduce isotropic etching of the sidewalls.
Variations in source power, on the other hand, have been found to
have little effect on trench profile and depth.
[0030] Referring to FIG. 2, a conventional etch system which is
suitable for forming a deep trench 38 (FIG. 3B) in a substrate 40
in implementation of the present invention as hereinafter
described, is generally indicated by reference numeral 20. In a
preferred embodiment, the etch system 20 is a DPS (Decoupled Plasma
Source) HDP (High Density Plasma) etch system available from AMAT
(Applied Materials, Inc.), of Santa Clara, Calif. Such a system is
typically used for the general purpose etching of conductive and
insulative material layers in the fabrication of integrated
circuits on substrates. The etch system 20 includes a reaction
chamber 22 having a typically grounded chamber wall and containing
an electrostatic chuck (ESC) 24 for supporting the substrate 40. An
electrode, such as a planar coil electrode 26, is positioned
adjacent to a dielectric plate (not shown) which separates the
electrode 26 from the interior of the reaction chamber 22 and acts
as an anode. The electrode 26 is connected to an RF power source
28. Plasma-generating source gases are provided to the reaction
chamber 22 by a gas supply (not shown). A bias power source 30 is
connected to the electrostatic chuck 24 for electrically biasing
the chuck 24, which acts as a cathode. Volatile reaction products
and unreacted plasma species are removed from the reaction chamber
22 by a gas removal mechanism, such as a vacuum pump through a
throttle valve (not shown), in conventional fashion.
[0031] Electrode power such as a high voltage signal is applied to
the electrode 26 to ignite and sustain a plasma 34 in the reaction
chamber 22. Ignition of a plasma 34 in the reaction chamber 22 is
accomplished primarily by electrostatic coupling of the electrode
26 with the source gases, due to the large-magnitude voltage
applied to the electrode 26 and the resulting electric fields
produced in the reaction chamber 22. Once ignited, the plasma 34 is
sustained by electromagnetic induction effects associated with
time-varying magnetic fields produced by the alternating currents
applied to the electrode 26. The plasma 34 may become
self-sustaining in the reaction chamber 22 due to the generation of
energized electrons from the source gases and striking of the
electrons with gas molecules to generate additional ions, free
radicals and electrons. The ESC 24 is typically electrically-biased
to provide ion energies that are independent of the RF voltage
applied to the electrode 26 and that impact the substrate 40.
[0032] Typically, the voltage varies as a function of position
along the coil electrode 26, with relatively higher-amplitude
voltages occurring at certain positions along the electrode 26 and
relatively lower-amplitude voltages occurring at other positions
along the electrode 26. A relatively large electric field strength
is required to ignite plasmas in the reaction chamber 22.
Accordingly, to create such an electric field it is desirable to
provide the relatively higher-amplitude voltages at locations along
the electrode 26 which are close to the grounded wall of the
reaction chamber 22.
[0033] The plasma 34 includes high-energy ions, free radicals and
electrons which react chemically with the surface material of the
substrate 40 to form reaction produces that leave the surface of
the substrate 40, thereby etching a trench in the substrate 40, as
hereinafter described. Plasma intensity depends on the type of
etchant gas or gases used, as well as the etchant gas pressure and
temperature and the radio frequency generated at the electrode 26.
If any of these factors changes during the process, the plasma
intensity may increase or decrease with respect to the plasma
intensity level required for optimum etching in a particular
application. Decreased plasma intensity results in decreased, and
thus incomplete, etching. Increased plasma intensity, on the other
hand, can cause overetching and plasma-induced damage of the
substrate 40. Plasma-induced damage includes trapped interface
charges, material defects migration into bulk materials, and
contamination caused by the deposition of etch products on material
surfaces.
[0034] Referring again to FIG. 2 in conjunction with FIGS. 3A and
3B, according to the process of the present invention a deep trench
38 having a depth of typically about 20 .mu.m is etched in the
substrate 40 for the purpose of fabricating MEMS
(microelectromechanical systems) on the substrate 40, for example.
Prior to the process of the invention, a photoresist mask 42 is
initially deposited on the surface of the substrate 40 to shield
the portions of the substrate 40 that are not to be exposed to the
etchant plasma, as well as expose the portions on the surface of
the substrate 40 which are to be exposed to the etchant plasma for
the formation of the deep trenches 38 therein. The photoresist mask
42 is typically spin-coated on the substrate 40 according to
methods which are well-known by those skilled in the art.
[0035] To begin the first step according to the process of the
invention, the substrate 40 is placed in the reaction chamber 22 of
the etch system 20, on the chuck 24. As HBr is introduced into the
reaction chamber 22 at a flow rate of typically about 0.about.20
sccm and CF.sub.4 is simultaneously introduced into the reaction
chamber 22 at a flow rate of typically about 10.about.100 sccm, for
a period of typically about 2 minutes, the reaction chamber 22 is
maintained at an interior pressure of typically about 4.about.20
mT, with a bias power of about 10.about.100 W applied to the chuck
24 via the bias power source 30 and a source power of typically
about 100.about.800 W applied to the electrode 26 via the RF power
source 28. The temperature of the cathode/chuck 24 is maintained at
a temperature of typically about 10.about.45 degrees C., whereas
the wall temperature of the reaction chamber 22 is maintained at
typically about 50.about.100 degrees C. As shown in FIG. 3A, the
first etching step heretofore described forms a tapered trench 44,
having slanted sidewalls 45 and a substantially flat bottom 46, in
the substrate 40 along the areas that remain uncovered and exposed
by the photoresist mask 42. During the etching process, a stream of
Cl.sub.2 may be introduced into the reaction chamber 22 in order to
promote polymer passivation of the slanted sidewalls 45.
[0036] As a second step according to the process of the invention,
the substrate 40 remains on the chuck 24 in the process chamber 22
while the interior pressure of the reaction chamber 22 is adjusted
to typically about 5.about.20 mT. HBr, O.sub.2 and SF.sub.6 are
introduced into the reaction chamber 22 at flow rates of typically
about 10.about.50, 30.about.100 and 30.about.100 sccm,
respectively, for a period of typically about 4.about.5 minutes. A
bias power of typically about 10.about.200 W is applied to the
chuck 24 via the bias power source 30, and a source power of
typically about 500.about.1200 W is applied to the electrode 26 via
the RF power source 28. The temperature of the cathode/chuck 24 is
maintained at a temperature of typically about 10.about.45 degrees
C. and the wall temperature of the reaction chamber 22 is
maintained at typically about 50.about.100 degrees C. This step
produces a high-density plasma 34 in the reaction chamber 22, thus
facilitating isotropic etching of the initially slanted sidewalls
45 of the tapered trench 44 to define the straight sidewalls 49 of
the deep trench 38, having the flat bottom 50.
[0037] The flow diagram of FIG. 4 summarizes the steps according to
the process of the present invention. In process step S1, a
substrate, which is typically silicon, is provided. In process step
S2, a photoresist mask is applied to the substrate typically using
conventional spin-coating techniques. The photoresist mask covers
and protects most areas on the substrate while exposing those areas
on the substrate along which the deep trench is to be formed. In
process step S3, the mask-covered substrate is placed in an etching
chamber such as a general purpose AMAT DPS etch chamber. In process
step S4, a trench having a tapered sidewall profile is initially
etched in the substrate as heretofore described with respect to
FIG. 3A. In process step S5, the tapered sidewall profile trench is
further subjected to isotropic etching using a high-density plasma
to form a deep trench having straight sidewalls and a depth of
typically about 20 .mu.m.
[0038] While the preferred embodiments of the invention have been
described above, it will be recognized and understood that various
modifications can be made in the invention and the appended claims
are intended to cover all such modifications which may fall within
the spirit and scope of the invention.
* * * * *