U.S. patent application number 10/872773 was filed with the patent office on 2005-02-03 for integrated circuit device and fabrication using metal-doped chalcogenide materials.
Invention is credited to Li, Jiutao, McTeer, Allen.
Application Number | 20050026433 10/872773 |
Document ID | / |
Family ID | 25479641 |
Filed Date | 2005-02-03 |
United States Patent
Application |
20050026433 |
Kind Code |
A1 |
Li, Jiutao ; et al. |
February 3, 2005 |
Integrated circuit device and fabrication using metal-doped
chalcogenide materials
Abstract
Methods of forming metal-doped chalcogenide layers and devices
containing such doped chalcogenide layers include using a plasma to
induce diffusion of metal into a chalcogenide layer concurrently
with metal deposition. The plasma contains at least one noble gas
of low atomic weight, such as neon or helium. The plasma has a
sputter yield sufficient to sputter a metal target and a UV
component of its emitted spectrum sufficient to induce diffusion of
the sputtered metal into the chalcogenide layer. Using such
methods, a conductive layer can be formed on the doped chalcogenide
layer in situ. In integrated circuit devices, such as non-volatile
chalcogenide memory devices, doping of the chalcogenide layer
concurrently with metal deposition and formation of a conductive
layer in situ with the doping of the chalcogenide layer reduces
contamination concerns and physical damage resulting from moving
the device substrate from tool to tool, thus facilitating improved
device reliability.
Inventors: |
Li, Jiutao; (Boise, ID)
; McTeer, Allen; (Eagle, ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L Street, NW
Washington
DC
20037
US
|
Family ID: |
25479641 |
Appl. No.: |
10/872773 |
Filed: |
June 22, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10872773 |
Jun 22, 2004 |
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10285463 |
Nov 1, 2002 |
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6800504 |
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10285463 |
Nov 1, 2002 |
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09943426 |
Aug 30, 2001 |
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6709958 |
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Current U.S.
Class: |
438/689 ;
257/E27.004; 257/E45.002 |
Current CPC
Class: |
C23C 14/0623 20130101;
C23C 14/544 20130101; C23C 14/5846 20130101; H01L 45/1658 20130101;
H01L 45/1233 20130101; H01L 45/141 20130101; H01L 45/143 20130101;
H01L 27/2409 20130101; H01L 45/085 20130101 |
Class at
Publication: |
438/689 |
International
Class: |
G03C 003/00; H01L
021/302; H01L 021/461 |
Claims
1. A method of forming a doped chalcogenide layer, comprising:
sputtering metal onto a chalcogenide layer in the presence of a
plasma containing at least one component gas selected from the
group consisting of neon and helium.
2.-55. (Cancelled)
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates generally to integrated
circuit memory devices, and in particular to the metal doping of
chalcogenide materials in the fabrication of chalcogenide memory
elements and integrated circuit devices containing such memory
elements.
BACKGROUND OF THE INVENTION
[0002] Electrically programmable and erasable materials, i.e.,
materials that can be electrically switched between a generally
resistive state and a generally conductive state are well known in
the art. Chalcogenide materials are one class of examples of such
materials finding use in the semiconductor industry, particularly
in the fabrication of non-volatile memory devices.
[0003] Chalcogenide materials are compounds made of one or more
chalcogens and one or more elements that are more electropositive
than the chalcogens. Chalcogens are the Group VIB elements of the
traditional IUPAC version of the periodic table, i.e., oxygen (O),
sulfur (S), selenium (Se), tellurium (Te) and polonium (Po). The
more electropositive elements are generally selected from Groups
IVB and VB. Typical combinations for non-volatile memory devices
include selenium and/or tellurium with germanium (Ge) and/or
antimony (Sb). However, other combinations are also known, such as
combinations of arsenic (As) and sulfur.
[0004] To obtain the desired electrical characteristics,
chalcogenide materials are often doped with metal, such as copper
(Cu), silver (Ag), gold (Au) or aluminum (Al). FIGS. 1A-1D depict
the fabrication of a simple chalcogenide memory element 100. The
basic structure of a chalcogenide memory element includes a first
electrode, a second electrode and a chalcogenide material
interposed between the first and second electrodes. Additional
detail of chalcogenide memory devices, as well as examples of
variations on the basic structure of a chalcogenide memory element,
are given in U.S. Pat. No. 5,998,244 issued Dec. 7, 1999 to
Wolstenholme et al., U.S. Pat. No. 5,920,788 issued Jul. 6, 1999 to
Reinberg, and U.S. Pat. No. 5,837,564 issued Nov. 17, 1998 to
Sandhu et al., each of which is commonly assigned with the assignee
of the present disclosure. In general, chalcogenide memory elements
are formed on a semiconductor wafer or other substrate as a portion
of an integrated circuit device.
[0005] Chalcogenide memory elements typically store a single bit,
e.g., a low resistivity (high conductivity) corresponding to a
first logic state and a high resistivity (low conductivity)
corresponding to a second logic state. Differing levels of
resistivity of the chalcogenide memory elements are sensed using
current sensing techniques well known in the art while applying a
read potential of less than the threshold potential.
[0006] Chalcogenide memory elements can be electrically switched
between conductivity states by applying varying electrical fields
to the doped chalcogenide material. By applying a programming
potential above some threshold potential, the metal dopant atoms
are believed to align in a dendritic structure, thereby forming
conductive channels and decreasing the resistivity of the
chalcogenide material. This transition is reversible by applying a
potential having an opposite polarity. A range of applied
potentials having a magnitude of less than the threshold potential,
i.e., read potentials, can be applied without altering the
resistivity of the doped chalcogenide materials. These read
potentials can be applied to the chalcogenide memory elements for
sensing the resistivity of the doped chalcogenide material and,
thus, the memory elements' data values.
[0007] Unlike dynamic random access memory (DRAM) devices, a
non-volatile memory device does not require a periodic refresh to
maintain its programmed state. Instead, non-volatile memory devices
can be disconnected from a power source for extended periods of
time, often measured in years, without the loss of the information
stored in its memory cells. Chalcogenide materials best suited for
use in non-volatile memory devices will thus tend to maintain their
degree of resistivity indefinitely if an applied voltage does not
exceed the threshold potential.
[0008] In FIG. 1A, a first electrode 110 is formed and a
chalcogenide layer 115 is formed overlying the first electrode 110.
As noted previously, electrical characteristics of chalcogenide
layer 115 may be improved through doping of the chalcogenide
material with metal. This is typically carried out through a
process known as photo-doping where diffusion of metal atoms is
photon induced. In this process, a metal layer 120 is first formed
on the chalcogenide layer 115 as shown in FIG. 1A. The metal layer
120 typically contains the copper, silver, gold, aluminum or other
high-diffusing metal. Formation of the first electrode 110 and/or
the metal layer 120 is typically performed in a vacuum chamber,
e.g., using a vacuum sputtering process.
[0009] To continue the photo-doping process in FIG. 1B,
electromagnetic radiation 125 is directed at the metal layer 120,
resulting in diffusion of metal atoms from the metal layer 120 into
the chalcogenide layer 115. The electromagnetic radiation 125 is
generally ultraviolet (UV) light. Driving metal atoms into the
chalcogenide layer 115 results in a doped chalcogenide layer 130
containing the chalcogenide material and the diffused metal. The
semiconductor wafer must generally be removed from the vacuum
chamber to expose the wafer surface to the UV light source.
[0010] The photo-doping process is generally carried out until the
metal layer 120 is completely diffused into the doped chalcogenide
layer 130 as shown in FIG. 1C. The thickness of the metal layer 120
should be chosen such that the desired doping level can be attained
in the doped chalcogenide layer 130. However, the metal layer 120
must be thin enough, e.g., hundreds of angstroms, to allow
transmission of the electromagnetic radiation 125 in order to
produce the desired photon-induced diffusion of metal. As shown in
FIG. 1D, a second electrode 150 is then formed overlying the doped
chalcogenide layer 130 and any remaining portion of the metal layer
120 to produce chalcogenide memory element 100. As with the first
electrode 110 and/or the chalcogenide layer 115, formation of the
second electrode 150 is also typically performed in a vacuum
chamber. The second electrode 150 is preferably a material having a
different work function (.PHI..sub.m) than the first electrode 110.
The work function is a measure of the energy required to remove an
electron from a material's surface.
[0011] There are several disadvantages to the traditional
photo-doping process. The process can be time consuming as the
semiconductor wafers are moved in and out of a vacuum chamber
during the various processing stages described above. This movement
of the semiconductor wafers among various process equipment also
increases the chance of contamination or other damage during
transport. Also, because the metal layer must be thin for efficient
photon-induced diffusion of metal, the desired doping level may not
be efficiently attainable with a single photo-doping process as the
necessary thickness of the metal layer may result in excessive
reflection of the electromagnetic radiation.
[0012] For the reasons stated above, and for other reasons stated
below that will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for alternative methods for producing chalcogenide
memory elements.
SUMMARY
[0013] Methods are described herein for forming metal-doped
chalcogenide layers and devices containing such doped chalcogenide
layers. The methods include using a plasma to induce diffusion of
metal into a chalcogenide layer concurrently with metal deposition.
The plasma contains at least one noble gas of low atomic weight,
such as neon or helium. The plasma has a sputter yield sufficient
to sputter a metal target and a UV component of its emitted
spectrum sufficient to induce diffusion of the sputtered metal into
the chalcogenide layer. Using such methods, a conductive layer can
be formed on the doped chalcogenide layer in situ. In integrated
circuit devices, such as non-volatile chalcogenide memory devices,
doping of a chalcogenide layer concurrently with metal deposition
and formation of a conductive layer in situ with the doping of the
chalcogenide layer reduces contamination concerns and physical
damage resulting from moving the device substrate from tool to
tool, thus facilitating improved device reliability.
[0014] For another embodiment, the invention provides a method of
forming a doped chalcogenide layer. The method includes sputtering
metal using a plasma containing at least one component gas selected
from the group consisting of neon and helium and driving the
sputtered metal into a layer of chalcogenide material using the UV
component generated by the plasma.
[0015] For a further embodiment, the invention provides a method of
forming a doped chalcogenide layer. The method includes forming a
layer of chalcogenide material and sputtering metal onto the layer
of chalcogenide material using a plasma containing at least two
noble gases. The plasma emits a spectrum having a UV component
capable of driving the sputtered metal into the layer of
chalcogenide material through UV-enhanced diffusion. For one
embodiment, the composition of the plasma is chosen to have an
average atomic weight sufficient to produce a desired sputtering
efficiency. For another embodiment, the composition of the plasma
is chosen to have a desired relative intensity of a UV component of
the emitted spectrum of the plasma. For yet another embodiment, the
composition of the plasma is chosen to have a desired emitted
spectrum of the plasma.
[0016] For one embodiment, the invention provides a method of
forming a chalcogenide memory element having a first electrode, a
second electrode, and a doped chalcogenide layer interposed between
the first electrode and the second electrode. The method includes
forming a chalcogenide layer on the first electrode, sputtering
metal onto the chalcogenide layer and diffusing metal into the
chalcogenide layer using a first plasma containing at least one
component gas selected from the group consisting of neon and
helium, thereby forming the doped chalcogenide layer, and
sputtering metal onto the chalcogenide layer using a second plasma
containing at least one component gas having an atomic weight
higher than an atomic weight of neon, thereby forming the second
electrode. For a further embodiment, the first plasma and the
second plasma are the same plasma. For a still further embodiment,
the composition of the first plasma is modified to generate the
second plasma. Such modification of the composition may occur as a
step change between sputtering stages or it may occur concurrently
with sputtering of the metal.
[0017] For another embodiment, the invention provides a method of
forming a chalcogenide memory element having a first electrode, a
second electrode, and a doped chalcogenide layer interposed between
the first electrode and the second electrode. The method includes
forming a chalcogenide layer on the first electrode, sputtering
silver onto the chalcogenide layer and diffusing silver into the
chalcogenide layer using a first plasma generated from feed gas
consisting essentially of neon, thereby forming the doped
chalcogenide layer, and sputtering silver onto the doped
chalcogenide layer using a second plasma generated from feed gas
consisting essentially of argon, thereby forming the second
electrode.
[0018] For yet another embodiment, the invention provides a method
of forming a non-volatile memory device. The method includes
forming word lines and forming first electrodes coupled to the word
lines, wherein each word line is coupled to more than one first
electrode. The method further includes forming a chalcogenide layer
on each first electrode and sputtering metal onto each chalcogenide
layer and diffusing metal into each chalcogenide layer using a
first plasma containing at least one component gas selected from
the group consisting of neon and helium, thereby forming doped
chalcogenide layers. The method still further includes sputtering
metal onto each doped chalcogenide layer using a second, different,
plasma, thereby forming second electrodes. The second plasma may
contain at least one component gas having an atomic weight higher
than the atomic weight of neon. Alternatively or additionally, the
second plasma may contain nitrogen (N.sub.2) such that the second
electrode is formed of a metal-nitride material. The method still
further includes forming bit lines coupled to the second
electrodes, wherein each bit line is coupled to more than one
second electrode. Each diode may be formed interposed between a
second electrode and a bit line, such that each second electrode is
coupled to a bit line through a diode. Alternatively, each diode
may be formed interposed between a first electrode and a word line,
such that each first electrode is coupled to a word line through a
diode.
[0019] Further embodiments of the invention include methods of
varying scope.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIGS. 1A-1D are cross-sectional views of a chalcogenide
memory element during various processing stages.
[0021] FIGS. 2A-2D are cross-sectional views of a chalcogenide
memory element during various processing stages in accordance with
an embodiment of the invention.
[0022] FIG. 3 is a schematic illustration of one physical vapor
deposition apparatus suitable for use with the embodiments of the
invention.
[0023] FIG. 4 is a schematic of a portion of a memory array in
accordance with an embodiment of the invention.
[0024] FIG. 5 is a simplified block diagram of an integrated
circuit memory device in accordance with an embodiment of the
invention.
DETAILED DESCRIPTION
[0025] In the following detailed description of the present
embodiments, reference is made to the accompanying drawings that
form a part hereof, and in which is shown by way of illustration
specific embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention, and it is to be
understood that other embodiments may be utilized and that process,
electrical or mechanical changes may be made without departing from
the scope of the present invention. The terms wafer or substrate
used in the following description include any base semiconductor
structure. Examples include silicon-on-sapphire (SOS) technology,
silicon-on-insulator (SOI) technology, thin film transistor (TFT)
technology, doped and undoped semiconductors, epitaxial layers of a
silicon supported by a base semiconductor structure, as well as
other semiconductor structures well known to one skilled in the
art. Furthermore, when reference is made to a wafer or substrate in
the following description, previous process steps may have been
utilized to form regions/junctions in the base semiconductor
structure, and the terms wafer and substrate include the underlying
layers containing such regions/junctions. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims and equivalents thereof.
[0026] FIGS. 2A-2D depict fabrication of a chalcogenide memory
element 200 as a portion of an integrated circuit device in
accordance with one embodiment of the invention. FIGS. 2A-2D are
cross-sectional views taken during various processing stages.
[0027] In FIG. 2A, a lower or first electrode 210 is formed on a
substrate (not shown). The first electrode 210 contains conductive
material. Examples include conductively doped polysilicon, carbon
(C), metals, metal alloys, metal suicides, conductive metal
nitrides and conductive metal oxides. The first electrode 210 may
further contain more than one conductive material. For example, the
first electrode 210 may contain a layer of carbon overlying a layer
of molybdenum (Mo) or a layer of tungsten (W) overlying a layer of
titanium nitride (TiN). In addition, the first electrode 210 may
include one or more adhesion or barrier layers adjacent underlying
or overlying layers. Any adhesion or barrier layer should
preferably be conductive as to not interfere with programming of
the chalcogenide memory element 200. For one embodiment, the first
electrode 210 contains silver. For a further embodiment, the first
electrode 210 is a layer of silver.
[0028] The first electrode 210 is preferably formed using a
physical vapor deposition (PVD) process. Examples include vacuum or
thermal evaporation, electron-beam evaporation and sputtering
techniques well known in the art. In a PVD process, a source or
target containing the material to be deposited is evaporated and
may include ionization of some or all of the vaporized target
material. The vaporized and/or ionized species impinging on the
substrate can then deposit on the substrate. PVD processes are
preferred for their general ability to form layers of high purity,
limited only by the purity of the source or target used in the PVD
process. However, other deposition techniques may be used, such as
a chemical vapor deposition (CVD) process in which vaporized
chemical precursors are adsorbed on the substrate surface and
reacted to form the first electrode 210.
[0029] For one embodiment, the first electrode 210 has a thickness
of approximately 500-1000 .ANG.. For a further embodiment, the
first electrode 210 has a thickness of approximately 700 .ANG..
[0030] Following formation of the first electrode 210, a
chalcogenide layer 215 is formed on the first electrode 210. As
with the first electrode 210, the chalcogenide layer 215 is
preferably formed using a PVD process, but may be formed using
other deposition techniques. For one embodiment, the chalcogenide
layer 215 contains a chalcogenide material containing one or more
Group VIB elements of the traditional IUPAC version of the periodic
table, i.e., oxygen (O), sulfur (S), selenium (Se), tellurium (Te)
and polonium (Po), and one or more Groups IVB and VB elements of
the traditional IUPAC version of the periodic table, i.e., carbon
(C), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), nitrogen
(N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).
More preferably, the chalcogenide layer 215 contains a chalcogenide
material containing a combination of selenium and/or tellurium with
germanium and/or antimony. For one embodiment, the chalcogenide
layer 215 contains a germanium selenide material (GeSe or
GeSe.sub.2).
[0031] For one embodiment, the chalcogenide layer 215 has a
thickness of approximately 300-700 .ANG.. For a further embodiment,
the chalcogenide layer 215 has a thickness of approximately 500
.ANG..
[0032] As shown in FIG. 2B, the chalcogenide layer 215 is doped
with metal 240 using a sputtering process to produce a doped
chalcogenide layer 230. The doped chalcogenide layer 230 is doped
to a desired doping level. For one embodiment, the desired doping
level produces a doped chalcogenide layer 230 saturated with the
metal 240. For another embodiment, the desired doping level
produces an oversaturated doped chalcogenide layer 230. For yet
another embodiment, the desired doping level is approximately 15-30
wt % of the metal 240 in the doped chalcogenide layer 230.
[0033] One example of an apparatus for performing sputtering may
include an ENDURA.RTM. system commercially available from Applied
Materials, Santa Clara, Calif., USA. The plasma generated in such
equipment will emit a UV component, thus providing photon-induced
diffusion during the sputtering process.
[0034] FIG. 3 is a schematic illustration of one PVD apparatus 310
suitable for use with the embodiments of the invention. Those
familiar with PVD apparatus will recognize that it is a simplified
schematic and that typical PVD apparatus may contain additional or
alternate components.
[0035] A conductive pedestal 314 containing substrate 312 is
located in a deposition chamber 316. The pedestal 314 is connected
to a DC power source 324. A gas inlet 318 is provided for
introduction of component gases into the chamber 316. The component
gases make up the plasma 322. The component gases are generally fed
to the deposition chamber 316 continuously during the operation of
the apparatus 310. As used herein, component gases do not include
any vaporized target material created during the sputter
process.
[0036] A sputter target 326 connected to a DC power source 328 is
located in the chamber 316. The target 326 may be a plate formed of
the material to be sputtered. Examples of materials to be sputtered
in the doping of the chalcogenide layer 215 include high-diffusion
metals such as copper, silver, gold and aluminum. Excess or spent
gases are drawn from the deposition chamber 316 through a vent 329
by a vacuum pump (not shown).
[0037] In the magnetron configuration, magnets 327 aid in the
development of the plasma 322. The plasma 322 is formed by the
application of a bias across the target 326 as a cathode and the
substrate 312 as an anode. Magnets 327 are often placed behind the
target 326.
[0038] In order to increase the UV component emitted by the plasma,
low molecular weight noble gases are added to the plasma. In
particular, the plasma is formed at least in part using neon (Ne)
and/or helium (He). The plasma may further contain other component
gases. One example is argon (Ar), which is commonly used in
sputtering processes. While argon's spectrum has a UV component as
well, its relative intensity is relatively low compared to that of
neon or helium, thus resulting in lower rates of metal diffusion.
For one embodiment, the plasma used during the doping process is
generated from feed gas consisting essentially of neon. For another
embodiment, the plasma used during the doping process contains
helium. For yet another embodiment, the plasma used during the
doping process contains at least argon and neon. The plasma could
also be generated from feed gas consisting essentially of helium
for its increased UV component, but such use can lead to
undesirable reductions in sputtering efficiency. Use of lower
atomic weight gases can result in much higher operating pressures
than traditional PVD processes, e.g., 30-300 mTorr.
[0039] By adjusting the volume percentages of the gases used in
generating the plasma, a plasma can be generated having an average
atomic weight anywhere between the lowest atomic weight of the
gases and the highest atomic weight of the gases. In this manner, a
plasma can be created having an average atomic weight sufficient to
facilitate a desired sputtering efficiency. Sputtering efficiency
generally refers to the number of target atoms ejected per incident
ion, typically in the range of about 0.5-1.5. Sputtering efficiency
largely determines the rate of sputter implantation or deposition.
Sputtering efficiency depends on a number of factors, including the
direction of incident ions, target material, mass of bombarding
ions, the energy of the bombarding ions, dose, crystal state and
surface binding energy.
[0040] It is noted that where more than two gases make up the
plasma, multiple combinations of these gases can produce the same
average atomic weight. For example, a mixture of 5% argon, 78% neon
and 17% helium by volume will have approximately the same average
atomic weight as a mixture of 10% argon, 67% neon and 23% helium by
volume.
[0041] By adjusting the volume percentages of the gases in the
plasma, a plasma also can be generated having a UV component that
is a composite of the spectra of the individual gases and having a
relative intensity generally between that of the lowest relative
intensity of the gases in the plasma and that of the highest
relative intensity of the gases in the plasma. In this manner, a
plasma can be created having a relative intensity of its composite
UV component sufficient to produce a desired level of
photon-induced diffusion of the sputtered metal. It is noted that
where more than two gases make up the plasma, multiple combinations
of these gases can emit UV components having the same relative
intensity.
[0042] In view of the above, it is possible to choose a plasma
having a desired relative intensity of its emitted UV component and
a desired average atomic weight through the selection of two or
more component gases and their relative volume percentages.
However, it is recognized that these values, i.e., the desired
relative intensity and the desired average atomic weight, may be
mutually exclusive. In other words, attaining one value may require
a compromise on the other. One method of compromise would be to
determine the combinations of component gases producing a plasma
having the desired relative intensity and then to choose one of
these combinations of the component gases having an average atomic
weight near the desired atomic weight. Another method would be to
determine the combinations of component gases producing a plasma
having the desired average atomic weight and then to choose one of
these combinations of the component gases having a relative
intensity of its UV component near the desired relative
intensity.
[0043] The UV components of differing plasmas may have differing
spectra, but the same relative intensity. Because the spectrum can
also affect diffusion rates, it may be desirable to produce a
specific emitted spectrum in a resulting plasma. Accordingly, for
one embodiment, a mixture of component gases is chosen to produce a
desired spectrum of the resulting plasma. For a further embodiment,
a mixture of component gases is chosen to produce a desired
spectrum of the resulting plasma having a higher level of visible
components than a plasma consisting of neon. For another
embodiment, a mixture of component gases capable of producing a
desired spectrum in a resulting plasma is chosen to produce a
target sputter efficiency. In general, the component gases of the
plasma used in the sputtering process for doping of the
chalcogenide layer 215 are selected to produce desired diffusion
and sputtering rates.
[0044] As an example of how the plasma composition affects
diffusion, an experiment was undertaken to sputter silver onto
germanium selenide using different plasmas, but otherwise
comparable processing conditions. Using a plasma generated from
feed gas consisting essentially of neon, approximately 501.6 .ANG.
of silver were sputtered onto approximately 503 .ANG. of germanium
selenide (GeSe). It is presumed that approximately 300 .ANG. of the
silver diffused into the germanium selenide layer. In contrast,
using a plasma generated from feed gas consisting essentially of
argon, and sputtering approximately 468.0 .ANG. of silver onto
approximately 503 .ANG. of germanium selenide (GeSe), approximately
336.3 .ANG. of silver were detected on the surface of the germanium
selenide. Thus, for argon, it is presumed that only approximately
131.7 .ANG. of the silver diffused into the germanium selenide
layer.
[0045] Returning to FIG. 2C, a top or second electrode 250 is
formed on the doped chalcogenide layer 230. The second electrode
250 generally follows the same guidelines as the first electrode
210. Accordingly, the second electrode 250 contains conductive
material. Examples include conductively doped polysilicon, carbon,
metals (including refractory metals), metal alloys, metal
silicides, conductive metal nitrides and conductive metal oxides.
The second electrode 250 may further contain more than one
conductive material. In addition, the second electrode 250 may
include one or more adhesion or barrier layers adjacent underlying
or overlying layers. Any adhesion or barrier layer should
preferably be conductive as to not interfere with programming of
the chalcogenide memory element 200. For one embodiment, the second
electrode 250 contains silver. For a further embodiment, the second
electrode 250 is a layer of silver.
[0046] The second electrode 250 is preferably formed using a PVD
process, but may be formed by other methods such as CVD techniques.
The second electrode 250 is more preferably formed using the same
PVD apparatus and target as used during the doping of the
chalcogenide layer 215. In this manner, the second electrode 250
may be formed in situ with the doping process, thus further
reducing risks of contamination or damage associated with transport
of the semiconductor substrate. Accordingly, for one embodiment,
the second electrode 250 is formed by sputtering metal 245 onto the
doped chalcogenide layer 230.
[0047] For one embodiment, the second electrode 250 has a thickness
of approximately 800-1200 .ANG.. For a further embodiment, the
second electrode 250 has a thickness of approximately 1000
.ANG..
[0048] For one embodiment, the component gases used during doping
of the chalcogenide layer 215 are evacuated from the deposition
chamber 316 prior to formation of the second electrode 250. For
such an embodiment, a new plasma 322 is formed with the new
component gases for the deposition of the second electrode 250. For
example, doping of the chalcogenide layer 215 can be performed
using a plasma 322 generated using a feed gas consisting
essentially of neon. The deposition chamber 316 is evacuated after
the desired doping level is attained. Subsequently, formation of
the second electrode can be performed using a plasma 322 generated
using a feed gas consisting essentially of argon. Alternatively or
additionally, the second plasma 322 may contain nitrogen or oxygen
to form conductive metal nitrides or metal oxides,
respectively.
[0049] Alternatively, the component gas feed composition could be
changed without an evacuation of the deposition chamber 316. For
example, doping of the chalcogenide layer 215 can be performed
using a component gas and plasma 322 having a first composition,
e.g., consisting essentially of neon. As the desired doping level
is approached, the component gas feed could be changed to the
second composition, e.g., consisting essentially of argon. For this
example, the concentration of argon in the plasma 322 will thus
gradually increase as argon is fed to the deposition chamber 316
and mixed gases are drawn off. As the composition of the plasma 322
changes, driving to a higher average atomic weight and/or a lower
UV component, the dynamics would shift away from diffusion and
toward deposition. To decrease the rate of change in the
composition of the plasma 322, the component gas feed composition
could be changed gradually instead of making a step change.
[0050] For another embodiment, the processing described with
reference to FIGS. 2B and 2C could be combined using a single
composition for plasma 322. For such an embodiment, the component
gases are chosen such that a desired combination of diffusion and
deposition occurs. The rate of diffusion should be high enough
relative to the rate of deposition that sufficient doping occurs
before the second electrode 250 becomes thick enough to block
further diffusion of metal into the doped chalcogenide layer
230.
[0051] FIG. 2D shows the chalcogenide memory element 200 upon
formation of the second electrode 250. The chalcogenide memory
element 200 has a doped chalcogenide layer interposed between the
first electrode 210 and the second electrode 250. The chalcogenide
memory element 200 can be used to form a chalcogenide memory cell
where the state of the doped chalcogenide layer 230 is indicative
of the data value stored by the memory cell.
[0052] FIG. 4 is a schematic showing a portion of a memory array
400 containing chalcogenide memory elements 200 as described
herein. The memory array 400 includes a number of memory cells 405
arranged generally in rows and columns. Typical memory arrays 400
contain millions of these memory cells 405. Each memory cell 405
includes a chalcogenide memory element 200 coupled between a first
conductive line, such as word line 410, and a diode 415. The diode
415 is further coupled between a second conductive line, such as
bit line 420, and the chalcogenide memory element 200.
Alternatively, the diode 415 could be coupled between the first
conductive line and the chalcogenide memory element 200. The diode
415 serves as the access device to the memory cell 300. A grouping
of memory cells 300 coupled to the same word line 410 are typically
referred to as a row of memory cells. Likewise, a grouping of
memory cells 300 coupled to the same bit line 420 are typically
referred to as a column of memory cells.
[0053] FIG. 5 is a simplified block diagram of an integrated
circuit memory device 500 in accordance with an embodiment of the
invention. The memory device 500 is a non-volatile memory device
containing chalcogenide memory elements in accordance with the
invention. The memory device 500 includes an array of memory cells
502 including the non-volatile chalcogenide memory elements. The
memory array 502 is arranged in a plurality of addressable banks.
In one embodiment, the memory contains four memory banks 504, 506,
508 and 510. Each memory bank contains addressable rows and columns
of memory cells.
[0054] The data stored in the memory array 502 can be accessed
using externally provided location addresses received by address
register 512 via address signal connections 528. The addresses are
decoded using bank decode logic 516 to select a target memory bank.
The addresses are also decoded using row decode circuitry 514 to
select the target rows. The addresses are further decoded using
column decode circuitry 518 to select one or more target
columns.
[0055] Data is input and output through I/O circuit 520 via data
connections 530. I/O circuit 528 includes data output registers,
output drivers and output buffers. Command execution logic 522 is
provided to control the basic operations of the memory device 500
in response to control signals received via control signal
connections 526. A state machine 524 may also be provided to
control specific operations performed on the memory array and
cells. The command execution logic 522 and/or state machine 524 can
be generally referred to as control circuitry to control read,
write, erase and other memory operations. The data connections 530
are typically used for bidirectional data communication. The memory
can be coupled to an external processor 550 for operation or
testing.
[0056] It will be appreciated by those skilled in the art that
additional circuitry and control signals can be provided, and that
the memory device of FIG. 5 has been simplified to help focus on
the invention. It will be understood that the above description of
a memory device is intended to provide a general understanding of
the memory and is not a complete description of all the elements
and features of a typical memory device.
[0057] As recognized by those skilled in the art, memory devices of
the type described herein are generally fabricated as an integrated
circuit containing a variety of semiconductor devices. The
integrated circuit is supported by a substrate. Integrated circuits
are typically repeated multiple times on each substrate. The
substrate is further processed to separate the integrated circuits
into dies as is well known in the art.
[0058] The foregoing figures were used to aid the understanding of
the accompanying text. However, the figures are not drawn to scale
and relative sizing of individual features and layers are not
necessarily indicative of the relative dimensions of such
individual features or layers in application. Accordingly, the
drawings are not to be used for dimensional characterization.
[0059] Although dimensional characteristics were provided herein
for information purposes, it is recognized that there is a
continuing drive to reduce integrated circuit device dimensions for
increased performance and reduced fabrication costs. In addition,
the concepts described herein are not fundamentally limited by
absolute dimensions. Accordingly, improvements in fabrication and
sensing technologies are expected to facilitate reduced dimensional
characteristics of the chalcogenide memory elements described
herein, particularly as they relate to layer thickness.
CONCLUSION
[0060] Methods have been described for forming metal-doped
chalcogenide layers and devices containing such doped chalcogenide
layers. The methods include using a plasma to induce diffusion of
metal into a chalcogenide layer concurrently with metal deposition.
The plasma contains at least one noble gas of low atomic weight,
such as neon or helium. The plasma has a sputter yield sufficient
to sputter a metal target and a UV component of its emitted
spectrum sufficient to induce diffusion of the sputtered metal into
the chalcogenide layer. Using such methods, a conductive layer can
be formed on the doped chalcogenide layer in situ. In integrated
circuit devices, such as non-volatile chalcogenide memory devices,
doping of a chalcogenide layer concurrently with metal deposition
and formation of a conductive layer in situ with the doping of the
chalcogenide layer reduces contamination concerns and physical
damage resulting from moving the device substrate from tool to
tool, thus facilitating improved device reliability.
[0061] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
Many adaptations of the invention will be apparent to those of
ordinary skill in the art. Accordingly, this application is
intended to cover any adaptations or variations of the invention.
It is manifestly intended that this invention be limited only by
the following claims and equivalents thereof.
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