U.S. patent application number 10/921497 was filed with the patent office on 2005-01-27 for multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps.
Invention is credited to Mertol, Atila, Pekin, Senol.
Application Number | 20050017368 10/921497 |
Document ID | / |
Family ID | 32594226 |
Filed Date | 2005-01-27 |
United States Patent
Application |
20050017368 |
Kind Code |
A1 |
Mertol, Atila ; et
al. |
January 27, 2005 |
Multi-level redistribution layer traces for reducing current
crowding in flipchip solder bumps
Abstract
A multi-level redistribution layer trace reduces current
crowding in solder bumps of an integrated circuit package. A
multi-level redistribution layer trace for an integrated circuit
die includes a redistribution layer trace formed on the integrated
circuit die in each of a plurality of electrically conductive
layers and an I/O pad formed at a termination of the redistribution
layer trace so that the I/O pad extends through each of the
plurality of electrically conductive layers to form an electrical
junction between the termination of the redistribution layer trace
and the I/O pad in each of the plurality of electrically conductive
layers. The redistribution layer trace may also be slotted to
divide current flow horizontally at the electrical junction between
the termination of the redistribution layer trace and the I/O pad
in each of the plurality of electrically conductive layers.
Inventors: |
Mertol, Atila; (Cupertino,
CA) ; Pekin, Senol; (San Jose, CA) |
Correspondence
Address: |
LSI LOGIC CORPORATION
1621 BARBER LANE
MS: D-106
MILPITAS
CA
95035
US
|
Family ID: |
32594226 |
Appl. No.: |
10/921497 |
Filed: |
August 18, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10921497 |
Aug 18, 2004 |
|
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10327333 |
Dec 20, 2002 |
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6818996 |
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Current U.S.
Class: |
257/773 ;
257/738; 257/E21.508; 257/E21.582; 257/E23.146; 257/E23.151;
438/737 |
Current CPC
Class: |
H01L 23/528 20130101;
H01L 21/76838 20130101; H01L 2924/01013 20130101; H01L 2924/14
20130101; H01L 2224/05016 20130101; H01L 24/11 20130101; H01L
2924/014 20130101; H01L 2224/05572 20130101; H01L 2924/01033
20130101; H01L 24/05 20130101; H01L 2224/05022 20130101; H01L
2924/01029 20130101; H01L 23/525 20130101; H01L 23/3114 20130101;
H01L 2224/05001 20130101; H01L 2224/13099 20130101; H01L 2224/05647
20130101; H01L 2924/00014 20130101; H01L 2224/05124 20130101; H01L
2924/00014 20130101; H01L 2224/05147 20130101; H01L 2924/00014
20130101; H01L 2224/05155 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/773 ;
257/738; 438/737 |
International
Class: |
H01L 023/48; H01L
023/52; H01L 029/40 |
Claims
What is claimed is:
1. A multi-level redistribution layer trace for an integrated
circuit die comprising: a redistribution layer trace formed on the
integrated circuit die in an electrically conductive layer of the
integrated circuit die; an I/O pad extending through the
electrically conductive layer to form an electrical junction
between the termination of the redistribution layer trace and the
I/O pad; and a slot formed in the redistribution layer trace to
divide the current flow horizontally at the electrical
junction.
2. A method of making a multi-level redistribution layer trace of
an integrated circuit die comprising steps for: forming a
redistribution layer trace in an electrically conductive layer of
the integrated circuit die; forming an I/O pad on the integrated
circuit die that extends through the electrically conductive layer
to form an electrical junction between the redistribution layer
trace and the I/O pad; and forming a slot in the redistribution
layer trace that extends into the redistribution layer trace from
the electrical junction between the redistribution layer trace and
the I/O pad.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of pending U.S. patent
application Ser. No. 10/327,333 by Atila Mertol et al. for
"MULTI-LEVEL REDISTRIBUTION LAYER TRACES FOR REDUCING CURRENT
CROWDING IN FLIPCHIP SOLDER BUMPS", filed on Dec. 20, 2002.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to the design of
flip-chip packages used in the manufacture of integrated circuits.
More specifically, but without limitation thereto, the present
invention relates to metal redistribution layer traces in an
integrated circuit die.
[0004] 2. Description of the Prior Art
[0005] An important issue in microelectronic packaging is
reliability. Technologies for microelectronic packaging are
developed not only to manufacture microelectronic packages at low
cost, but also to ensure that the performance of the
microelectronic packages will not deteriorate over their service
life. A critical factor in determining the service life of an
integrated circuit is the redistribution of current through the
metal redistribution layer of the integrated circuit die. The metal
redistribution layer is a conductive layer formed on a surface of
the die in which traces are formed that connect various signals and
power between the die and I/O pads formed on the surface of the
die. The I/O pads connect the signals between the traces and the
package substrate through solder bumps. In certain areas of the
solder bumps near the junctions of the traces and the I/O pads, the
current density reaches a maximum that may shorten the useful life
of the integrated circuit. The peaking of the current density at
the junctions of the traces and the I/O pads and in the solder
bumps is generally referred to as current crowding. It has been
discovered that current crowding results in the deterioration of
not only the trace junctions, which decreases the wafer level
reliability, but also the solder bumps, which decreases the package
level reliability.
SUMMARY OF THE INVENTION
[0006] In one aspect of the present invention, a multi-level
redistribution layer trace reduces current crowding in solder bumps
of an integrated circuit package. In one embodiment, a multi-level
redistribution layer trace for an integrated circuit die includes a
redistribution layer trace formed on the integrated circuit die in
each of a plurality of electrically conductive layers and an I/O
pad formed at a termination of the redistribution layer trace so
that the I/O pad extends through each of the plurality of
electrically conductive layers to form an electrical junction
between the termination of the redistribution layer trace and the
I/O pad in each of the plurality of electrically conductive
layers.
[0007] In another aspect of the present invention, a method of
making a multi-level redistribution layer trace of an integrated
circuit die includes the steps of forming a redistribution layer
trace on the integrated circuit die in each of a plurality of
electrically conductive layers, and forming an I/O pad at a
termination of the redistribution layer trace so that the I/O pad
extends through each of the plurality of electrically conductive
layers to form an electrical junction between the termination of
the redistribution layer trace and the I/O pad in each of the
plurality of electrically conductive layers.
[0008] In a further aspect of the present invention, a multi-level
redistribution layer trace of an integrated circuit die includes a
redistribution layer trace formed on the integrated circuit die in
one or more electrically conductive layers, and a slot formed in
the redistribution layer trace to divide the current flow
horizontally at an electrical junction between a termination of the
redistribution layer trace and an I/O pad.
[0009] In yet another aspect of the present invention, a method of
making a multi-level redistribution layer trace of an integrated
circuit die includes the steps of forming a redistribution layer
trace on the integrated circuit die in one or more electrically
conductive layers, and forming a slot in the redistribution layer
trace to divide the current flow horizontally at an electrical
junction between a termination of the redistribution layer trace
and an I/O pad.
DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0010] The present invention is illustrated by way of example and
not limitation in the accompanying figures, in which like
references indicate similar elements throughout the several views
of the drawings, and in which:
[0011] FIG. 1 illustrates a cross-sectional view of a conventional
flip chip package of the prior art;
[0012] FIG. 2 illustrates a cross-sectional view of a conventional
redistribution layer trace in the flipchip package of FIG. 1;
[0013] FIG. 3A illustrates a finite element model of a conventional
narrow redistribution layer trace corresponding to FIG. 2;
[0014] FIG. 3B illustrates a finite element model of a conventional
wide redistribution layer trace corresponding to FIG. 2;
[0015] FIG. 4 illustrates a computer simulation of current crowding
in a solder bump resulting from the conventional redistribution
layer trace of FIG. 3A;
[0016] FIG. 5 illustrates a cross-sectional view of a multi-level
redistribution layer trace according to an embodiment of the
present invention;
[0017] FIG. 6 illustrates a finite element model of a narrow
multi-level redistribution layer trace corresponding to FIG. 5;
[0018] FIG. 7 illustrates a finite element model of a wide
multi-level redistribution layer trace corresponding to FIG. 5;
[0019] FIGS. 8A and 8B illustrate a top view of two tapered
multi-level redistribution layer traces corresponding to FIG.
5;
[0020] FIG. 9 illustrates a computer simulation of current crowding
in a solder bump resulting from the redistribution layer trace of
FIG. 6;
[0021] FIG. 10 illustrates a flow chart of a method of making a
multi-level redistribution layer trace of an integrated circuit die
according to an embodiment of the present invention;
[0022] FIG. 11 illustrates a finite element model of a slotted
multi-level redistribution layer trace according to an embodiment
of the present invention;
[0023] FIG. 12 illustrates a flow chart of a method of making a
slotted redistribution layer trace of an integrated circuit die
according to an embodiment of the present invention; and
[0024] FIG. 13 illustrates a plot of maximum current density vs.
passivation opening diameter in a solder bump resulting from the
conventional narrow trace of FIG. 3A, the conventional wide
redistribution layer trace of FIG. 3B, and the multi-level
redistribution layer trace of FIG. 6.
[0025] Elements in the figures are illustrated for simplicity and
clarity and have not necessarily been drawn to scale. For example,
the dimensions of some of the elements in the figures may be
exaggerated relative to other elements to help to improve
understanding of embodiments of the present invention.
DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
[0026] One of the limiting factors of the service life of a
microelectronic package is electromigration. Electromigration is
the mass transport of atoms in die interconnects and solder bumps
of a microelectronic package. Since the invention of the first
integrated circuits in the 1960's, electromigration has been a
major problem. As package size and I/O pad dimensions decrease with
higher density technologies, reliability may be comprised if
measures are not taken to mitigate electromigration. Also, with the
implementation of a metal redistribution layer made of copper
instead of aluminum, the maximum current density capability of the
metal redistribution layer doubles from about 4.times.10.sup.-3
amperes per square micron to about 8.times.10.sup.-3 amperes per
square micron. The higher current density in the metal
redistribution layer results in a correspondingly higher current
density in the die interconnects and the solder bumps.
[0027] Solder bumps are especially prone to failures due to high
current crowding in the area near the junctions between the
termination of the redistribution layer traces and the I/O pads.
Reducing the maximum current density by improving the distribution
of current at junctions between the termination of the
redistribution layer traces and the I/O pads can significantly
increase the reliability of the solder bumps and consequently that
of the integrated circuit.
[0028] In one aspect of the present invention, a multi-level
redistribution layer trace reduces current crowding in solder bumps
of an integrated circuit package. In one embodiment, a multi-level
redistribution layer trace for an integrated circuit die includes a
redistribution layer trace formed on the integrated circuit die in
each of a plurality of electrically conductive layers and an I/O
pad formed at a termination of the redistribution layer trace so
that the I/O pad extends through each of the plurality of
electrically conductive layers to form an electrical junction
between the termination of the redistribution layer trace and the
I/O pad in each of the plurality of electrically conductive
layers.
[0029] FIG. 1 illustrates a cross-sectional view of a conventional
flipchip package of the prior art. Shown in FIG. 1 are a die 102,
first level interconnects 104, and a package substrate 106.
[0030] In FIG. 1, the first level interconnects 104 are solder
bumps formed between the die 102 and the package substrate 106.
[0031] FIG. 2 illustrates a cross-sectional view of a conventional
redistribution layer trace in the flipchip package of FIG. 1. Shown
in FIG. 2 are a die 102, a solder bump 104, under bump metallurgy
(UMB) 202, a passivation opening 204, an I/O pad 206, a
redistribution layer trace 208, and an I/O pad height 210.
[0032] In FIG. 2, the solder bump 104 is electrically connected to
the I/O pad 206 by the under bump metallurgy (UMB) 202. The I/O pad
206 is formed on the metal redistribution (metal-R) layer of the
die 102 at the termination of the redistribution layer trace 208.
The metal redistribution layer is an electrically conductive layer
formed on the surface of the die 102 that distributes signals and
power between the die 102 and the solder bumps 104, and is formed
according to well known chemical deposition techniques such as
evaporation, sputtering, and screen printing.
[0033] The I/O pad 206 and the redistribution layer trace 208 are
formed in the metal redistribution layer by removing selected
portions of the metal redistribution layer according to well known
photolithography techniques. The I/O pad height 210 extends to the
bottom of the redistribution layer trace 208, forming an electrical
junction between the termination of the redistribution layer trace
208 and the I/O pad 206 in the metal redistribution layer.
[0034] The passivation opening 204 is an opening formed by removing
an area around the edge of the I/O pad 206 in a passivation layer
formed on the die 102 that protects the metal redistribution layer
from contaminants. The passivation opening 204 exposes the I/O pad
206 so that the under bump metallurgy 202 may be formed on the I/O
pad 206. The solder bump 104 is then formed on the I/O pad 206
according to well-known techniques.
[0035] The under bump metallurgy 202 is formed on the I/O pad 206
through the passivation opening 204 typically has three layers (not
shown): an upper layer for promoting adhesion to the solder bump
104, a middle layer for limiting diffusion between the solder bump
104 and the I/O pad 206, and a lower layer for bonding the under
bump metallurgy 202 to the I/O pad 206. By way of example, the
upper layer may be made of copper, the middle layer may be made of
nickel, and the lower layer may be made of the same metal as the
I/O pad 206, for example, aluminum or copper.
[0036] The solder bump 104 may be formed on the under bump
metallurgy 202, for example, by a solder reflow process according
to well-known techniques.
[0037] FIG. 3A illustrates a finite element model of a conventional
narrow redistribution layer trace corresponding to FIG. 2. Shown in
FIG. 3A are solder bumps 104, I/O pads 206, and a conventional
narrow redistribution layer trace 302.
[0038] FIG. 3B illustrates a finite element model of a wide
conventional redistribution layer trace corresponding to FIG. 2.
Shown in FIG. 3B are solder bumps 104, I/O pads 206, and a
conventional wide redistribution layer trace 304.
[0039] FIG. 4 illustrates a computer simulation of current crowding
in a solder bump resulting from the conventional redistribution
layer trace of FIG. 3A. Shown in FIG. 4 are a solder bump 104, an
under bump metallurgy 202, a passivation opening 204, a low current
crowding area 402, medium current crowding areas 404, and high
current crowding areas 406.
[0040] In FIG. 4, the current density is low as illustrated by the
low current crowding area 402 except on the side of the solder bump
104 near the electrical junction of the I/O pad 206 and the
termination of the redistribution layer trace 302 in FIG. 3. The
current density increases near the electrical junction of the I/O
pad 206 and the termination of the redistribution layer trace 302
as illustrated by the medium current crowding areas 404, and
reaches a maximum along the junction of the passivation opening and
the under bump metallurgy 202 as illustrated by the high current
crowding areas 406. In this example, the maximum value of the
current density is 1.07.times.10.sup.-4 amperes per square micron
(millionth of a meter).
[0041] FIG. 5 illustrates a cross-sectional view of a narrow
multi-level redistribution layer trace according to an embodiment
of the present invention. Shown in FIG. 5 are a die 102, a solder
bump 104, under bump metallurgy 202, a passivation opening 204, a
redistribution layer trace 502, an I/O pad 503, an I/O pad height
504, electrically conductive layers 506, 508 and 510, insulating
layers 512 and 514, and a termination offset 516.
[0042] The description of FIG. 2 generally applies to FIG. 5,
except that multiple electrically conductive layers 506, 508 and
510 are formed on the die 102 to distribute signals and power
between the die 102 and the solder bumps 104 instead of the single
metal redistribution layer shown in FIG. 2. The electrically
conductive layers 506, 508 and 510 may be formed according to the
same well-known techniques used to form the single metal
redistribution layer shown in FIG. 2. Each of the electrically
conductive layers 506, 508 and 510 is electrically insulated from
one another, for example, by the insulating layers 512 and 514. The
insulating layers 512 and 514 may be formed, for example, by
depositing a layer of silicon oxide or silicon nitride on each of
the electrically conductive layers 508 and 510. In this example,
three electrically conductive layers 506, 508 and 510 are formed on
the die 102 and insulated from one another by the insulating layers
512 and 514, however, any number of electrically conductive layers
and insulating layers may be formed in the same manner to practice
various embodiments of the present invention to suit specific
applications. For example, only two electrically conductive layers
insulated from each other by a single insulating layer may be
formed in the same manner described above to practice the present
invention to suit specific applications.
[0043] The redistribution layer trace 502 may be formed in each of
the electrically conductive layers 506, 508 and 510 according to
well-known photolithography techniques. The redistribution layer
trace 502 is terminated by the I/O pad 503.
[0044] The I/O pad height 504 extends through each of the
electrically conductive layers 506, 508 and 510 to form an
electrical junction between the I/O pad 503 and the termination of
the redistribution layer trace 502 in each of the electrically
conductive layers 506, 508 and 510.
[0045] An important feature of the present invention is that the
I/O pad 503 extends completely through all the electrically
conductive layers 506, 508 and 510 so that an electrical junction
is formed between the redistribution layer trace 502 and the I/O
pad 503 in each of the electrically conductive layers 506, 508 and
510 on the die 102 without any intervening devices such as vias.
Previous methods for reducing current crowding such as disclosed by
Smooha in U.S. Pat. No. 5,969,421, incorporated herein by
reference, incorporate intervening vias between the contact pads
and conductive layers in the package substrate.
[0046] Current flowing through the redistribution layer trace 502
between the die 102 and the solder bump 104 is divided among each
of the electrically conductive layers 506, 508 and 510 so that
current flows between the I/O pad 503 and the die 102 through each
of the junctions formed between the I/O pad 503 and the termination
of the redistribution layer trace 502 in each of electrically
conductive layers 506, 508 and 510. Dividing the current among the
multiple junctions of the I/O pad 503 with the redistribution layer
trace 502 diffuses the current flow between the die 102 and the
solder bump 104 over a wider area through the under bump metallurgy
202, substantially reducing the maximum current density as well as
the area of high current density in the solder bump 104.
[0047] The current flow between the die 102 and the solder bump 104
may be further diffused by terminating the redistribution layer
trace 502 at the I/O pad 503 in each of the electrically conductive
layers 506, 508 and 510 so that the termination of the
redistribution layer trace 502 in one electrically conductive layer
is vertically offset from the termination of the redistribution
layer trace 502 in a preceding electrically conductive layer as
indicated in FIG. 5 by the termination offset 516. The termination
offset 516 may have a value ranging from zero to the diameter of
the I/O pad 503 in accordance with various embodiments of the
present invention to suit specific applications.
[0048] FIG. 6 illustrates a finite element model of a narrow
multi-level redistribution layer trace corresponding to FIG. 5.
Shown in FIG. 6 are a solder bump 104, an I/O pad 503, a
redistribution layer trace 602, and electrically conductive layers
506 and 508. In this example, the redistribution layer trace 502 is
formed in two electrically conductive layers 506 and 508 that
terminate respectively at the top and bottom of the I/O pad 503,
and the redistribution layer trace 502 has a width equal to one
side of the octagonally shaped I/O pad 503. The shape of the I/O
pad 503 is not a limiting factor of the present invention, however,
and other geometrical shapes may be used for the I/O pad 503 in
various embodiments to practice the present invention to suit
specific applications.
[0049] FIG. 7 illustrates a finite element model of a wide
multi-level redistribution layer trace corresponding to FIG. 5.
Shown in FIG. 7 are a solder bump 104, an I/O pad 503, a
redistribution layer trace 702, and electrically conductive layers
506 and 508. In this example, the redistribution layer trace 702 is
formed in two electrically conductive layers 506 and 508 that
terminate respectively at the top and bottom of the I/O pad 503,
and the redistribution layer trace 502 has a width equal to the
diameter of the octagonally shaped I/O pad 503.
[0050] FIGS. 8A and 8B illustrate a top view of two tapered
multi-level redistribution layer traces corresponding to FIG. 5.
The tapered trace designs shown in FIG. 8 may be used to practice
the present invention in various embodiments to further reduce the
maximum current density in the solder bumps 104 to suit specific
applications. Shown in FIG. 8 are I/O pads 503, a short tapered
multi-level redistribution layer trace 802 and a long tapered
multi-level redistribution layer trace 804. Both the fast tapered
multi-level redistribution layer trace 802 and the slow tapered
multi-level redistribution layer trace 804 include a tapered
portion having an initial width substantially equal to the diameter
of the I/O pad 503. The tapered portion extends from the
termination of the redistribution layer trace at the I/O pad 503 to
a termination of the tapered portion. In the fast tapered
multi-level redistribution layer trace 802, a straight portion
having a width substantially equal to a final width of the tapered
portion extends from the termination of the tapered portion. In the
slow tapered multi-level redistribution layer trace 804, there is
no straight portion, that is, the straight portion has a length of
substantially zero.
[0051] FIG. 9 illustrates a computer simulation of current crowding
in a solder bump resulting from the redistribution layer trace of
FIG. 6. Shown in FIG. 9 are a solder bump 104, an under bump
metallurgy 202, a passivation opening 204, a low current crowding
area 902, medium current crowding areas 904, and a high current
crowding area 906.
[0052] In FIG. 9, the high current crowding area 906 of the
multi-level redistribution layer trace of the present invention is
smaller than the high current crowding areas 406 of the
conventional redistribution layer trace illustrated in the computer
simulation of FIG. 4, and the maximum current density of the
multi-level redistribution layer trace is only 0.9.times.10.sup.-4
amperes per square micron compared to 1.07.times.10.sup.-4 amperes
per square micron for the conventional redistribution layer
trace.
[0053] In another aspect of the present invention, a method of
making a multi-level redistribution layer trace of an integrated
circuit die includes the steps of forming a redistribution layer
trace on the integrated circuit die in each of a plurality of
electrically conductive layers, and forming an I/O pad at a
termination of the redistribution layer trace so that the I/O pad
extends through each of the plurality of electrically conductive
layers to form an electrical junction between the termination of
the redistribution layer trace and the I/O pad in each of the
plurality of electrically conductive layers.
[0054] FIG. 10 illustrates a flow chart 1000 of a method of making
a multi-level redistribution layer trace of an integrated circuit
die according to an embodiment of the present invention.
[0055] Step 1002 is the entry point of the flow chart 1000.
[0056] In step 1004, a redistribution layer trace is formed on the
integrated circuit die in each of a plurality of electrically
conductive layers according to well-known techniques. The
redistribution layer trace may have a narrow, wide, or tapered
shape as described above to further diffuse the current flow
between the under bump metallurgy and the solder bump.
[0057] In step 1006, an I/O pad is formed at a termination of the
redistribution layer trace. The I/O pad extends through each of the
plurality of electrically conductive layers to form an electrical
junction between the termination of the redistribution layer trace
and the I/O pad in each of the plurality of electrically conductive
layers. The termination of the redistribution layer trace at the
I/O pad may be offset in each of the plurality of electrically
conductive layers to further diffuse the current flow into the
solder bump as described above.
[0058] In step 1008, a passivation opening is formed on the I/O
pad.
[0059] In step 1010, an under bump metallurgy is formed on the
passivation opening.
[0060] In step 1012, a solder bump is formed on the under bump
metallurgy.
[0061] Step 1014 is the exit point of the flow chart 1000.
[0062] In a further aspect of the present invention, a multi-level
redistribution layer trace of an integrated circuit die includes a
redistribution layer trace formed on the integrated circuit die in
one or more electrically conductive layers, and a slot formed in
the redistribution layer trace to divide the current flow
horizontally at an electrical junction between a termination of the
redistribution layer trace and an I/O pad.
[0063] FIG. 11 illustrates a finite element model of a slotted
redistribution layer trace according to embodiment of the present
invention. Shown in FIG. 11 are solder bumps 104, I/O pads 503, a
slotted multiple layer redistribution layer trace 1102,
electrically conductive layers 506 and 508, and a slot 1104.
[0064] The slot 1104 extends from the junction of the
redistribution layer trace 1102 and the I/O pad 503 into the
redistribution layer trace 1102 and may extend the entire length of
the redistribution layer trace 1102 as shown in FIG. 11.
Alternatively, the slot 1104 may extend less than the entire length
of the redistribution layer trace 1102 to practice the present
invention in various embodiments to suit specific applications.
[0065] In this example, only one slot 1104 is shown in the
redistribution layer trace 1102, however, the redistribution layer
trace 1102 may include additional slots formed in the same manner
as described above to divide the current flow horizontally at the
I/O pad 503 to practice the present invention in various
embodiments to suit specific applications.
[0066] While only two electrically conductive layers 506 and 508
are used to illustrate this example, a single electrically
conductive layer may be used to divide the current flow
horizontally at the I/O pad 503 to practice the present invention
in various embodiments to suit specific applications.
Alternatively, more than two electrically conductive layers may be
used to practice the present invention in various embodiments to
suit specific applications.
[0067] In yet another aspect of the present invention, a method of
making a multi-level redistribution layer trace of an integrated
circuit die includes the steps of forming a redistribution layer
trace on the integrated circuit die in one or more electrically
conductive layers, and forming a slot in the redistribution layer
trace to divide the current flow horizontally at an electrical
junction between a termination of the redistribution layer trace
and an I/O pad.
[0068] FIG. 12 illustrates a flow chart 1200 of a method of making
a slotted redistribution layer trace of an integrated circuit die
according to an embodiment of the present invention.
[0069] Step 1202 is the entry point of the flow chart 1200.
[0070] In step 1204, a redistribution layer trace is formed on the
integrated circuit die in at least one electrically conductive
layer as described above.
[0071] In step 1206, an I/O pad is formed on the integrated circuit
die that extends through each electrically conductive layer to form
an electrical junction between the redistribution layer trace and
the I/O pad in each electrically conductive layer as described
above.
[0072] In step 1207, a slot is formed in the redistribution layer
trace that extends into the redistribution layer trace from the
electrical junction between the redistribution layer trace and the
I/O pad in each at least one electrically conductive layer.
[0073] In step 1208, a passivation opening is formed on the I/O
pad.
[0074] In step 1210, an under bump metallurgy is formed on the
passivation opening.
[0075] In step 1212, a solder bump is formed on the under bump
metallurgy.
[0076] Step 1214 is the exit point of the flow chart 1200.
[0077] FIG. 13 illustrates a plot of passivation opening diameter
vs. maximum current density for the conventional narrow trace of
FIG. 3A, the conventional wide redistribution layer trace of FIG.
3B, and the multi-level redistribution layer trace of FIG. 6. The
passivation opening diameter is defined by the width of the
intersection of the passivation 204, the I/O pad 206, and the first
level interconnect 104 in FIG. 6.
[0078] The points plotted in the plot of FIG. 13 correspond to the
maximum current density of each corresponding redistribution layer
trace design. The conventional narrow redistribution layer trace
has the highest maximum current density. The conventional wide
redistribution layer has the next highest maximum current density,
and the multi-level redistribution layer trace of the present
invention has the lowest maximum current density.
[0079] Although the methods of the present invention illustrated by
the flowchart descriptions above are described and shown with
reference to specific steps performed in a specific order, these
steps may be combined, sub-divided, or reordered without departing
from the scope of the claims. Unless specifically indicated herein,
the order and grouping of steps is not a limitation of the present
invention.
[0080] While the invention herein disclosed has been described by
means of specific embodiments and applications thereof, other
modifications, variations, and arrangements of the present
invention may be made in accordance with the above teachings other
than as specifically described to practice the invention within the
spirit and scope defined by the following claims.
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