U.S. patent application number 10/458413 was filed with the patent office on 2004-12-16 for high on-current device for high performance embedded dram (edram) and method of forming the same.
Invention is credited to Cheng, Tzyy-Ming, Divakaruni, Rama, Iyer, Subramanian S., Khan, Babar A..
Application Number | 20040251512 10/458413 |
Document ID | / |
Family ID | 33434914 |
Filed Date | 2004-12-16 |
United States Patent
Application |
20040251512 |
Kind Code |
A1 |
Khan, Babar A. ; et
al. |
December 16, 2004 |
HIGH ON-CURRENT DEVICE FOR HIGH PERFORMANCE EMBEDDED DRAM (EDRAM)
AND METHOD OF FORMING THE SAME
Abstract
A method for enhancing the on-current carrying capability of a
MOSFET device is disclosed. In an exemplary embodiment, the method
includes recessing fill material formed within a shallow trench
isolation (STI) adjacent the MOSFET so as to expose a desired depth
of a sidewall of the STI, thereby increasing the effective size of
a parasitic corner device of the MOSFET. The threshold voltage of
the parasitic corner device is then adjusted so as to be
substantially equivalent to the threshold voltage of the MOSFET
device.
Inventors: |
Khan, Babar A.; (Ossining,
NY) ; Divakaruni, Rama; (Ossining, NY) ; Iyer,
Subramanian S.; (Mount Kisco, NY) ; Cheng,
Tzyy-Ming; (Hsinchu City, TW) |
Correspondence
Address: |
Sean F. Sullivan, Esq.
Cantor Colburn LLP
55 Griffin Road South
Bloomfield
CT
06002
US
|
Family ID: |
33434914 |
Appl. No.: |
10/458413 |
Filed: |
June 10, 2003 |
Current U.S.
Class: |
257/510 ;
257/513; 257/516; 257/E21.345; 257/E21.628; 257/E21.642;
257/E21.654; 257/E21.661; 257/E21.682; 438/221; 438/296 |
Current CPC
Class: |
H01L 21/823878 20130101;
H01L 27/10873 20130101; H01L 21/823481 20130101; H01L 27/11
20130101; H01L 27/11521 20130101; H01L 21/26586 20130101 |
Class at
Publication: |
257/510 ;
257/513; 438/221; 438/296; 257/516 |
International
Class: |
H01L 029/00; H01L
021/8238 |
Claims
What is claimed is:
1. A method for enhancing the on-current carrying capability of a
MOSFET device, the method comprising: recessing fill material
formed within a shallow trench isolation (STI) adjacent the MOSFET
so as to expose a desired depth of a sidewall of the STI, thereby
increasing the effective size of a parasitic corner device of the
MOSFET; and adjusting the threshold voltage of said parasitic
corner device so as to be substantially equivalent to the threshold
voltage of the MOSFET device.
2. The method of claim 1, wherein said adjusting said threshold
voltage of said parasitic corner device comprising implanting the
exposed portions of said sidewall with a dopant material.
3. The method of claim 2, wherein said exposed portions of side
wall are implanted with an angled implant.
4. The method of claim 1, wherein the effective size of said
parasitic corner device is selected such that the magnitude of
on-current of said parasitic corner device is substantially
equivalent to the magnitude of on-current of the MOSFET device.
5. The method of claim 1, wherein said STI material is recessed by
a first etch process, said first etch process being implemented
before the removal of a pad nitride formed over an active area of a
substrate in which the MOSFET is defined, and wherein said
implanting is performed subsequent to said first etch process.
6. The method of claim 5, further comprising: refilling said STI
with additional said fill material; performing a second etch in
which a portion of the refilled STI is removed so as to effectively
extend a gate insulator layer over said sidewall of said STI; and
depositing a gate conductor layer over said gate insulator
layer.
7. A semiconductor device, comprising: a MOSFET disposed adjacent a
shallow trench isolation (STI); and said MOSFET including a gate
oxide layer formed over an active device area and a corner region
defined by said STI, said STI further having a sufficient amount of
fill material therein removed so as to allow the formation of said
gate oxide layer to increase the effective size of a parasitic
corner device; wherein said corner region is further implanted with
a dopant so as adjust the threshold voltage of said parasitic
corner device to be substantially equivalent to the threshold
voltage of the MOSFET.
8. The device of claim 7, wherein the effective size of said
parasitic corner device is selected such that the magnitude of
on-current of said parasitic corner device is substantially
equivalent to the magnitude of on-current of the MOSFET.
9. An embedded, dynamic random access memory (eDRAM) device,
comprising: an array of memory storage devices associated with a
plurality of MOSFET devices for accessing said memory storage
devices, each of said MOSFET devices disposed adjacent a shallow
trench isolation (STI); and each of said MOSFET devices including a
gate oxide layer formed over an active device area and a corner
region defined by said STI, said STI further having a sufficient
amount of fill material therein removed so as to allow the
formation of said gate oxide layer to increase the effective size
of a parasitic corner device; wherein said corner region is further
implanted with a dopant so as adjust the threshold voltage of said
parasitic corner device to be substantially equivalent to the
threshold voltage of the MOSFET.
10. The eDRAM device of claim 7, wherein the effective size of said
parasitic corner device is selected such that the magnitude of
on-current of said parasitic corner device is substantially
equivalent to the magnitude of on-current of the MOSFET.
Description
BACKGROUND
[0001] The present invention relates generally to semiconductor
device manufacturing and, more particularly, to an embedded dynamic
random access (eDRAM) device having a high on-current for high
performance thereof.
[0002] In the integrated circuit (IC) industry, manufacturers have
been embedding dynamic random access memory (DRAM) arrays on the
same substrate as microprocessor cores or other logic devices. This
technology is commonly referred to as embedded DRAM (eDRAM).
Embedded DRAM provides microcontrollers and other logic devices
with faster access to larger capacities of on-chip memory at a
lower cost than other currently available systems having
conventional embedded static random access memory (SRAM) and/or
electrically erasable programmable read only memory (EEPROM).
[0003] At the same time, the semiconductor industry continually
strives to increase semiconductor device performance and density by
miniaturizing the individual semiconductor components and by
miniaturizing the overall semiconductor device dimensions. For
example, the semiconductor device density can be increased by more
densely integrating the components on the semiconductor chip.
However, increasing integration densities by placing the individual
circuit elements in closer proximity increases the potential for
interactions between the circuit elements. Therefore, it has become
necessary to include isolation structures to prevent any
significant interaction between circuit elements on the same
chip.
[0004] Contemporary CMOS technologies generally employ field
effect-transistors that are adjacent or bounded by trenches. These
trenches provide isolation (shallow trench isolation or "STI") for
the semiconductor devices. As is known in the art, the close
proximity of each semiconductor device to an edge or corner of the
trench may create parasitic leakage paths. These parasitic leakage
paths result from an enhancement of the gate electric field near
the trench corners, the gate electric field in turn being enhanced
by the trench corner's small radius of curvature and the proximity
of the gate conductor. As a result of the enhanced gate electric
field, the trench corner has a lower threshold voltage (V.sub.t)
than the planar portion of the device.
[0005] Ideally, in an eDRAM device, the DRAM is embedded within the
logic without affecting the performance of the logic device.
However, as a practical matter, there are device design constraints
imposed by the logic processing steps, such as relating to spacer
and oxide thicknesses. These processes are kept preferably the same
for the DRAM, so that the manufacturing costs of the eDRAM may be
minimized. At the same time, the eDRAM should include a high
performance DRAM, meaning that the on-current of the DRAM devices
should remain high, (even as device dimensions shrink), without
compromising the device off-current. Unfortunately, this becomes
more and more difficult as cell and device size shrinks. In
particular, the reduced diffusion width of the DRAM devices in
succeeding technologies has a proportionate impact (i.e., a
decrease) on the device on-current. Accordingly, it is desirable to
be able to fabricate a reduced width eDRAM device that is still a
high-performance device by having a relatively high on-current
capability.
SUMMARY
[0006] The foregoing discussed drawbacks and deficiencies of the
prior art are overcome or alleviated by a method for enhancing the
on-current carrying capability of a MOSFET device. In an exemplary
embodiment, the method includes recessing fill material formed
within a shallow trench isolation (STI) adjacent the MOSFET so as
to expose a desired depth of a sidewall of the STI, thereby
increasing the effective size of a parasitic corner device of the
MOSFET. The threshold voltage of the parasitic corner device is
then adjusted so as to be substantially equivalent to the threshold
voltage of the MOSFET device.
[0007] In another aspect, a semiconductor device includes a MOSFET
disposed adjacent a shallow trench isolation (STI). The MOSFET
includes a gate oxide layer formed over an active device area and a
corner region defined by the STI, the STI further having a
sufficient amount of fill material therein removed so as to allow
the formation of the gate oxide layer to increase the effective
size of a parasitic corner device. The corner region is further
implanted with a dopant so as to adjust the threshold voltage of
the parasitic corner device to be substantially equivalent to the
threshold voltage of the MOSFET.
[0008] In yet another aspect, an embedded, dynamic random access
memory (eDRAM) device includes an array of memory storage devices
associated with a plurality of MOSFET devices for accessing the
memory storage devices, wherein each of the MOSFET devices is
disposed adjacent a shallow trench isolation (STI). Further, each
of the MOSFET devices includes a gate oxide layer formed over an
active device area and a corner region defined by the STI. The STI
has a sufficient amount of fill material therein removed so as to
allow the formation of the gate oxide layer to increase the
effective size of a parasitic corner device. The corner region is
further implanted with a dopant so as adjust the threshold voltage
of the parasitic corner device to be substantially equivalent to
the threshold voltage of the MOSFET.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Referring to the exemplary drawings wherein like elements
are numbered alike in the several Figures:
[0010] FIG. 1 is a sectional view of a MOSFET device having a
parasitic corner device as result of conventional shallow trench
isolation (STI) formation techniques;
[0011] FIG. 2 is a graph illustrating characteristic current versus
gate voltage curves for both the channel device and the parasitic
corner device in the MOSFET of FIG. 1;
[0012] FIG. 3 is a plan view of a section of a semiconductor memory
device, such as an eDRAM, suitable for use in accordance with an
embodiment of the invention; and
[0013] FIGS. 4 and 5 are sectional views, taken along the line 4-4
of FIG. 3, illustrating a method for enhancing the on-current of a
MOSFET device, in accordance with an embodiment of the
invention.
DETAILED DESCRIPTION
[0014] Disclosed herein is an embedded DRAM device (and method of
forming the same) having an increased on-current without physically
increasing the cell size thereof. Briefly stated, the present
disclosure effectively creates a "wider" device by deliberately
increasing the size of a parasitic device, thereby allowing for an
increased on-current of the regular channel DRAM device. The
threshold voltage of this larger device is then adjusted so as to
be compatible with (and become a part of) the channel device.
[0015] As opposed to conventional processes, the present disclosure
does not seek to reduce, suppress or eliminate the effects of the
parasitic corner device. Rather, the size and current carrying
capability of the parasitic corner device is actually enhanced (and
threshold voltage thereof is also adjusted) so as to increase the
current carrying capability of the channel device. Thus, for
example, as diffusion widths shrink below 0.14 .mu.m, an equivalent
corner device which is 0.03 .mu.m wide can actually increase the
effective device width to about 0.2 .mu.m, thereby allowing for
substantially higher on-currents and device performance without
increasing the cell area.
[0016] Referring initially to FIG. 1, there is shown a sectional
view of a MOSFET device 10 having a parasitic corner device as
result of conventional shallow trench isolation (STI) formation
techniques. The MOSFET device 10 is formed on a lightly doped
substrate 12, over which is formed a gate oxide layer 14 (or other
suitable gate insulating material) above a channel 16. Adjacent the
gate oxide layer 14 is an STI region 18 that is separated from the
substrate 12 by a sidewall 20. The sidewall 20 forms a corner 22
having a radius "r" and a corner angle .theta. with respect to the
lower surface of the gate oxide layer 14. To the right of the
corner 22, there is shown a depression 24 formed in the surface of
the STI region 18, thereby causing the gate to wrap around the
corner 22 following the deposition of the doped polysilicon layer
26 that serves as the gate conductor.
[0017] Because of the combination of the steep slope of the
sidewall 20 and the depression 24, an applied gate voltage results
in an enhanced electric field at the corner 22 of the active area.
Thus, this resulting corner device can lead to high off-currents
and variations in the threshold voltage of the transistor, as the
threshold voltage of the corner devices is lower than the threshold
voltage of the main device. FIG. 2 is a graph illustrating
characteristic current versus gate voltage curves for both the
channel device and the corner device. As can be seen, the parasitic
corner device (dashed curve) has a lower threshold voltage than the
channel device (solid curve), thus leading to higher off-currents
that are a component of the overall DRAM storage cell leakage.
Moreover, the actual total device current will be the sum of the
two device currents. Accordingly, the on-current contribution of a
corner device in a conventional transistor will not be significant
where the corner device width is relatively small.
[0018] As stated previously, existing processes have been directed
toward minimizing the effects of the corner device, such as by
ensuring that the top surface of the STI is above that of the
silicon substrate, or by simply increasing the threshold voltage of
the sidewall by implanting dopants therein. In contrast, the
present invention embodiments use the corner device in an
advantageous manner, as is described hereinafter in further
detail.
[0019] Referring generally now to FIGS. 3 through 5, there is shown
an exemplary structure and method in which a larger corner device
is fashioned for use in applications such as eDRAM. Those skilled
in the art, however, will appreciate, that the device embodiments
herein may be used in other suitable semiconductor applications. In
particular, FIG. 3 is a top view of a section of eDRAM array 100
illustrating a plurality of deep trenches 102 (in which individual
memory storage devices, i.e., capacitors, are formed), gate
conductor lines 104, and active area diffusion regions 106. Those
skilled in the art will recognize that the MOSFET gate stack
devices are formed at the intersections 108 of the gate conductor
lines 104 and the diffusion regions 106. The individual MOSFET
devices formed by the gate stack devices and diffusion regions are
used as access transistors for reading data from and writing data
to the storage devices within the deep trenches 102. Elsewhere, the
array 100 includes a plurality of shallow trench isolations (STIs)
adjacent the active area diffusion regions 106, as is seen more
particularly in FIGS. 4 and 5.
[0020] FIG. 4 is a sectional view of the eDRAM array 100, taken
along the line 4-4 of FIG. 3. As can be seen, the STIs 1 10 are
formed on opposing sides of the active areas of a given MOSFET
device, including the channel regions 112 directly underneath the
gate stack devices, and into the semiconductor substrate 114. As
opposed to a conventional memory device or other semiconductor
device, the STI oxide is etched down or recessed in a first etch
step so as to expose an additional surface area of the substrate
114 adjacent the corner regions. Preferably, the first etch step is
done just before a pad nitride 116 in the gate stack is removed.
Alternatively, the first etch may also be selectively implemented
in the array by using a block mask and photolithography
techniques.
[0021] In either case, the STI oxide material is recessed to a
sufficient depth "d" (up to, for example, about 1000 .ANG.) in
order to accommodate an angled corner implantation step for the
adjustment of the corner/sidewall device threshold voltage,
indicated by the arrows in FIG. 4. Once the sidewalls are
implanted, the gate polysilicon 118 is conformally deposited so as
to wrap around the corners and a portion of the sidewalls, as seen
in FIG. 5, thereby effectively creating a wider device having
increased current on-current capability and with a consistent
threshold voltage of the main device and the corner/sidewall
device. As compared with the parasitic corner device illustrated in
FIG. 1, the deliberately fabricated, wider parasitic device of the
present disclosure takes advantage of both the corner region (see
22 of FIG. 1) and the sidewall region (see 20 of FIG. 1). Moreover,
since both the corner and sidewall areas are implanted so as to
result in a consistent threshold voltage, the combination thereof
effectively serves a single, larger parasitic device than just a
corner device.
[0022] In order to ensure that an adequate area of the exposed
substrate sidewalls are exposed for the voltage threshold
adjustment implantation step, the first etch may be carried out a
greater depth than is actually desired for the poly-gate fill.
After the implantation, the STI areas may be refilled with oxide
material and then subsequently recessed with a second etch process
to a shallower depth than for the first etch process, before then
depositing the gate conductor material.
[0023] As will be appreciated, the above described method and
structure allows for improved eDRAM performance by increasing the
on-current capability of the main device without increasing the
cell area of the MOSFET corner device is actually enhanced. So long
as the threshold voltage of the enhanced parasitic corner devices
is adjusted to be substantially equivalent to that of the main
device, the parasitic device increases the current carrying
capability of the channel device. Moreover, this is accomplished
without a significant impact on device off-current.
[0024] While the invention has been described with reference to a
preferred embodiment or embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted for elements thereof without departing from the
scope of the invention. In addition, many modifications may be made
to adapt a particular situation or material to the teachings of the
invention without departing from the essential scope thereof.
Therefore, it is intended that the invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention will include
all embodiments falling within the scope of the appended
claims.
* * * * *