Divakaruni; Rama

Patent Applications and Registrations

Patent applications and USPTO patent grants for Divakaruni; Rama.The latest application filed is for "conductive contacts in semiconductor on insulator substrate".

Company Profile

1.43.33

Divakaruni; Rama - Ossining NY
Divakaruni; Rama - Ossing NY
Divakaruni; Rama - Somers NY
Divakaruni; Rama - Middletown NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Conductive contacts in semiconductor on insulator substrate Grant 11,177,285 - Cheng , et al. November 16, 2	2021-11-16
Conductive contacts in semiconductor on insulator substrate Grant 10,734,410 - Cheng , et al.	2020-08-04
Conductive Contacts In Semiconductor On Insulator Substrate App 20200058677 - Cheng; Kangguo ; et al.	2020-02-20
Conductive Contacts In Semiconductor On Insulator Substrate App 20180076220 - Cheng; Kangguo ; et al.	2018-03-15
Conductive contacts in semiconductor on insulator substrate Grant 9,685,535 - Cheng , et al. June 20, 2	2017-06-20
Fin isolation structures facilitating different fin isolation schemes Grant 9,673,222 - Jacob , et al. June 6, 2	2017-06-06
Fin Isolation Structures Facilitating Different Fin Isolation Schemes App 20160260742 - JACOB; Ajey Poovannummoottil ; et al.	2016-09-08
Method of fabricating self-aligned bipolar transistor having tapered collector Grant 7,615,457 - Akatsu , et al. November 10, 2	2009-11-10
High performance FET with elevated source/drain region Grant 7,566,599 - Divakaruni , et al. July 28, 2	2009-07-28
Integration Scheme For Multiple Metal Gate Work Function Structures App 20090108356 - Cheng; Kangguo ; et al.	2009-04-30
Method of fabricating self-aligned bipolar transistor having tapered collector App 20080318373 - Akatsu; Hiroyuki ; et al.	2008-12-25
Method of fabricating a bipolar transistor having reduced collector-base capacitance Grant 7,462,547 - Akatsu , et al. December 9, 2	2008-12-09
Structure and method of self-aligned bipolar transistor having tapered collector Grant 7,425,754 - Akatsu , et al. September 16, 2	2008-09-16
Method of fabricating semiconductor side wall fin Grant 7,361,556 - Adkisson , et al. April 22, 2	2008-04-22
Method of fabricating semiconductor side wall fin Grant 7,265,417 - Adkisson , et al. September 4, 2	2007-09-04
Fabrication of bipolar transistor having reduced collector-base capacitance App 20070096259 - Akatsu; Hiroyuki ; et al.	2007-05-03
Bipolar transistor having reduced collector-base capacitance Grant 7,190,046 - Akatsu , et al. March 13, 2	2007-03-13
Method of fabricating semiconductor side wall fin App 20070026617 - Adkisson; James W. ; et al.	2007-02-01
Structure of vertical strained silicon devices Grant 7,170,126 - Cheng , et al. January 30, 2	2007-01-30
Method of fabricating semiconductor side wall fin Grant 7,163,864 - Adkisson , et al. January 16, 2	2007-01-16
Double gate trench transistor Grant 7,112,845 - Adkisson , et al. September 26, 2	2006-09-26
High density chip carrier with integrated passive devices Grant 7,030,481 - Chudzik , et al. April 18, 2	2006-04-18
Nitrided STI liner oxide for reduced corner device impact on vertical device performance Grant 6,998,666 - Beintner , et al. February 14, 2	2006-02-14
High performance FET with elevated source/drain region App 20050260801 - Divakaruni, Rama ; et al.	2005-11-24
Forming collar structures in deep trench capacitors with thermally stable filler material Grant 6,967,137 - Belyansky , et al. November 22, 2	2005-11-22
N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same Grant 6,964,892 - Clevenger , et al. November 15, 2	2005-11-15
High density chip carrier with integrated passive devices Grant 6,962,872 - Chudzik , et al. November 8, 2	2005-11-08
Pitcher-shaped active area for field effect transistor and method of forming same Grant 6,960,514 - Beintner , et al. November 1, 2	2005-11-01
Structure And Method Of Making A Bipolar Transistor Having Reduced Collector-based Capacitance App 20050212087 - Akatsu, Hiroyuki ; et al.	2005-09-29
Structure And Method Of Forming A Bipolar Transistor Having A Void Between Emitter And Extrinsic Base App 20050199907 - Divakaruni, Rama ; et al.	2005-09-15
Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base Grant 6,940,149 - Divakaruni , et al. September 6, 2	2005-09-06
Structure And Method Of Self-aligned Bipolar Transistor Having Tapered Collector App 20050184359 - Akatsu, Hiroyuki ; et al.	2005-08-25
Filling high aspect ratio isolation structures with polysilazane based material App 20050179112 - Belyansky, Michael P. ; et al.	2005-08-18
Nitrided Sti Liner Oxide For Reduced Corner Device Impact On Vertical Device Performance App 20050151181 - Beintner, Jochen ; et al.	2005-07-14
Method for forming TTO nitride liner for improved collar protection and TTO reliability Grant 6,897,107 - Divakaruni , et al. May 24, 2	2005-05-24
Reduced cap layer erosion for borderless contacts Grant 6,890,815 - Faltermeier , et al. May 10, 2	2005-05-10
Self-aligned Array Contact For Memory Cells App 20050077562 - Divakaruni, Rama ; et al.	2005-04-14
Self-aligned array contact for memory cells Grant 6,870,211 - Divakaruni , et al. March 22, 2	2005-03-22
Filling high aspect ratio isolation structures with polysilazane based material Grant 6,869,860 - Belyansky , et al. March 22, 2	2005-03-22
Method And Structure Of Vertical Strained Silicon Devices App 20050059214 - Cheng, Kangguo ; et al.	2005-03-17
Bulk Contact Mask Process App 20050054158 - Divakaruni, Rama ; et al.	2005-03-10
Reduced Cap Layer Erosion For Borderless Contacts App 20050051839 - Faltermeier, Johnathan ; et al.	2005-03-10
High performance FET with elevated source/drain region Grant 6,864,540 - Divakaruni , et al. March 8, 2	2005-03-08
High density chip carrier with integrated passive devices App 20050023664 - Chudzik, Michael Patrick ; et al.	2005-02-03
Forming Collar Structures In Deep Trench Capacitors With Thermally Stable Filler Material App 20050009267 - Belyansky, Michael P. ; et al.	2005-01-13
Method of fabricating semiconductor side wall fin App 20050001216 - Adkisson, James W. ; et al.	2005-01-06
High On-current Device For High Performance Embedded Dram (edram) And Method Of Forming The Same App 20040251512 - Khan, Babar A. ; et al.	2004-12-16
Filling High Aspect Ratio Isolation Structures With Polysilazane Based Material App 20040248374 - Belyansky, Michael P. ; et al.	2004-12-09
High on-current device for high performance embedded DRAM (eDRAM) and method of forming the same Grant 6,821,857 - Khan , et al. November 23, 2	2004-11-23
TTO nitride liner for improved collar protection and TTO reliability Grant 6,809,368 - Divakaruni , et al. October 26, 2	2004-10-26
Integration scheme for enhancing capacitance of trench capacitors Grant 6,806,138 - Cheng , et al. October 19, 2	2004-10-19
Structure and methods for process integration in vertical DRAM cell fabrication Grant 6,790,739 - Malik , et al. September 14, 2	2004-09-14
Pitcher-shaped active area for field effect transistor and method of forming same App 20040173858 - Beintner, Jochen ; et al.	2004-09-09
TTO nitride liner for improved collar protection and TTO reliability App 20040155275 - Divakaruni, Rama ; et al.	2004-08-12
Field-shield-trench isolation for gigabit DRAMs Grant 6,762,447 - Mandelman , et al. July 13, 2	2004-07-13
High density chip carrier with integrated passive devices App 20040108587 - Chudzik, Michael Patrick ; et al.	2004-06-10
Pitcher-shaped active area for field effect transistor and method of forming same Grant 6,746,933 - Beintner , et al. June 8, 2	2004-06-08
TTO nitride liner for improved collar protection and TTO reliability App 20040106258 - Divakaruni, Rama ; et al.	2004-06-03
PMOSFET device with localized nitrogen sidewall implantation Grant 6,724,053 - Divakaruni , et al. April 20, 2	2004-04-20
Structure and method for dual work function logic devices in vertical DRAM process Grant 6,635,526 - Malik , et al. October 21, 2	2003-10-21
Structure And Methods For Process Integration In Vertical Dram Cell Fabrication App 20030186502 - Malik, Rajeev ; et al.	2003-10-02
Structure and methods for process integration in vertical DRAM cell fabrication Grant 6,620,676 - Malik , et al. September 16, 2	2003-09-16
Process flow for thick isolation collar with reduced length Grant 6,605,838 - Mandelman , et al. August 12, 2	2003-08-12
DRAM array bit contact with relaxed pitch pattern App 20030116784 - Divakaruni, Rama ; et al.	2003-06-26
Trench isolation processes using polysilicon-assisted fill Grant 6,566,228 - Beintner , et al. May 20, 2	2003-05-20
Structure and methods for process integration in vertical DRAM cell fabrication App 20030003653 - Malik, Rajeev ; et al.	2003-01-02
Transistors having independently adjustable parameters Grant 6,501,131 - Divakaruni , et al. December 31, 2	2002-12-31
Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation Grant 6,498,061 - Divakaruni , et al. December 24, 2	2002-12-24
Double gate trench transistor Grant 6,472,258 - Adkisson , et al. October 29, 2	2002-10-29
TTO nitride liner for improved collar protection and TTO reliability App 20020149047 - Divakaruni, Rama ; et al.	2002-10-17
Double gate trench transistor App 20020140039 - Adkisson, James W. ; et al.	2002-10-03
Trench capacitor with an intrinsically balanced field across the dielectric Grant 6,441,423 - Mandelman , et al. August 27, 2	2002-08-27
Shared body and diffusion contact structure and method for fabricating same Grant 6,429,477 - Mandelman , et al. August 6, 2	2002-08-06
Negative Ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation App 20020068399 - Divakaruni, Rama ; et al.	2002-06-06
Method and device for array threshold voltage control by trapped charge in trench isolation Grant 6,348,394 - Mandelman , et al. February 19, 2	2002-02-19
Dram Cell With Active Area Reclaim App 20010042880 - DIVAKARUNI, RAMA ; et al.	2001-11-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.