U.S. patent application number 10/873102 was filed with the patent office on 2004-11-25 for methods of forming vertical power devices having trench-based source electrodes with sidewall source contacts.
Invention is credited to Baliga, Bantval Jayant.
Application Number | 20040232479 10/873102 |
Document ID | / |
Family ID | 25263519 |
Filed Date | 2004-11-25 |
United States Patent
Application |
20040232479 |
Kind Code |
A1 |
Baliga, Bantval Jayant |
November 25, 2004 |
Methods of forming vertical power devices having trench-based
source electrodes with sidewall source contacts
Abstract
Methods of forming vertical power devices include the steps of
forming a lateral-channel MOSFET having a base region of second
conductivity type within the semiconductor substrate and a source
region of first conductivity type within the base region. A trench
is also formed in the semiconductor substrate. The trench has
sidewalls that define an interface with the source and base
regions. The sidewalls of the trench are lined with a trench
insulating layer and an electrically conductive region is formed on
the trench insulating layer. An upper portion of the trench
insulating layer is removed to expose a portion of the base region
extending along the interface. A source electrode is then formed
that ohmically contacts the source region, the exposed portion of
the base region and the electrically conductive region, which
operates as a trench-based electrode.
Inventors: |
Baliga, Bantval Jayant;
(Raleigh, NC) |
Correspondence
Address: |
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH
NC
27627
US
|
Family ID: |
25263519 |
Appl. No.: |
10/873102 |
Filed: |
June 21, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10873102 |
Jun 21, 2004 |
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09833132 |
Apr 11, 2001 |
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6781194 |
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Current U.S.
Class: |
257/327 ;
257/E29.04; 257/E29.066; 257/E29.118; 257/E29.257; 257/E29.338 |
Current CPC
Class: |
H01L 29/407 20130101;
H01L 29/41766 20130101; H01L 29/7802 20130101; H01L 29/66727
20130101; H01L 29/7806 20130101; H01L 29/1095 20130101; H01L 29/402
20130101; H01L 29/41741 20130101; H01L 29/0878 20130101 |
Class at
Publication: |
257/327 |
International
Class: |
H01L 029/76 |
Claims
1-53. (Cancelled)
54. A method of forming a vertical power device, comprising the
steps of: forming a plurality of trenches in a surface of a
semiconductor substrate having a drift region of first conductivity
type therein that extends adjacent the surface; lining the
plurality of trenches with trench insulating layers; forming
electrically conductive regions on the trench insulating layers;
implanting transition region dopants of first conductivity type at
a first dose level and first energy level into the drift region;
forming a gate electrode that extends opposite the implanted
transition region dopants, on the surface; implanting shielding
region dopants of second conductivity type at a second dose level
and second energy level into the surface, using the gate electrode
as an implant mask; implanting base region dopants of second
conductivity type at a third dose level and third energy level into
the surface, using the gate electrode as an implant mask; driving
the implanted transition, shielding and base region dopants into
the substrate to define a transition region that extends in the
drift region, first and second shielding regions that extend on
opposite sides of the transition region and form respective P--N
rectifying junctions therewith and first and second base regions
that extend on opposite sides of the transition region and form
respective P--N rectifying junctions therewith; forming source
regions of first conductivity type in the first and second base
regions; etching back portions of the trench insulating layers to
expose the source, base and shielding regions; and forming a source
contact that ohmically contacts the exposed source, base and
shielding regions and the electrically conductive regions.
55. The method of claim 54, wherein said step of implanting
transition region dopants comprises implanting transition region
dopants into the conductive regions within the plurality of
trenches and into mesas defined between the plurality of
trenches.
56. The method of claim 54, wherein the first and second energy
levels are at respective levels that cause a depth of a peak second
conductivity type dopant concentration in the shielding region to
be within 10% of a depth of a peak first conductivity type dopant
concentration in the transition region, when the depths of the
peaks are measured relative to the surface.
57. The method of claim 54, wherein the gate electrode is an
insulated gate electrode; wherein the transition region extends to
an interface between the insulated gate electrode and the surface;
and wherein a peak first conductivity type dopant concentration in
the transition region is greater than about ten times a surface
dopant concentration in the transition region.
58. The method of claim 54, wherein the second dose level is
greater than the third dose level; and wherein the second energy
level is greater than the third energy level.
59. A method of forming a vertical power device, comprising the
steps of: forming a trench in a semiconductor substrate having a
drift region of first conductivity type therein that extends
adjacent a sidewall of the trench; lining the trench with a trench
insulating layer; forming a trench-based electrode on the trench
insulating layer; forming an insulated gate electrode on a surface
of the substrate; forming a base region of second conductivity type
that extends in the substrate and to the sidewall of the trench;
forming a source region of first conductivity type that extends in
the base region and to the sidewall of the trench; etching back a
portion of the trench insulating layer to expose portions of the
base and source regions that extend along the sidewall of the
trench; and forming a source contact that ohmically contacts the
exposed portions of the base and source regions.
60. A method of forming a vertical power device, comprising the
steps of: forming a lateral-channel MOSFET having a base region of
second conductivity type within the semiconductor substrate and a
source region of first conductivity type within the base region;
forming a trench in the semiconductor substrate, said trench having
sidewalls that define an interface with the base region; lining the
sidewalls of said trench with a trench insulating layer; forming an
electrically conductive region on the trench insulating layer;
removing an upper portion of the trench insulating layer to expose
a portion of the base region extending along the interface; and
forming a source electrode ohmically contacting the source region,
the exposed portion of the base region and the electrically
conductive region.
Description
REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. application Ser.
No. 09/833,132, filed Apr. 11, 2001, the disclosure of which is
hereby incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to semiconductor switching
devices, and more particularly to switching devices for power
switching and power amplification applications and methods of
forming same.
BACKGROUND OF THE INVENTION
[0003] Power MOSFETs have typically been developed for applications
requiring power switching and power amplification. For power
switching applications, the commercially available devices are
typically DMOSFETs and UMOSFETs. In these devices, one main
objective is obtaining a low specific on-resistance to reduce power
losses. In a power MOSFET, the gate electrode provides turn-on and
turn-off control upon the application of an appropriate gate bias.
For example, turn-on in an N-type enhancement MOSFET occurs when a
conductive N-type inversion-layer channel (also referred to as
"channel region") is formed in the P-type base region in response
to the application of a positive gate bias. The inversion-layer
channel electrically connects the N-type source and drain regions
and allows for majority carrier conduction therebetween.
[0004] The power MOSFET's gate electrode is separated from the base
region by an intervening insulating layer, typically silicon
dioxide. Because the gate is insulated from the base region, little
if any gate current is required to maintain the MOSFET in a
conductive state or to switch the MOSFET from an on-state to an
off-state or vice-versa. The gate current is kept small during
switching because the gate forms a capacitor with the MOSFET's base
region. Thus, only charging and discharging current ("displacement
current") is required during switching. Because of the high input
impedance associated with the insulated-gate electrode, minimal
current demands are placed on the gate and the gate drive circuitry
can be easily implemented. Moreover, because current conduction in
the MOSFET occurs through majority carrier transport through an
inversion-layer channel, the delay associated with the
recombination and storage of excess minority carriers is not
present. Accordingly, the switching speed of power MOSFETs can be
made orders of magnitude faster than that of bipolar transistors.
Unlike bipolar transistors, power MOSFETs can be designed to
withstand high current densities and the application of high
voltages for relatively long durations, without encountering the
destructive failure mechanism known as "second breakdown". Power
MOSFETs can also be easily paralleled, because the forward voltage
drop across power MOSFETs increases with increasing temperature,
thereby promoting an even current distribution in parallel
connected devices.
[0005] DMOSFETs and UMOSFETs are more fully described in a textbook
by B. J. Baliga entitled Power Semiconductor Devices, PWS
Publishing Co. (ISBN 0-534-94098-6) (1995), the disclosure of which
is hereby incorporated herein by reference. Chapter 7 of this
textbook describes power MOSFETs at pages 335-425. Examples of
silicon power MOSFETs including accumulation, inversion and
extended trench FETs having trench gate electrodes extending into
the N+ drain region are also disclosed in an article by T. Syau, P.
Venkatraman and B. J. Baliga, entitled Comparison of Ultralow
Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET,
INVFET, and Convention UMOSFETs, IEEE Transactions on Electron
Devices, Vol. 41, No. 5, May (1994). As described by Syau et al.,
specific on-resistances in the range of 100-250 .mu..OMEGA.cm.sup.2
were experimentally demonstrated for devices capable of supporting
a maximum of 25 volts. However, the performance of these devices
was limited by the fact that the forward blocking voltage must be
supported across the gate oxide at the bottom of the trench. U.S.
Pat. No. 4,680,853 to Lidow et al. also discloses a conventional
power MOSFET that utilizes a highly doped N+ region 130 between
adjacent P-base regions in order to reduce on-state resistance. For
example, FIG. 22 of Lidow et al. discloses a high conductivity
region 130 having a constant lateral density and a gradient from
relatively high concentration to relatively low concentration
beginning from the chip surface beneath the gate oxide and
extending down into the body of the chip.
[0006] FIG. 1(d) from the aforementioned Syau et al. article
discloses a conventional UMOSFET structure. In the blocking mode of
operation, this UMOSFET supports most of the forward blocking
voltage across the N-type drift layer, which must be doped at
relatively low levels to obtain a high maximum blocking voltage
capability, however low doping levels typically increase the
on-state series resistance. Based on these competing design
requirements of high blocking voltage and low on-state resistance,
a fundamental figure of merit for power devices has been derived
which relates specific on-resistance (R.sub.on,sp) to the maximum
blocking voltage (BV). As explained at page 373 of the
aforementioned textbook to B. J. Baliga, the ideal specific
on-resistance for an N-type silicon drift region is given by the
following relation:
R.sub.on,sp=5.93.times.10.sup.-9(BV).sup.2.5 (1)
[0007] Thus, for a device with 60 volt blocking capability, the
ideal specific on-resistance is 170 .mu..OMEGA.cm.sup.2. However,
because of the additional resistance contribution from the channel,
reported specific on-resistances for UMOSFETs are typically much
higher. For example, a UMOSFET having a specific on-resistance of
730 .mu..OMEGA.cm.sup.2 is disclosed in an article by H. Chang,
entitled Numerical and Experimental Comparison of 60V Vertical
Double-Diffused MOSFETs and MOSFETs With A Trench-Gate Structure,
Solid-State Electronics, Vol. 32, No. 3, pp. 247-251, (1989).
However, in this device a lower-than-ideal uniform doping
concentration in the drift region was required to compensate for
the high concentration of field lines near the bottom corner of the
trench when blocking high forward voltages. U.S. Pat. Nos.
5,637,989 and 5,742,076 and U.S. application Ser. No. 08/906,916,
filed Aug. 6, 1997, the disclosures of which are hereby
incorporated herein by reference, also disclose popular power
semiconductor devices having vertical current carrying
capability.
[0008] In particular, U.S. Pat. No. 5,637,898 to Baliga discloses a
preferred silicon field effect transistor which is commonly
referred to as a graded-doped (GD) UMOSFET. As illustrated by FIG.
3 from the '898 patent, a unit cell 100 of an integrated power
semiconductor device field effect transistor may have a width
"W.sub.c" of 1 .mu.m and comprise a highly doped drain layer 114 of
first conductivity type (e.g., N+) substrate, a drift layer 112 of
first conductivity type having a linearly graded doping
concentration therein, a relatively thin base layer 116 of second
conductivity type (e.g., P-type) and a highly doped source layer
118 of first conductivity type (e.g., N+). The drift layer 112 may
be formed by epitaxially growing an N-type in-situ doped
monocrystalline silicon layer having a thickness of 4 .mu.m on an
N-type drain layer 114 having a thickness of 100 .mu.m and a doping
concentration of greater than 1.times.10.sup.18 cm.sup.-3 (e.g.
1.times.10.sup.19 cm.sup.-3) therein. The drift layer 112 also has
a linearly graded doping concentration therein with a maximum
concentration of 3.times.10.sup.17 cm.sup.-3 at the N+/N junction
with the drain layer 114, and a minimum concentration of
1.times.10.sup.16 cm.sup.-3 beginning at a distance 3 .mu.m from
the N+/N junction (i.e., at a depth of 1 .mu.m) and continuing at a
uniform level to the upper face. The base layer 116 may be formed
by implanting a P-type dopant such as boron into the drift layer
112 at an energy of 100 kEV and at a dose level of
1.times.10.sup.14 cm.sup.-2. The P-type dopant may then be diffused
to a depth of 0.5 .mu.m into the drift layer 112. An N-type dopant
such as arsenic may also be implanted at an energy of 50 kEV and at
dose level of 1.times.10.sup.15 cm.sup.-2. The N-type and P-type
dopants can then be diffused simultaneously to a depth of 0.5 .mu.m
and 1.0 .mu.m, respectively, to form a composite semiconductor
substrate containing the drain, drift, base and source layers.
[0009] A stripe-shaped trench having a pair of opposing sidewalls
120a which extend in a third dimension (not shown) and a bottom
120b is then formed in the substrate. For a unit cell 100 having a
width W.sub.c of 1 .mu.m, the trench is preferably formed to have a
width "W.sub.t" of 0.5 .mu.m at the end of processing. An insulated
gate electrode, comprising a gate insulating region 124 and an
electrically conductive gate 126 (e.g., polysilicon), is then
formed in the trench. The portion of the gate insulating region 124
extending adjacent the trench bottom 120b and the drift layer 112
may have a thickness "T.sub.1" of about 2000 .ANG. to inhibit the
occurrence of high electric fields at the bottom of the trench and
to provide a substantially uniform potential gradient along the
trench sidewalls 120a. The portion of the gate insulating region
124 extending opposite the base layer 116 and the source layer 118
may have a thickness "T.sub.2" of about 500 .ANG. to maintain the
threshold voltage of the device at about 2-3 volts. Simulations of
the unit cell 100 at a gate bias of 15 Volts confirm that a
vertical silicon field effect transistor having a maximum blocking
voltage capability of 60 Volts and a specific on-resistance
(R.sub.sp,on) of 40 .mu..OMEGA.cm.sup.2, which is four (4) times
smaller than the ideal specific on-resistance of 170
.mu..OMEGA.cm.sup.2 for a 60 volt power UMOSFET, can be achieved.
Notwithstanding these excellent characteristics, the transistor of
FIG. 3 of the '898 patent may suffer from a relatively low
high-frequency figure-of-merit (HFOM) if the overall gate-to-drain
capacitance (C.sub.GD) is too large. Improper edge termination of
the MOSFET may also prevent the maximum blocking voltage from being
achieved. Additional UMOSFETs having graded drift regions and
trench-based source electrodes are also disclosed in U.S. Pat. No.
5,998,833 to Baliga, the disclosure of which is hereby incorporated
herein by reference.
[0010] Power MOSFETs may also be used in power amplification
applications (e.g., audio or rf). In these applications the
linearity of the transfer characteristic (e.g., I.sub.d v. V.sub.g)
becomes very important in order to minimize signal distortion.
Commercially available devices that are used in these power
amplification applications are typically the LDMOS and gallium
arsenide MESFETs. However, as described below, power MOSFETs
including LDMOS transistors, may have non-linear characteristics
that can lead to signal distortion. The physics of current
saturation in power MOSFETs is described in a textbook by S. M. Sze
entitled "Physics of Semiconductor Devices, Section 8.2.2, pages
438-451 (1981). As described in this textbook, the MOSFET typically
works in one of two modes. At low drain voltages (when compared
with the gate voltage), the MOSFET operates in a linear mode where
the relationship between I.sub.d and V.sub.g is substantially
linear. Here, the transconductance (g.sub.m) is also independent of
V.sub.g:
g.sub.m=(Z/L)u.sub.nsC.sub.oxV.sub.d (2)
[0011] where Z and L are the channel width and length,
respectively, u.sub.ns is the channel mobility, C.sub.ox is the
specific capacitance of the gate oxide, and V.sub.d is the drain
voltage. However, once the drain voltage increases and becomes
comparable to the gate voltage (V.sub.g), the MOSFET operates in
the saturation mode as a result of channel pinch-off. When this
occurs, the expression for transconductance can be expressed
as:
g.sub.m=(Z/L)u.sub.nsC.sub.ox(V.sub.g-V.sub.th) (3)
[0012] where V.sub.g represents the gate voltage and V.sub.th
represents the threshold voltage of the MOSFET. Thus, as
illustrated by equation (3), during saturation operation, the
transconductance increases with increasing gate bias. This makes
the relationship between the drain current (on the output side) and
the gate voltage (on the input side) non-linear because the drain
current increases as the square of the gate voltage. This
non-linearity can lead to signal distortion in power amplifiers. In
addition, once the voltage drop along the channel becomes large
enough to produce a longitudinal electric field of more than about
1.times.10.sup.4 V/cm while remaining below the gate voltage, the
electrons in the channel move with reduced differential mobility
because of carrier velocity saturation.
[0013] Thus, notwithstanding attempts to develop power MOSFETs for
power switching and power amplification applications, there
continues to be a need to develop power MOSFETs that can support
high voltages and have improved electrical characteristics,
including highly linear transfer characteristics when supporting
high voltages.
SUMMARY OF THE INVENTION
[0014] Vertical power devices according to embodiments of the
present invention utilize retrograded-doped transition regions to
enhance forward on-state and reverse breakdown voltage
characteristics. Highly doped shielding regions may also be
provided that extend adjacent the transition regions and contribute
to depletion of the transition regions during both forward on-state
conduction and reverse blocking modes of operation.
[0015] A vertical power device (e.g., MOSFET) according to a first
embodiment of the invention comprises a semiconductor substrate
having first and second trenches and a drift region of first
conductivity type (e.g., N-type) therein that extends into a mesa
defined by and between the first and second trenches. The drift
region is preferably nonuniformly doped and may have a retrograded
doping profile relative to an upper surface of the substrate in
which the first and second trenches are formed. In particular, the
substrate may comprise a highly doped drain region of first
conductivity type and a drift region that extends between the drain
region and the upper surface. The doping profile in the drift
region may decrease monotonically from a nonrectifying junction
with the drain region to the upper surface of the substrate and an
upper portion of the drift region may be uniformly doped at a
relatively low level (e.g., 1.times.10.sup.16 cm.sup.-3). First and
second insulated electrodes may also be provided in the first and
second trenches. These first and second insulated electrodes may
constitute trench-based source electrodes in a three-terminal
device.
[0016] First and second base regions of second conductivity type
(e.g., P-type) are also provided in the mesa. These base regions
preferably extend adjacent sidewalls of the first and second
trenches, respectively. First and second highly doped source
regions of first conductivity type are also provided in the first
and second base regions, respectively. An insulated gate electrode
is provided that extends on the mesa. The insulated gate electrode
is patterned so that the upper surface preferably defines an
interface between the insulated gate electrode and the first and
second base regions. Inversion-layer channels are formed within the
first and second base regions during forward on-state conduction,
by applying a gate bias of sufficient magnitude to the insulated
gate electrode.
[0017] A transition region of first conductivity type is also
provided in the mesa. This transition region preferably extends
between the first and second base regions and extends to the
interface with the insulated gate electrode. The transition region
may also form a non-rectifying junction with the drift region and
has a vertically retrograded first conductivity type doping profile
relative to the upper surface. This doping profile has a peak
doping concentration at a first depth relative to the upper
surface, which may extend in a range from about 0.2 to 0.5 microns
relative to the upper surface. Between the first depth and the
upper surface, the doping profile is preferably monotonically
decreasing in a direction towards the upper surface. A magnitude of
a portion of a slope of this monotonically decreasing profile is
preferably greater that 3.times.10.sup.21 cm.sup.-4. The
establishment of a "buried" peak at the first depth may be achieved
by performing a single implant step at respective dose and energy
levels or by performing multiple implant steps at respective dose
levels and different energy levels. The peak dopant concentration
in the transition region is preferably greater than at least about
two (2) times the transition region dopant concentration at the
upper surface. More preferably, the peak dopant concentration in
the transition region is greater than about ten (10) times the
transition region dopant concentration at the upper surface.
[0018] According to preferred aspects of power devices of the first
embodiment, a product of the peak first conductivity type dopant
concentration in the transition region (at the first depth) and a
width of the transition region at the first depth is in a range
between 1.times.10.sup.12 cm.sup.-2 and 7.times.10.sup.12 cm.sup.-2
and, more preferably, in a range between about 3.5.times.10.sup.12
cm.sup.-2 and about 6.5.times.10.sup.12 cm.sup.-2. Depending on
unit cell design within an integrated multi-celled device, the
product of the peak first conductivity type dopant concentration in
the transition region and a width of the non-rectifying junction
between the transition region and the drift region may also be in a
range between 1.times.10.sup.12 cm.sup.-2 and 7.times.10.sup.12
cm.sup.-2. A product of the peak first conductivity type dopant
concentration in the transition region, a width of the transition
region at the first depth and a width of the mesa may also be set
at a level less than 2.times.10.sup.15 cm.sup.-1. To achieve
sufficient charge coupling in the drift region mesa, a product of
the drift region mesa width and quantity of first conductivity type
charge in a portion of the drift region mesa extending below the
transition region is preferably in a range between 2.times.10.sup.9
cm.sup.-1 and 2.times.10.sup.10 cm.sup.-1.
[0019] According to further aspects of the first embodiment,
enhanced forward on-state and reverse blocking characteristics can
be achieved by including highly doped shielding regions of second
conductivity type that extend in the mesa and on opposite sides of
the transition region. In particular, a first shielding region of
second conductivity type is provided that extends between the first
base region and the drift region and is more highly doped than the
first base region. Similarly, a second shielding region of second
conductivity type is provided that extends between the second base
region and the drift region and is more highly doped than the
second base region. To provide depletion during forward on-state
and reverse blocking modes of operation, the first and second
shielding regions form respective P--N rectifying junctions with
the transition region. High breakdown voltage capability may also
be achieved by establishing a product of the peak first
conductivity type dopant concentration in the transition region and
a width between the first and second shielding regions in a range
between 1.times.10.sup.12 cm.sup.-2 and 7.times.10.sup.12
cm.sup.-2.
[0020] Integrated vertical power devices according to a second
embodiment of the invention preferably comprise active unit cells
that provide forward on-state current and dummy cells that remove
heat from the active cells during forward on-state conduction and
support equivalent maximum reverse blocking voltages. According to
the second embodiment, each integrated unit cell may comprise an
active unit cell and one or more dummy unit cells. In addition to
the first and second trenches, a third trench may be provided in
the semiconductor substrate. The first and second trenches define
an active mesa, in which an active unit cell is provided, and the
second and third trenches define a dummy mesa therebetween in which
a dummy unit cell is provided. A dummy base region of second
conductivity type is provided in the dummy mesa preferably along
with a dummy shielding region. The dummy base and shielding regions
preferably extend across the dummy mesa and may be electrically
connected to the first and second source regions within the active
unit cell. In the event one or more dummy unit cells is provided,
uniform reverse blocking voltage characteristics can be achieved by
making the width of the mesa, in which the active unit cell is
provided, equal to a width of the respective dummy mesa in which
each of the dummy unit cells is provided. Alternatively, and in
place of the third dummy base region, a field plate insulating
layer may be provided on an upper surface of the dummy mesa and a
third insulated electrode may be provided in the third trench. The
source electrode may extend on the field plate insulating layer and
is electrically connected to the first, second and third insulated
electrodes within the trenches. In the event a field plate
insulating layer is provided on the dummy mesa instead of using a
dummy base region, the spacing between the first and second
trenches need not necessarily equal the spacing between the second
and third trenches in order to support maximum blocking
voltages.
[0021] Additional embodiments of the present invention also include
methods of forming vertical power devices. These methods preferably
include implanting transition region dopants of first conductivity
type at a first dose level and first energy level into a surface of
a semiconductor substrate having a drift region of first
conductivity type therein that extends adjacent the surface. An
insulated gate electrode may then be formed on the surface. The
insulated gate electrode is preferably patterned so that it extends
opposite the implanted transition region dopants. Shielding region
dopants of second conductivity type are then implanted at a second
dose level and second energy level into the surface. This implant
step is preferably performed in a self-aligned manner with respect
to the gate electrode, by using the gate electrode as an implant
mask. Base region dopants of second conductivity type are also
implanted at a third dose level and third energy level into the
surface, using the gate electrode as an implant mask. Accordingly,
the base and shielding region dopants are self-aligned to each
other.
[0022] A thermal treatment step is then performed to drive the
implanted transition, shielding and base region dopants into the
substrate and define a transition region, first and second
shielding regions on opposite sides of the transition region and
first and second base regions on opposite sides of the transition
region. The transition region extends into the drift region and has
a vertically retrograded first conductivity type doping profile
therein relative to the surface. This retrograded profile is
achieved by establishing a buried peak dopant concentration
sufficiently below the surface. The first and second shielding
regions form respective P--N rectifying junctions with the
transition region and the first and second base regions also form
respective P--N rectifying junctions with the transition region.
The dose and implant energies associated with the base and
shielding region dopants are also selected so that the shielding
regions are more highly doped relative to the base regions and
extend deeper into the substrate.
[0023] According to a preferred aspect of this embodiment, the
first dose and energy levels and a duration of the thermal
treatment step are of sufficient magnitude that a product of a peak
first conductivity type dopant concentration in the transition
region and a width of the transition region, as measured between
the first and second shielding regions, is in a range between
1.times.10.sup.12 cm.sup.-2 and 7.times.10.sup.12 cm.sup.-2. The
first and second energy levels may also be set to cause a depth of
a peak second conductivity type dopant concentration in the
shielding region to be within 10% of a depth of a peak first
conductivity type dopant concentration in the transition region,
when the depths of the peaks are measured relative to the
surface.
[0024] The step of implanting shielding region dopants is also
preferably preceded by the step of forming trenches in the
semiconductor substrate and lining the trenches with trench
insulating layers. Conductive regions are also formed on the trench
insulating layers. These trench related steps may be performed
before the step of implanting the transition region dopants. In
this case, the transition region dopants are preferably implanted
into the conductive regions within the trenches and into mesas that
are defined by the trenches. According to still further preferred
aspects of this embodiment, steps are also performed to increase
maximum on-state current density within the power device by
improving the configuration of the source contact. In particular,
the source contact is formed on a sidewall of the trenches by
etching back the trench insulating layers to expose the source,
base and shielding regions and then forming a source contact that
ohmically contacts the conductive regions and also contacts the
source, base and shielding regions at the sidewall of each
trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a cross-sectional view of a vertical power device
according to a first embodiment of the present invention.
[0026] FIG. 2 is a cross-sectional view of a vertical power device
according to a second embodiment of the present invention.
[0027] FIG. 3 is a cross-sectional view of a vertical power device
according to a third embodiment of the present invention.
[0028] FIG. 4 is a cross-sectional view of a vertical power device
according to a fourth embodiment of the present invention.
[0029] FIG. 5 is a cross-sectional view of a vertical power device
according to a fifth embodiment of the present invention.
[0030] FIG. 6 is a cross-sectional view of a vertical power device
according to a sixth embodiment of the present invention.
[0031] FIG. 7 is a cross-sectional view of a vertical power device
according to a seventh embodiment of the present invention.
[0032] FIG. 8A is a graphical illustration of a preferred
vertically retrograded doping profile across the transition region
of the embodiment of FIG. 1, obtained by performing multiple
implants of transition region dopants at respective different
energies.
[0033] FIG. 8B is a graphical illustration of a preferred vertical
doping profile across the source, base and shielding regions of the
embodiment of FIG. 1.
[0034] FIGS. 9A-9K are cross-sectional views of intermediate
structures that illustrate preferred methods of forming the
vertical power device of FIG. 5.
[0035] FIG. 10 is a cross-sectional view of a vertical power device
according to another embodiment of the present invention.
[0036] FIG. 11 is a cross-sectional view of a vertical power device
that includes a dummy gate electrode electrically connected to a
source electrode, according to another embodiment of the present
invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
[0037] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. This invention
may, however, be embodied in different forms and should not be
construed as limited to the embodiments set forth herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the
thickness of layers and regions are exaggerated for clarity. It
will also be understood that when a layer is referred to as being
"on" another layer or substrate, it can be directly on the other
layer or substrate, or intervening layers may also be present.
Moreover, the terms "first conductivity type" and "second
conductivity type" refer to opposite conductivity types such as N
or P-type, however, each embodiment described and illustrated
herein includes its complementary embodiment as well. Like numbers
refer to like elements throughout.
[0038] Referring now to FIG. 1, an integrated vertical power device
10 according to a first embodiment of the present invention
includes a plurality of active vertical power device unit cells
located side-by-side in a semiconductor substrate. As illustrated,
the power device 10 comprises a highly doped drain region 100 of
first conductivity type (shown as N+) and a drift region 102 of
first conductivity type that forms a non-rectifying junction with
the drain region 100. A drain electrode 136 is also provided in
ohmic contact with the drain region 100. The drain region 100 may
have a thickness in a range between about 10 microns and about 500
microns. The drift region 102 is preferably nonuniformly doped. In
particular, the drift region 102 preferably has a graded doping
profile which decreases monotonically in a direction extending from
the non-rectifying junction to a first surface 102a of the drift
region 102. This graded doping profile may be a linearly graded
doping profile that decreases from a preferred maximum drift region
dopant concentration in a range between about 1.times.10.sup.17 and
about 2.5.times.10.sup.17 cm.sup.-3 to a minimum dopant
concentration. Accordingly, if the drain region 100 is doped at a
level of about 1.times.10.sup.19 cm.sup.-3 or greater, then the
non-rectifying junction will be an abrupt non-rectifying junction.
An upper portion of the drift region 102 may be uniformly doped at
a level of about 1.times.10.sup.16 cm.sup.-3 and the uniformly
doped upper portion of the drift region 102 may have a thickness in
a range between about 0.5 and about 1.0 .mu.m.
[0039] A plurality of trenches 104 may be formed in the drift
region 102. If trenches are provided, the trenches 104 are
preferably formed side-by-side in the drift region 102 as parallel
stripe-shaped trenches, however, other less preferred trench shapes
(e.g., ring-shaped) may also be used. As described herein, regions
will be defined as separate regions if they appear as such when
viewed in transverse cross-section. Each pair of trenches
preferably defines a drift region mesa 102b therebetween, as
illustrated. An electrically insulating layer 106 is also provided
on the sidewalls and bottoms of the trenches 104. The "trench"
insulating layer 106 may have a thickness of about 3000 .ANG.,
however, the thickness may vary depending, among other things, on
the rating of the power device 10. The electrically insulating
layer 106 may comprise silicon dioxide or another conventional
dielectric material. Each of the trenches 104 is preferably filled
with a conductive region 110 that is electrically insulated from
the drift region 102 by a respective electrically insulating layer
106. The conductive regions 110 may constitute trench-based
electrodes that are electrically connected together by a source
electrode 138. This source contact/electrode 138 may extend on the
first surface 102a of the drift region 102, as illustrated.
[0040] Upper uniformly doped portions of the drift region mesas
102b preferably comprise respective transition regions 130 of first
conductivity type. The transition regions 130 form respective
non-rectifying junctions with the drift region 102 and, depending
on thickness, may form respective non-rectifying junctions with the
uniformly doped upper portions of the drift region 102 or the
graded doped portions of the drift region 102. For example, the
uniformly doped upper portions of the drift region 102 may have a
thickness of about 1.0 .mu.m relative to the first surface 102a and
the transition regions 130 may have thicknesses of about 0.7 .mu.m
relative to the first surface 102a. Moreover, according to a
preferred aspect of the present invention, each transition region
130 has a first conductivity type doping profile therein that is
vertically retrograded relative to the first surface 102a. In
particular, a peak first conductivity type dopant concentration at
a first depth in the transition region is at least two (2) times
greater than a value of the retrograded first conductivity type
doping profile at the first surface 102a. More preferably, the peak
first conductivity type dopant concentration in the transition
region is at least about ten (10) times greater than the value of
the first conductivity type dopant concentration at the first
surface. According to another preferred aspect, a slope of at least
a portion of the retrograded first conductivity type doping profile
is greater than about 3.times.10.sup.21 cm.sup.-4. The doping
profile in the transition region 130 also includes a high-to-low
graded profile in a direction extending downward from the peak to
the non-rectifying junction between the transition region 130 and
the drift region 102. A desired doping profile may be achieved by
performing a single transition region implant step at relatively
high energy and dose or performing multiple implant steps. For
example, as illustrated by FIG. 8A, a relatively wide peak in the
transition region doping profile may be achieved by performing
three implant steps at respective energies (and same or similar
dose levels) to achieve first, second and third implant depths of
about 0.15, 0.3 and 0.45 microns, using a dopant having a
characteristic diffusion length of about 0.1 microns.
[0041] Gate electrodes 118 are provided on the first surface 102a,
as illustrated. These gate electrodes 118 may be stripe-shaped and
may extend parallel to the trench-based electrodes 110. As
illustrated, the gate electrodes 118 preferably constitute
insulated gate electrodes (e.g., MOS gate electrodes). The vertical
power device 10 also comprises highly doped shielding regions 128
of second conductivity type (shown as P+) that are formed at spaced
locations in the drift region mesas 102b. These shielding regions
128 are preferably self-aligned to the gate electrodes 118. Each of
the shielding regions 128 preferably forms a P--N rectifying
junction with a respective side of the transition region 130 and
with a respective drift region mesa 102b (or tail of the transition
region 130). According to a preferred aspect of the present
invention, the peak second conductivity type dopant concentration
in each shielding region 128 is formed at about the same depth
(relative to the first surface 102a) as the peak first conductivity
type dopant concentration in a respective transition region 130.
Base regions 126 of second conductivity type (shown as P) are also
formed in respective drift region mesas 102b. Each base region 126
is preferably self-aligned to a respective gate electrode 118.
Highly doped source regions 133 of first conductivity type (shown
as N+) are also formed in respective base regions 126, as
illustrated. The spacing along the first surface 102a between a
source region 133 and a respective edge of the transition region
130 defines the channel length of the power device 10. These source
regions 133 ohmically contact the source electrode 138. Edge
termination may also be provided by extending the source electrode
138 over peripheral drift region extensions 102c and by
electrically isolating the source electrode 138 from the peripheral
drift region extensions 102c by a field plate insulating region
125.
[0042] The combination within each drift region mesa 102b of (i) a
pair of spaced-apart shielding regions 128 and (ii) a preferred
transition region 130 that extends between the shielding regions
128 and has a vertically retrograded doping profile, can enhance
the breakdown voltage characteristics of each active unit cell in
the multi-celled power device 10. In particular, the shielding
regions 128 can operate to "shield" the respective base regions 126
by significantly suppressing P-base reach-through effects when the
power device 10 is blocking reverse voltages and causing reverse
current to flow through the shielding regions 128 instead of the
base regions 126. This suppression of P-base reach-through enables
a reduction in the channel length of the device 10. Moreover, the
preferred retrograded doping profile in the transition region 130
enables complete or full depletion of the transition region 130
when the power device 10 is blocking maximum reverse voltages and
the drift region mesa 102b is supporting the reverse voltage.
[0043] Full depletion of the transition region 130 may also occur
during forward on-state conduction. In particular, full depletion
during forward operation preferably occurs before the voltage in
the channel (at the end adjacent the transition region 130) equals
the gate voltage on the insulated gate electrode 118. As used
herein, the reference to the transition region being "fully
depleted" should be interpreted to mean that the transition region
is at least sufficiently depleted to provide a JFET-style pinch-off
of a forward on-state current path that extends vertically through
the transition region 130. To achieve full depletion, the
relatively highly doped shielding regions 128 of second
conductivity (e.g., P+) are provided in close proximity and on
opposite sides of the transition region 130. As the voltage in the
channel increases during forward on-state conduction, the
transition region 130 becomes more and more depleted until a
JFET-style pinch-off occurs within the transition region 130. This
JFET-style pinch-off in the transition region 130 can be designed
to occur before the voltage at the drain-side of the channel
(V.sub.cd) equals the gate voltage (i.e.,
V.sub.cd.ltoreq.V.sub.gs). For example, the MOSFET may be designed
so that the transition region 130 becomes fully depleted when
0.1.ltoreq.V.sub.cd<0.5 Volts and V.sub.gs=4.0 Volts. Use of the
preferred transition region 130 enables the channel of the field
effect transistor within the power device 10 to operate in a linear
mode of operation during forward on-state conduction while a drain
region of the transistor simultaneously operates in a velocity
saturation mode of operation. Other power devices that exhibit
similar modes of operation are described in U.S. application Ser.
No. 09/602,414, filed Jun. 23, 2000, entitled "MOSFET Devices
Having Linear Transfer Characteristics When Operating in Velocity
Saturation Mode and Methods of Forming and Operating Same",
assigned to the present assignee, the disclosure of which is hereby
incorporated herein by reference.
[0044] Simulations of the device of FIG. 1 were also performed for
a unit cell having a trench depth of 4.7 microns, a trench width of
1.1 microns and a mesa width of 1.9 microns. A sidewall oxide
thickness of 3000 .ANG. was also used. The drift region had a
thickness of 6 microns and the uniformly doped upper portion of the
drift region had a thickness of 0.5 microns. The concentration of
first conductivity type dopants in the uniformly doped upper
portion of the drift region was set at 1.times.10.sup.16 cm.sup.-3
and the drain region had a phosphorus doping concentration of
5.times.10.sup.9 cm.sup.-3. The gate oxide thickness was set at 250
.ANG. and a total gate length (across the mesa) of 0.9 microns was
used. The widths of the shielding, base and source regions
(relative to the sidewalls) were 0.65, 0.65 and 0.45 microns,
respectively, and the channel length was 0.2 microns. The width of
the transition region (at the depth of the peak concentration in
the transition region) was set at 0.6 microns. The depths of the
source, base, shielding and transition regions and their peak
dopant concentrations can be obtained from the following Table 1
and FIGS. 8A-8B, where Peak N.sub.d and Peak N.sub.a are the peak
donor and acceptor concentrations.
1TABLE 1 Implant Energy Implant Dose Region (KeV) (cm.sup.-2)
Dopant Peak N.sub.d,a cm.sup.-3 N+ source 40-50 1-5 .times.
10.sup.15 P, As 1 .times. 10.sup.20 P-base 40-50 1-5 .times.
10.sup.13 B 2 .times. 10.sup.18 (surface); 4 .times. 10.sup.17
(channel max) P+ shield 100 1-5 .times. 10.sup.14 B 5 .times.
10.sup.18 N-transition 200 1-10 .times. 10.sup.12 P 1.3 .times.
10.sup.17
[0045] Based on the above characteristics and including variations
of the peak dopant concentration in the transition region
(Peak.sub.TR) and width of the transition region (W.sub.TR), the
following simulated breakdown voltages of Tables 2 and 3 were
obtained. Medici.TM. simulation software, distributed by Avant!.TM.
Corporation, was used to perform the device simulations.
2 TABLE 2 W.sub.TR(.mu.m) (Peak.sub.TR)(cm.sup.-3) BV (Volts)
Q(#/cm.sup.2) 0.5 0.4 .times. 10.sup.17 80 0.2 .times. 10.sup.13
0.5 0.7 .times. 10.sup.17 80 0.35 .times. 10.sup.13 0.5 1.2 .times.
10.sup.17 79 0.6 .times. 10.sup.13 0.5 1.3 .times. 10.sup.17 78
0.65 .times. 10.sup.13 0.5 1.4 .times. 10.sup.17 62 0.7 .times.
10.sup.13 0.5 1.6 .times. 10.sup.17 35 0.8 .times. 10.sup.13 0.5
1.9 .times. 10.sup.17 20 0.95 .times. 10.sup.13 0.5 2.5 .times.
10.sup.17 9 1.25 .times. 10.sup.13
[0046]
3 TABLE 3 W.sub.TR(.mu.m) (Peak.sub.TR)(cm.sup.-3) BV (Volts)
Q(#/cm.sup.2) 0.3 1.4 .times. 10.sup.17 80 0.42 .times. 10.sup.13
0.4 1.4 .times. 10.sup.17 80 0.56 .times. 10.sup.13 0.5 1.4 .times.
10.sup.17 62 0.7 .times. 10.sup.13 0.6 1.4 .times. 10.sup.17 37
0.84 .times. 10.sup.13 0.7 1.4 .times. 10.sup.17 24 0.98 .times.
10.sup.13
[0047] As determined by the inventor herein and illustrated by the
simulation results of Tables 2 and 3, power devices having high
breakdown voltages can be provided by establishing a product of the
peak first conductivity type dopant concentration in the transition
region (at the first depth) and a width of the transition region at
the first depth in a preferred range that is between about
1.times.10.sup.12 cm.sup.-2 and about 7.times.10.sup.12 cm.sup.-2
and, more preferably, in a range between about 3.5.times.10.sup.12
cm.sup.-2 and about 6.5.times.10.sup.12 cm.sup.-2. This narrower
more preferred range can result in devices having high breakdown
voltage and excellent on-state resistance characteristics.
Depending on unit cell design within an integrated multi-celled
device, the product of the peak first conductivity type dopant
concentration in the transition region and a width of the
non-rectifying junction between the transition region and the drift
region may also be in a range between about 1.times.10.sup.12
cm.sup.-2 and about 7.times.10.sup.12 cm.sup.-2. A product of the
peak first conductivity type dopant concentration in the transition
region, a width of the transition region at the first depth and a
width of the mesa may also be set at a level less than about
2.times.10.sup.15 cm.sup.-1. To achieve sufficient charge coupling
in the drift region mesa, a product of the drift region mesa width
and quantity of first conductivity type charge in a portion of the
drift region mesa extending below the transition region is
preferably in a range between about 2.times.10.sup.9 cm.sup.-1 and
about 2.times.10.sup.10 cm.sup.-1.
[0048] Referring now to FIGS. 2-7, additional embodiments of power
devices according to the present invention include the multi-celled
power device 20 of FIG. 2. This device 20 is similar to the device
10 of FIG. 1, however, antiparallel diodes are provided by Schottky
rectifying contacts that extend between the source electrode 138
and the drift region extensions 102c. The power device 30 of FIG. 3
is also similar to the power device 20 of FIG. 2, however, a
plurality of dummy unit cells are provided in dummy drift region
mesas 102d. Dummy shielding regions (shown as P+) and dummy base
regions (shown as P) are also provided in the dummy drift region
mesas 102d. As illustrated, the dummy base regions electrically
contact the source electrode 138. The dummy base regions and dummy
shielding region can be formed at the same time as the base and
shielding regions within the active unit cells. Depending on the
thermal ratings of a multi-celled power device, one or more dummy
unit cells may be provided to facilitate heat removal from each
active unit cell.
[0049] The multi-celled power device 40 of FIG. 4 is similar to the
device 30 of FIG. 3, however, the dummy drift region mesas 102d
(which may not contribute to forward on-state conduction, but
preferably support equivalent reverse breakdown voltages) are
capacitively coupled through a field plate insulating layer 125 to
the source electrode 138. In contrast to the widths of the dummy
drift region mesas 102d in FIG. 3, which should be equal to the
widths of the drift region mesas 102b of the active unit cells, the
widths of the dummy drift region mesas 102d in FIG. 4 need not be
equal. The power device 50 of FIG. 5 is similar to the device 20 of
FIG. 2, however, the electrically insulating layers 106 on the
sidewalls of the trenches have been recessed to enable direct
sidewall contact between the source electrode 138 and the source,
base and shielding regions within the active unit cells. The
establishment of this direct sidewall contact increases the active
area of the device 50 by reducing and preferably eliminating the
requirement that the source regions be periodically interrupted in
a third dimension (not shown) in order to provide direct contacts
to the base regions.
[0050] The power device 60 of FIG. 6 illustrates a relatively wide
active drift region mesa 102b with a centrally located base region
126a and shielding region 128a. The transition region 130a may have
the same characteristics as described above with respect to the
transition regions 130 within the power devices 10-50 of FIGS. 1-5.
The power device 70 of FIG. 7 is similar to the device 60 of FIG.
6, however, the centrally located base region 126a and shielding
region 128a of FIG. 6 have been separated by a centrally located
trench 104. The power device 10' of FIG. 10 is similar to the power
device 10 of FIG. 1, however, the insulated gate electrode 118 on
each active mesa 102b has been replaced by a pair of shorter
insulated gate electrodes 118a and 118b. For a mesa having a width
of 2.6 microns, the gate electrodes 118a and 118b may have a length
of 0.3 microns, for example. The use of a pair of shorter gate
electrodes instead of a single continuous gate electrode that
extends opposite the entire width of the transition region 130 can
reduce the gate-to-drain capacitance C.sub.gd of the device 10' and
increase high frequency power gain. The source electrode 138 also
extends into the space between the gate electrodes 118a and 118b,
as illustrated by FIG. 10. The portion of the source electrode 138
that extends into the space between the gate electrodes 118a and
118b may have a length of about 0.2 microns. The insulator that
extends directly between the source electrode 138 and the
transition region 130 may be a gate oxide and may have a thickness
in a range between about 100 .ANG. and about 1000 .ANG.. The
sidewall insulator that extends between the sidewalls of the gate
electrodes 118a and 118b and the source electrode 138 may also have
a thickness in a range between about 1000 .ANG. and about 5000
.ANG., however, other sidewall insulator thicknesses may also be
used. According to another aspect of this embodiment, the portion
of the source electrode 138 that extends into the space between the
gate electrodes 118a and 118b may be formed by patterning a
conductive layer (e.g., polysilicon) used to form the gate
electrode 118a and 118b. In particular, a third "dummy" gate
electrode 118c may be patterned that extends opposite the
transition region 130. An illustration of a vertical power device
10" that utilizes a dummy gate electrode 118c is provided by FIG.
11. The device 10" of FIG. 11 may otherwise be similar to the
device 10' of FIG. 10. Electrical contact between this third dummy
gate electrode 118c and the source electrode 138 may be made using
conventional back-end processing techniques.
[0051] Preferred methods of forming the vertical power device of
FIG. 5 with a 65 Volt product rating will now be described. As
illustrated by FIG. 9A, these methods may include the step of
epitaxially growing a drift region 202 of first conductivity type
(shown as N) on a highly doped silicon substrate 200 (e.g., N+
substrate). This highly doped substrate 200 may have a first
conductivity type doping concentration therein of greater than
about 1.times.10.sup.19 cm.sup.-3 and may have an initial thickness
T.sub.s of about 500 microns. The epitaxial growth step is
preferably performed while simultaneously doping the drift region
202 with first conductivity type dopants in a graded manner. To
achieve a 65 Volt product rating, a vertical power device having an
actual blocking voltage of 75 Volts may be required. To achieve
this blocking voltage, trenches having a depth in a range between
about 4.5-5 microns will typically be required. To support trenches
with this depth, a graded doped drift region 202 having a thickness
T.sub.d of about 6 microns may be required. Preferably, a drift
region 202 having a thickness of 6 microns will include a uniformly
doped region at an upper surface thereof. This uniformly doped
region may have a thickness in a range between about 0.5 and 1.0
microns and may be doped at a uniform level of about
1.times.10.sup.16 cm.sup.-3. The graded-doped portion of the drift
region 202 may have a thickness of 5.0-5.5 microns and may be
graded from a doping level of 1.times.10.sup.16 cm.sup.-3 at a
depth of 0.5 or 1.0 microns, for example, to a higher level of at
least about 5.times.10.sup.16 cm.sup.-3 at a depth of 6.0 microns.
The drift region 202 may form an abrupt non-rectifying junction
with the substrate 200.
[0052] Conventional selective etching techniques may then be
performed using a first etching mask (not shown) to define a
plurality of parallel stripe-shaped trenches 204 in the drift
region 202. Trenches 204 having other shapes may also be used. For
example, each pair of adjacent trenches 204 may represent opposing
sides of a respective ring-shaped trench. These trenches 204 may
have a depth D.sub.t of 5 microns, for example. Adjacent trenches
204 define drift region mesas 202b therebetween, with the width
W.sub.m of each mesa 202b controlled by the spacing between the
adjacent trenches 204. As illustrated by FIG. 9B, a thin thermal
oxide layer 206 may then be grown at a low temperature on the
sidewalls and bottoms of the trenches 204 and on an upper surface
202a of each of the mesas 202b. For example, this thin oxide layer
206 may be grown for a duration of 30 minutes at a temperature of
900.degree. C. in a wet O.sub.2 ambient. This thermal growth step
may result in an oxide layer 206 having a thickness of about 700
.ANG.. This thin oxide layer 206 can be used to improve the
interface between the sidewalls of the trenches 204 and
subsequently formed regions within the trenches 204, by removing
etching related defects. The thermal budget associated with this
thermal oxide growth step should be insufficient to significantly
alter the graded doping profile in the drift region 202, however,
the doping concentration at the surface 202a of each mesa 202b may
increase as a result of dopant segregation. A thick conformal oxide
layer 208 may then be deposited at a low temperature to produce an
electrically insulating spacer on the sidewalls and bottoms of the
trenches 204. For a 65 Volt product rating, the total oxide
thickness (thermal oxide plus deposited oxide) may be 3000
.ANG..
[0053] Referring now to FIG. 9C, a conformal polysilicon layer 210
may then be deposited using a low temperature CVD process. The
thickness of this layer should be sufficient to fill the trenches
204. The polysilicon layer 210 may be in-situ doped (e.g., with
phosphorus) so that a low sheet resistance of 10 ohms/square is
achieved. As illustrated by FIG. 9D, the deposited polysilicon
layer 210 may then be etched back using conventional etching
techniques. The duration of this etching step may be sufficiently
long that the polysilicon regions 210a within each trench 204 are
planar with the upper surfaces 202a of the mesas 202b. This etch
back step may be performed without an etching mask. Referring now
to FIG. 9E, another etching step may then be performed with a
second mask (not shown) in order to selectively remove the oxide
over the mesas 202b, but preserve the oxide within field oxide
regions (not shown) that may be located around a periphery of the
drift region 202. This second mask may comprise a photoresist layer
that has been patterned to define an etching window that is within
a border of an outside trench (not shown) that surrounds an
integrated power device containing a plurality of the illustrated
power devices as unit cells.
[0054] As illustrated by FIG. 9F, a thin pad oxide layer 212 is
then grown as a screening oxide over the exposed upper surfaces of
the mesas 202b. This thin pad oxide layer 212 may have a thickness
of about 250 .ANG.. This thin pad oxide layer 212 may be grown for
a duration of 10 minutes at a temperature of 900.degree. C. in a
wet O.sub.2 ambient. Transition region dopants 214 of first
conductivity type may then be implanted using a blanket implant
step. In particular, transition regions having vertically
retrograded doping profiles therein relative to the upper surface
202a may be formed by implanting phosphorus dopants at an energy
level of 200 keV and at a preferred dose level of 5.times.10.sup.12
cm.sup.-2. This energy level of 200 keV and dose level of
5.times.10.sup.12 cm.sup.-2 may result in an N-type transition
region having a peak implant depth (N.sub.PID) of about 0.25-0.3
microns and a peak dopant concentration of about
1.3.times.10.sup.17 cm.sup.-3. As illustrated on the left side of
FIG. 8A, the N-type dopant concentration in the N-type transition
may be set to a value of less than about 2.times.10.sup.16
cm.sup.-3 at the upper surface 202a.
[0055] Referring now to FIG. 9G, the pad oxide layer 212 is then
removed and in its place a gate oxide layer 216 having thickness of
about 500 .ANG. may be formed. This gate oxide layer 216 may be
provided by performing a thermal oxidation step in a wet O.sub.2
ambient for a duration of 20 minutes and at a temperature of
900.degree. C. A blanket polysilicon layer 218 is then deposited
and patterned using a photoresist mask layer 220 (third mask), to
define a plurality of gate electrodes 218. A sequence of
self-aligned implant steps are then performed. In particular,
highly doped self-aligned shielding regions of second conductivity
may be formed in the transition region by implanting shielding
region dopants 222 (e.g., boron) at an energy level of 100 keV and
at a dose level of 1.times.10.sup.14 cm.sup.-2. After thermal
treatment, these energy and dose levels may ultimately result in a
shielding region having a peak boron concentration of about
5.times.10.sup.18 cm.sup.-3 at a depth of about 0.3 microns,
assuming a characteristic diffusion length of about 0.1 microns.
These shielding region dopants 222 are preferably implanted using
both the gate electrodes 218 and the mask layer 220 as an implant
mask. Self-aligned base regions of second conductivity type may
also be formed in the shielding regions by implanting base region
dopants 224 (e.g., boron) at an energy level of 50 keV and at a
dose level of 3.times.10.sup.13 cm.sup.-2. The locations of peak
concentrations of the shielding region dopants 222 and base region
dopants 224 within the mesas 202b, are represented by the reference
characters "+". The peak concentration of the shielding region
dopants may equal 3.times.10.sup.18 cm.sup.-3, at a depth of
0.25-0.3 microns. This depth preferably matches the depth of the
peak of the transition region dopants.
[0056] Referring now to FIG. 9H, the mask layer 220 may be removed
and then a drive-in step may be performed at a temperature of about
1000.degree. C. and for a duration of about 60 minutes to define
self-aligned base regions 226 (shown as P), self-aligned shielding
regions 228 (shown as P+) and the transition regions 230 (shown as
N). This drive-in step, which causes lateral and downward diffusion
of the implanted base, shielding and transition region dopants, may
provide the highest thermal cycle in the herein described method.
If the uniform and graded doping profile in the drift region is
significantly altered during this step, then the initial drift
region doping profile may be adjusted to account for the thermal
cycle associated with the drive-in step. As illustrated by FIG. 9H,
the implant energies and duration and temperature of the drive-in
step may be chosen so that the depth of the P--N junction between
the P+ shielding region 228 and the drift region 202 is about equal
to the depth of the non-rectifying junction between the transition
region 230 and the drift region 202, however, unequal depths may
also be used. The depth of the P--N junction may equal 0.7
microns.
[0057] Referring now to FIG. 91, source region dopants 232 of first
conductivity type are then implanted into the base regions 226,
using the gate electrodes 218 as an implant mask. The source region
dopants 232 may be implanted at an energy level of 40 keV and at a
dose level of 2.times.10.sup.14 cm.sup.-2. As illustrated by FIG.
9J, the implanted source region dopants (shown by reference
character "-") may then be driven-in at a temperature of
900.degree. C. and for a duration of 10 minutes, to define N+
source regions 233. This implant step may be performed using the
gate electrodes 218 and fourth photoresist mask (not shown) as an
implant mask. The fourth photoresist mask may be patterned to
define the locations of shorts to the P-base region in a third
dimension relative to the illustrated cross-section (not shown).
Conventional insulator deposition, sidewall spacer formation and
patterning steps may then be performed to define a plurality of
insulated gate electrodes 234. These steps may also be performed to
define contact windows to the source regions, the P-base regions,
the polysilicon in the trenches and the gate electrodes. The
insulating regions 206/208 lining upper sidewalls of the trenches
may also be selectively etched back to expose sidewalls of the
source, base and shielding regions. The presence of this etch back
step may eliminate the need to define shorts to the P-base region,
using the fourth photoresist mask, and therefore may result in an
increase in the forward on-state conduction area for a given
lateral unit cell dimension. As illustrated by FIG. 9K,
conventional front side metallization deposition and patterning
steps may also be performed to define a source contact 238 and gate
contact (not shown). As illustrated, the source contact 238 extends
along the upper sidewalls of the trenches 204 and contacts the
exposed portions of the source, base and shielding regions. The
backside of the substrate 200 may also be thinned and then
conventional backside metallization steps may be performed to
define a drain contact 236.
[0058] In the drawings and specification, there have been disclosed
typical preferred embodiments of the invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purposes of limitation, the
scope of the invention being set forth in the following claims.
* * * * *