U.S. patent application number 10/439154 was filed with the patent office on 2004-11-18 for densifying a relatively porous material.
Invention is credited to Johnston, Steven W., O'Brien, Kevin P..
Application Number | 20040229452 10/439154 |
Document ID | / |
Family ID | 33417739 |
Filed Date | 2004-11-18 |
United States Patent
Application |
20040229452 |
Kind Code |
A1 |
Johnston, Steven W. ; et
al. |
November 18, 2004 |
Densifying a relatively porous material
Abstract
An interlayer dielectric may be exposed to a gas cluster ion
beam to densify an upper layer of the interlayer dielectric. As a
result, the upper layer of the interlayer dielectric may be
densified without separate deposition steps and without the need
for etch stops that may adversely affect the capacitance of the
overall structure.
Inventors: |
Johnston, Steven W.;
(Portland, OR) ; O'Brien, Kevin P.; (Portland,
OR) |
Correspondence
Address: |
Timothy N. Trop
TROP, PRUNER & HU, P.C.
STE 100
8554 KATY FWY
HOUSTON
TX
77024-1841
US
|
Family ID: |
33417739 |
Appl. No.: |
10/439154 |
Filed: |
May 15, 2003 |
Current U.S.
Class: |
438/622 ;
257/E21.038; 257/E21.273; 257/E21.277; 257/E21.576;
257/E21.581 |
Current CPC
Class: |
H01L 21/76825 20130101;
H01L 21/0337 20130101; H01L 21/76832 20130101; H01L 21/76807
20130101; H01L 21/7682 20130101; H01L 21/02126 20130101; H01L
21/02203 20130101; H01L 21/3105 20130101; H01L 21/02351 20130101;
H01L 21/76829 20130101 |
Class at
Publication: |
438/622 |
International
Class: |
H01L 021/31; H01L
021/4763; H01L 021/469 |
Claims
What is claimed is:
1. A method comprising: forming a porous layer; and exposing said
porous layer to a gas clustered ion beam to densify said porous
layer.
2. The method of claim 1 wherein forming a porous layer includes
forming an interlayer dielectric.
3. The method of claim 2 including forming a carbon doped oxide
interlayer dielectric.
4. The method of claim 1 including forming metallic features on
said porous layer and exposing said metallic features and said
porous layer to a clustered ion beam.
5. The method of claim 1 including densifying said porous layer to
form a hard mask.
6. The method of claim 5 including using said hard mask to enable
an unlanded via integration scheme.
7. The method of claim 5 including using said hard mask in a
damascene or dual damascene process.
8. The method of claim 1 including forming said porous layer over a
sacrificial layer.
9. The method of claim 8 including removing said sacrificial layer
through said porous layer and after removing said sacrificial layer
through said porous layer exposing said porous layer to said
clustered ion beam to form said hard mask.
10. The method of claim 1 including densifying only a surface
region of said porous layer while the remainder of said porous
layer below said surface region remains undensified.
11. The method of claim 10 including controlling the thickness of a
densified region to approximately 20 Angstroms or less.
12-19. (Canceled).
20. A method comprising: forming a porous layer over a sacrificial
layer; exhausting at least a portion of said sacrificial layer
through said overlying porous layer; and densifying the porous
layer.
21. The method of claim 20 including densifying the porous layer
using a clustered ion beam.
22. The method of claim 21 including forming a non-porous region in
said porous layer by densifying.
Description
BACKGROUND
[0001] This invention relates generally to processes for
manufacturing semiconductor integrated circuits.
[0002] In a variety of different processes, it may be desirable to
form what is called a hard mask. A hard mask is a mask that may be
utilized as an etching mask for subsequent process steps. For
example, in the damascene process, a hard mask may be formed that
prevents etched vias from extending through the hard mask. The hard
mask may be utilized to enable an unlanded via integration
scheme.
[0003] One problem with hard masks is that they may require an
extra processing step. Basically, a separate hard mask may be
deposited on top of a previously deposited material, such as a low
dielectric constant film. The use of such hard mask may increase
etch complexity due to the nature of the stack, including the
resist, hard mask and underlying film. In addition, moisture may
infiltrate through the hard mask. The infiltrated moisture, for
example, may increase the capacitance contributed by a low
dielectric constant film.
[0004] Thus, there is a need for better ways to form a
hardmask.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is an enlarged, cross-sectional view of one
embodiment of the present invention in the course of
manufacture;
[0006] FIG. 2 is an enlarged, cross-sectional view of the
embodiment as shown in FIG. 1 at a subsequent stage of
manufacture;
[0007] FIG. 3 is an enlarged, cross-sectional view of the
embodiment as shown in FIG. 1 at a subsequent stage of manufacture
in accordance with one embodiment of the present invention;
[0008] FIG. 4 is an enlarged, cross-sectional view of the
embodiment shown in FIG. 1 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention;
[0009] FIG. 5 is an enlarged, cross-sectional view of another
embodiment of the present invention;
[0010] FIG. 6 is an enlarged, cross-sectional view of the
embodiment shown in FIG. 5 at a subsequent stage in accordance with
one embodiment of the present invention;
[0011] FIG. 7 is an enlarged, cross-sectional view of the
embodiment shown in FIG. 5 at a subsequent stage in accordance with
one embodiment of the present invention; and
[0012] FIG. 8 is a schematic depiction of an apparatus for forming
gas cluster ions.
DETAILED DESCRIPTION
[0013] Referring to FIG. 1, a substrate 12 may be defined with the
appropriate active and passive components, such as the metal
elements 14 and the dielectric layer 16. A masking layer 18 may
then be deposited. A dielectric film 20 may be deposited over the
layer 18. The dielectric film 20 may be followed by a second
interlayer dielectric film 26 in one embodiment.
[0014] Lithography, etching, and cleaning may be utilized to form
trenches or vias through the dielectric films 26 and 20 using a
damascene or dual damascene approach. Degassing, cleaning, barrier
deposition, and seed deposition of the dielectric material may
follow as desired. The resulting trenches may be filled with
conductive material 22 and 24 using electroplating or any other
fill technology.
[0015] The resulting wafer may be planarized down to the top of the
dielectric film 26 by chemical mechanical polishing (CMP) or other
planarization technology. If desired, deposition of a thin copper
capping film 28 may be done using chemical vapor deposition, atomic
layer deposition, or electroless methods to create a thin,
continuous capping film.
[0016] The film 26 may be modified by the addition of carbon to
form carbon-doped oxide (CDO) film. Other films 26 may also be used
including porous silicon, spin-on glass, polymers, and other low
dielectric constant materials. Then, as shown in FIG. 2, the
exposed film 26 may be bombarded with a gas clustered ion beam. As
a result of the mass and energy of the clustered ions used to
bombard the film 26, the upper layer 30 of the film 26 may be
densified. The capping film 28 is not substantially affected by the
densification. In effect, the bombarding clustered ions actually
compress the atomic structure of the exposed film 26. In one
embodiment, a relatively porous material can be converted to a
substantially non-porous hard mask.
[0017] Thereafter, another low dielectric constant interlayer
dielectric layer 40 may be deposited in accordance with the
damascene or dual damascene approach as shown in FIG. 3. The
masking layer 42 may be formed and patterned to the desired trench
characteristics as shown in FIG. 4. The masking layer 42 may then
be used as a mask to pattern the layer 40 to form additional
trenches for forming an additional layer of metal interconnects.
Again, the metal interconnects may be arranged in an unlanded via
configuration to repeat the sequence described in connection with
FIGS. 1 and 2. In one application, the etched vias 44 may be filled
with a sacrificial light activated material. The resulting
structure may be covered by another masking layer, trenches may be
etched, and then the sacrificial light activated material is etched
to leave behind a trench and via that are filled with the material
22, 24. The techniques described herein can also be used to form
embedded etch stops and to densify the bottom of trenches. Any
surface layer may be converted in a directional fashion as
described herein.
[0018] In another embodiment of the present invention, a similar
process sequence to that described above may be utilized, except
that a previously deposited, porous hard mask may be densified.
Subsequent steps can then be built up to form multi-levels of vias
and interconnects, all using the densified hard mask procedure
described herein. As another example, a non-hermetic etch stop may
have its top surface densified while the bulk of a silicon carbide
etch stop is not altered. As a result, a low dielectric constant
may be preserved for the material.
[0019] In one embodiment, a porous layer 56 may be formed over a
sacrificial material 54 in a layer 52 over a substrate 50, as shown
in FIG. 5. The porosity of the layer 56 enables the sacrificial
material 54 to be evaporated and exhausted through the porous layer
56 in one embodiment, to create a void 58, shown in FIG. 6. Then,
the porous layer 56 may be densified to form a substantially
non-porous hard mask 60, sealing the void 58 as shown in FIG.
7.
[0020] Referring to FIG. 8, a typical gas clustered ion beam is
illustrated. The desired gas is provided to a nozzle 32 and ejected
by an ionizer 34 and accelerated by an accelerator 36. The
accelerated ion clusters then impact the target structure causing
densification. The clustered ions may include oxygen ions in one
embodiment. As a result, an unlanded via integration scheme may be
enabled, as indicated by 22.
[0021] The modified structure may result in a hard mask with lower
interconnect capacitance since no silicon carbide etch stop layer
may be utilized, a simpler etch process for the next metal layer
since no separate hard mask is used on top of the next interlayer
dielectric layer to etch through to form a via trench, a naturally
self-aligned hard mask material, and a smoother copper or copper
capped surface, which may have advantages in some embodiments.
[0022] Another advantage of using the gas cluster ions is that the
total energy of the gas cluster can be high while the energy per
atom is quite low. Thus, subsurface damage is reduced and is
controllable to less than 20 Angstroms at low cluster energies. The
gas cluster ion also tends to smooth the exposed metal surfaces,
resulting in a smoother overlying via barrier interface.
[0023] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *