U.S. patent application number 10/863979 was filed with the patent office on 2004-11-04 for apparatus and method for molding a semiconductor die package with enhanced thermal conductivity.
Invention is credited to Bolken, Todd O., Hall, Frank L..
Application Number | 20040217389 10/863979 |
Document ID | / |
Family ID | 29548926 |
Filed Date | 2004-11-04 |
United States Patent
Application |
20040217389 |
Kind Code |
A1 |
Hall, Frank L. ; et
al. |
November 4, 2004 |
Apparatus and method for molding a semiconductor die package with
enhanced thermal conductivity
Abstract
A method and apparatus for assembling and packaging
semiconductor die assemblies utilizes a coating element such as a
wafer back side laminate formed on a back side of a semiconductor
die is disclosed. The coating element may be formed from a somewhat
compressible and, optionally, resilient material, which seals
against a surface of a mold cavity while the semiconductor die
assembly is being encapsulated. In this manner, the coating element
prevents encapsulant material from covering at least a portion of
the back side of the semiconductor die to prevent encapsulant
flashing over the back side and thus improve heat dissipation
characteristics of the packaged semiconductor die during
operation.
Inventors: |
Hall, Frank L.; (Boise,
ID) ; Bolken, Todd O.; (Star, ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
29548926 |
Appl. No.: |
10/863979 |
Filed: |
June 9, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10863979 |
Jun 9, 2004 |
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10154640 |
May 24, 2002 |
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Current U.S.
Class: |
257/222 ;
257/E23.004; 257/E23.039; 257/E23.069; 257/E23.124;
257/E23.126 |
Current CPC
Class: |
H01L 2224/45099
20130101; H01L 2224/48465 20130101; H01L 2224/48465 20130101; H01L
2224/85399 20130101; H01L 2924/181 20130101; H01L 2224/16 20130101;
H01L 2224/73215 20130101; H01L 2224/48247 20130101; H01L 2224/48465
20130101; H01L 2924/00012 20130101; H01L 2224/48091 20130101; H01L
2924/207 20130101; H01L 2224/48091 20130101; H01L 2924/00012
20130101; H01L 2224/32225 20130101; H01L 2924/01087 20130101; H01L
2224/45015 20130101; H01L 2924/00 20130101; H01L 2924/00012
20130101; H01L 2924/00 20130101; H01L 2224/4824 20130101; H01L
2224/48465 20130101; H01L 2224/48465 20130101; H01L 23/3128
20130101; H01L 2224/4824 20130101; H01L 2224/4826 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 23/3135
20130101; H01L 24/48 20130101; H01L 2224/73215 20130101; H01L
2924/181 20130101; H01L 2224/48465 20130101; H01L 23/49816
20130101; H01L 2224/73253 20130101; H01L 2924/12042 20130101; H01L
2224/73215 20130101; H01L 2924/01013 20130101; H01L 21/565
20130101; H01L 23/4951 20130101; H01L 2224/05599 20130101; H01L
2224/85399 20130101; H01L 2924/15311 20130101; H01L 2924/10253
20130101; H01L 2224/48465 20130101; H01L 2924/00014 20130101; H01L
2924/10253 20130101; H01L 23/13 20130101; H01L 2224/16225 20130101;
H01L 2224/32014 20130101; H01L 2224/05599 20130101; H01L 2224/4824
20130101; H01L 2924/12042 20130101; H01L 23/3107 20130101; H01L
2924/09701 20130101; H01L 2924/15311 20130101; H01L 2224/48091
20130101; H01L 2224/48247 20130101; H01L 2224/48091 20130101; H01L
2224/48465 20130101; H01L 2924/00 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 2924/00012 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/32225 20130101;
H01L 2924/00014 20130101; H01L 2224/45099 20130101; H01L 2224/4824
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2224/4826 20130101; H01L 2924/00014 20130101; H01L 2224/32225
20130101; H01L 2224/4824 20130101; H01L 2224/4824 20130101 |
Class at
Publication: |
257/222 |
International
Class: |
H01L 027/148 |
Claims
1. A semiconductor device assembly, comprising: at least one
semiconductor die; a carrier positioned adjacent to an active
surface of the at least one semiconductor die and including at
least a portion oriented substantially parallel thereto; at least
one intermediate conductive element electrically connecting at
least one bond pad of the at least one semiconductor die and a
corresponding contact of the carrier; an encapsulant covering at
least an outer periphery of the at least one semiconductor die; and
a compressible coating element on at least a portion of a back side
of the at least one semiconductor die, at least a substantial
portion of the compressible coating element being exposed.
2. The semiconductor device assembly of claim 1, wherein the
compressible coating element is sized and shaped in substantial
conformance to a size and shape of the back side of the at least
one semiconductor die.
3. The semiconductor device assembly of claim 1, wherein the
compressible coating element has an outer surface substantially
coplanar with an outer surface of the encapsulant.
4. The semiconductor device assembly of claim 1, wherein an outer
surface of the compressible coating element projects slightly
beyond a surrounding outer surface of the encapsulant.
5. The semiconductor device assembly of claim 1, wherein the
compressible coating element substantially covers the back side of
the at least one semiconductor die.
6. The semiconductor device assembly of claim 1, wherein the
compressible coating element includes an outer boundary lying
substantially along a periphery of the back side of the at least
one semiconductor die.
7. The semiconductor device assembly of claim 6, wherein the
compressible coating element is configured as a frame.
8. The semiconductor device assembly of claim 6, wherein the
compressible coating element is configured so that a nonperipheral
portion of the back side of the at least one semiconductor die is
exposed.
9. The semiconductor device assembly of claim 6, wherein the
compressible coating element is configured so that a central
portion of the back side is exposed.
10. The semiconductor device assembly of claim 1, wherein the
compressible coating element comprises a compliant or resilient
material.
11. The semiconductor device assembly of claim 1, wherein the
compressible coating element comprises a preformed film.
12. The semiconductor device assembly of claim 11, wherein the
preformed film is adhered to the at least a portion of the back
side with an adhesive.
13. The semiconductor device assembly of claim 1, wherein the
compressible coating element is formed on the at least a portion of
the back side in a nonsolid state and subsequently at least
substantially solidified.
14. The semiconductor device assembly of claim 1, wherein the
compressible coating element is formulated to exhibit a coefficient
of thermal expansion similar to a coefficient of thermal expansion
of the at least one semiconductor die.
15. The semiconductor device assembly of claim 14, wherein the
compressible coating element comprises a preformed film filled with
silicon particles.
16. The semiconductor device assembly of claim 14, wherein the
compressible coating element is formed on the at least a portion of
the back side in a nonsolid mass filled with silicon particles and
subsequently at least substantially solidified.
17. The semiconductor device assembly of claim 1, wherein the
encapsulant substantially encapsulates the at least one
intermediate conductive element.
18. The semiconductor device assembly of claim 1, wherein the
encapsulant covers at least a portion of the carrier.
19. The semiconductor device assembly of claim 1, wherein the
carrier includes at least one aperture through which the at least
one bond pad of the at least one semiconductor die is exposed and
the at least one intermediate conductive element extends through
the at least one aperture between the at least one bond bad and the
corresponding contact of the carrier.
20. The semiconductor device assembly of claim 1, wherein the
corresponding contact of the carrier is on a surface of the carrier
facing the active surface of the at least one semiconductor die and
in alignment therewith and the carrier is spaced from the at least
one semiconductor die by the at least one intermediate conductive
element.
21. The semiconductor device assembly of claim 20, wherein the at
least one bond pad comprises an array of bond pads.
22. The semiconductor device assembly of claim 21, wherein the at
least one intermediate conductive element comprises a conductive
bump, a conductive pillar, or a conductive pin.
23. The semiconductor device assembly of claim 20, wherein the
encapsulant extends between the carrier and the at least one
semiconductor die and encapsulates the at least one intermediate
conductive element therebetween.
24. The semiconductor device assembly of claim 1, wherein the
carrier comprises a lead frame and the corresponding contact
comprises a lead finger.
25. A mold assembly configured for use in packaging a semiconductor
die on a carrier, the mold assembly comprising: at least first and
second mold sections to be assembled with one another; at least one
cavity segment formed in each of the first and second mold
sections, the at least one cavity segment in each of the first and
second mold sections being sized and configured, when in alignment,
to define at least one cavity configured to receive a semiconductor
die on a carrier; a portion of an inner surface of the at least one
cavity segment of at least one of the first and second mold
sections comprising a surface finish of enhanced smoothness
relative to at least one other portion of the inner surface.
26. The mold assembly of claim 25, wherein the portion of the inner
surface is substantially centrally located in the at least one
cavity segment.
27. The mold assembly of claim 25, wherein the portion of the inner
surface is positioned on the inner surface to correspond with a
location of a back side of the semiconductor die on the carrier
when received in the at least one cavity segment.
28. The mold assembly of claim 27, wherein the portion of the inner
surface has an outer periphery substantially coincident with the
back side of the semiconductor die.
29. The mold assembly of claim 25, wherein the surface finish of
enhanced smoothness of the portion of the inner surface comprises a
ground finish, a lapped finish or a polished finish.
30. The mold assembly of claim 25, wherein the surface finish of
enhanced smoothness of the portion of the inner surface is shaped
as a frame.
31. An intermediate structure for a semiconductor device assembly,
comprising: a semiconductor die secured to a carrier and operably
coupled thereto for external electrical communication therethrough;
and a compressible coating element positioned on a back side of the
semiconductor die adjacent to at least a peripheral edge of the
back side, the compressible coating element comprising a material
for sealing between the back side of the semiconductor die and an
inner surface of a mold cavity to prevent an encapsulant material
introduced into the mold cavity from covering the back side of the
semiconductor die during encapsulation of the intermediate
structure in the mold cavity.
32. The intermediate structure of claim 31, wherein the
compressible coating element is sized and configured to
substantially cover the back side of the semiconductor die.
33. The intermediate structure of claim 31, wherein the
compressible coating element is sized and configured to
substantially overlie the back side of the semiconductor die
proximate a peripheral edge thereof.
34. The intermediate structure of claim 33, wherein the
compressible coating element is sized and configured so that a
portion of the back side of the semiconductor die is exposed.
35. The intermediate structure of claim 31, wherein the
compressible coating element comprises a compliant or a resilient
material.
36. The intermediate structure of claim 31, wherein the
compressible coating element exhibits a coefficient of thermal
expansion similar to a coefficient of thermal expansion of the
semiconductor die.
37. An electronic system comprising: a processor in communication
with at least one input device and at least one output device; and
a semiconductor assembly, comprising: at least one semiconductor
die; a carrier positioned adjacent to an active surface of the at
least one semiconductor die and oriented substantially parallel
thereto, the carrier being in communication with at least one of
the processor, the at least one input device, and the at least one
output device; at least one intermediate conductive element
electrically connecting a bond pad of the at least one
semiconductor die and a corresponding contact of the carrier; an
encapsulant covering at least an outer periphery of the at least
one semiconductor die; and a compressible coating element on a back
side of the at least one semiconductor die, at least a substantial
portion of the compressible coating element being exposed.
38. The electronic system of claim 37, wherein the compressible
coating element comprises a layer that substantially covers the
back side of the at least one semiconductor die.
39. The electronic system of claim 37, wherein the compressible
coating element comprises a layer that overlies the back side at
least proximate an outer periphery of the back side of the at least
one semiconductor die.
40. The electronic system of claim 39, wherein the layer is
configured so that a portion of the back side of the at least one
semiconductor die is exposed.
41. The electronic system of claim 37, wherein the compressible
coating element is positioned on the back side of the at least one
semiconductor die adjacent to an outer periphery thereof, a central
portion of the back side remaining exposed.
42. The electronic system of claim 37, wherein the compressible
coating element comprises a compliant or resilient material.
43. The electronic system of claim 37, wherein the compressible
coating element exhibits a coefficient of thermal expansion similar
to a coefficient of thermal expansion of the at least one
semiconductor die.
44. The electronic system of claim 37, wherein the encapsulant
substantially encapsulates the at least one intermediate conductive
element.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No.
10/154,640, filed May 24, 2002, pending.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to packaging of
semiconductor dice and, more specifically, packaging of
semiconductor dice to provide improved heat dissipation
characteristics.
[0004] 2. State of the Art
[0005] During operation, semiconductor devices typically generate
large amounts of heat. The amount of heat that a semiconductor
device generates is typically related, if not proportional to, the
density of features of the semiconductor device. Heat reduces the
reliability with which semiconductor devices, including processors
and memory devices, operate. In addition, the exposure of
semiconductor devices to elevated temperatures for prolonged
periods of time may also decrease the useful lives thereof.
Accordingly, the dissipation of heat from semiconductor devices has
long been a concern in the semiconductor device industry.
[0006] The reduced power requirements of state-of-the-art
semiconductor dice have been useful for decreasing the amount of
heat generated by such semiconductor dice. Nonetheless, as feature
densities are ever-increasing, the temperatures generated by
semiconductor dice with even reduced power requirements will also
continue to increase. Thus, heat dissipation continues to be of
concern, even with the low power requirements of state-of-the-art
semiconductor dice.
[0007] When a semiconductor die is encapsulated, or packaged, the
most delicate regions thereof, such as the active surface that
bears integrated circuitry and the bond wires that connect bond
pads of the semiconductor die to corresponding leads of a lead
frame or contacts of a carrier substrate, are covered with a
dielectric protective material. In addition, other, more robust
surfaces of the semiconductor die, such as the peripheral edges and
back side thereof, are also covered with dielectric protective
material. Unfortunately, many of the dielectric protective
materials that are used to encapsulate semiconductor dice are not
good heat conductors. As a result of the manner in which such
dielectric protective materials have been used to coat
semiconductor dice, a large amount of the heat generated by an
encapsulated semiconductor die becomes trapped within or around the
die.
[0008] Several approaches have been taken to improve the rate at
which heat is transferred and dissipated from packaged
semiconductor devices. Conventionally, large surface area
structures formed from materials that have good heat conductivity
properties and, thus, which are able to "pull" or transfer heat
away from a structure, such as a semiconductor die, contacted
thereby have been used to dissipate heat from the package during
operation of the semiconductor die or dice thereof. These large
surface area structures are generally known in the art as "heat
sinks." Air circulation systems, which often include cooling fans,
have also been used, typically in combination with heat sinks or
other heat dissipation means. While heat sinks and air circulation
systems may be useful for maintaining conventionally configured
semiconductor dice at acceptable operational temperatures in some
applications, heat sinks are typically fairly massive and the size
thereof prevents further increases in the densities at which
semiconductor devices are carried upon circuit boards, as is
desired to maintain the trend for ever-decreasing electronic device
sizes. In addition, heat sinks may also present locational problems
between adjacent, superimposed circuit boards and for
space-critical applications such as laptop and notebook computers,
cell phones, personal digital assistants and the like.
[0009] As an alternative to the use of space-consuming heat sinks,
encapsulation processes have been modified to reduce the amount of
dielectric protective material that covers the surfaces of
semiconductor dice. Additionally, encapsulation techniques have
been developed that protect the most delicate portions of a
semiconductor die, while leaving other surfaces of the
semiconductor die bare, thereby improving heat dissipation
therefrom.
[0010] One such technique is described in U.S. Pat. No. 5,604,376
to Hamburgen et al. (hereinafter "Hamburgen"), which describes a
packaged semiconductor device in which a back side of a
semiconductor die is exposed through an encapsulant to facilitate
the dissipation and transfer of heat from the back side of the
semiconductor die. The packaged semiconductor device of Hamburgen
also includes leads to which bond pads of the semiconductor die are
electrically connected. The assembly and packaging method described
in Hamburgen includes temporarily securing a bare semiconductor die
upon a pedestal by application of a vacuum through the pedestal to
a back side of the semiconductor die. Leads are then electrically
connected to corresponding bond pads of the semiconductor die by
way of conventional wire bonding processes. Next, the assembly is
positioned over a bottom half of a mold, with the back side of the
semiconductor die resting upon a platform. Upon enclosing the
semiconductor die and the bond wires within a cavity of the mold
and as a molding compound is introduced into the cavity, a negative
pressure is applied through an aperture in the platform to the back
side of the semiconductor die, causing the back side of the
semiconductor die to be pulled against the platform and purportedly
preventing the molding compound from flowing onto the back side of
the semiconductor die. This process may be somewhat undesirable for
several reasons. For example, as the semiconductor die and the mold
platform therefor are both rigid structures, any deviations in the
planarity or mutual orientation of either the back side of the
semiconductor die or the surface of the platform may permit molding
compound to flow therebetween. Such planarity deviations, coupled
with the force applied to the semiconductor die to temporarily
secure the same to the mold platform, may also exert potentially
damaging stresses on the semiconductor die during the encapsulation
process.
[0011] Another example of a packaged semiconductor device that
includes a semiconductor die with an exposed back side is described
in U.S. Pat. No. 6,348,729 to Li et al. (hereinafter "Li"). The
packaged semiconductor device of Li is formed by attaching an
adhesive-coated tape or film to a surface of a lead frame and
securing a semiconductor die to the adhesive-coated tape or film,
within a centrally located opening of the lead frame. Bond pads of
the semiconductor die are then electrically connected with
corresponding leads of the lead frame by forming or positioning
intermediate conductive elements (e.g., bond wires) therebetween.
Next, the semiconductor die, intermediate conductive elements, and
regions of the leads that are located adjacent to the semiconductor
die and above the tape or film are encapsulated. Finally, the tape
or film is removed from the packaged semiconductor device structure
(e.g., by peeling). Unfortunately, in addition to exposing the back
side of the semiconductor die, surfaces of the leads are also
somewhat undesirably exposed. Exposure of the bottom surfaces of
the leads may increase the likelihood of electrical shorting
between leads as the packaged semiconductor device is positioned
upon a carrier substrate, such as a circuit board. Moreover, upon
securing the packaged semiconductor device of Li to a carrier
substrate, the back side of the semiconductor die thereof will be
positioned adjacent or very closely to the carrier substrate, which
may hinder the dissipation of heat from the back side of the
semiconductor die, defeating the intent of exposing the back
side.
[0012] During the preliminary stages of semiconductor device
fabrication processes, the back sides of silicon wafers and other
bulk semiconductor substrates are typically adhered to a preformed
dielectric protective film, such as a polyimide film. In addition
to protecting the back sides of substrates during fabrication
processes and as the substrates are being handled and transported
from one fabrication process location to another, these dielectric
protective films also retain the positions of the various
semiconductor devices that have been fabricated on a particular
semiconductor substrate following singulation of the semiconductor
devices, which are, at this point, commonly referred to as "dice,"
from one another. The dice may then be tested or otherwise
evaluated, and operable, useful dice picked from the dielectric
protective film for further testing, assembly, or packaging.
[0013] The inventors are not aware of structures that facilitate
heat dissipation from a back side of a semiconductor die through a
molded encapsulant while reducing compressional stresses on the
semiconductor die during encapsulation thereof and without
undesirably increasing the size of the packaged semiconductor
device or causing electrically conductive structures from being
undesirably exposed through the encapsulant.
BRIEF SUMMARY OF THE INVENTION
[0014] The present invention includes methods and apparatus for
packaging semiconductor device assemblies in such a way as to
facilitate the transfer of heat from the back sides of
semiconductor dice thereof.
[0015] One aspect of the present invention includes a coating
element for use on a back side of a semiconductor die. The coating
element is configured to seal against a surface of a mold cavity
during packaging of a semiconductor device assembly of which the
semiconductor die is a part to prevent packaging material from
covering or "flashing" over the back side of the semiconductor die.
The coating element may also protect the back side of the
semiconductor die during encapsulation of at least portions of the
semiconductor device assembly. Accordingly, the material of the
coating element may be a somewhat compressible or compliant, and
resilient, material which is configured to act as a sealant against
an inside surface of a mold while packaging the semiconductor
device assembly. The materials of the coating element may also be
compressible and compliant, but not necessarily resilient so that
it remains in a substantially compressed state after the
encapsulation process. The material of the coating element may also
be somewhat durable so that the coating element may protect the die
during the assembly and encapsulation processes.
[0016] The back side of a semiconductor die may receive a coating
element prior to severing the semiconductor die from a common
substrate upon which a plurality of semiconductor dice or other
electronic components has been fabricated (e.g., at the wafer
level), subsequent to singulating the semiconductor die from a
wafer or other common substrate, or following assembly of the
semiconductor die with a carrier therefor. The coating element may
comprise a preformed, substantially planar element or a quantity of
uncured material that will be cured and, optionally, patterned
following application thereof to the back side of the semiconductor
die. The coating element may be applied so as to cover
substantially the entire back side of the semiconductor die or, in
a variation, to cover only a portion of the back side of the
semiconductor die at or proximate a lateral periphery thereof. In
the case of applying coating elements onto semiconductor devices
that have not yet been severed or singulated from a common
substrate, the coating element may comprise a single member that
substantially covers the back side of the common substrate and
which is severed as the semiconductor devices that have been
fabricated on the common substrate are singulated from one another,
or separate coating elements may be formed on or secured to the
back sides of each yet-to-be severed semiconductor device.
[0017] A semiconductor device assembly according to the present
invention includes one or more semiconductor dice and a carrier.
The carrier and at least one semiconductor die are oriented in a
substantially parallel manner relative to one another with the back
side of the at least one semiconductor die in the assembly facing
outward in such a way as to contact a surface of a mold cavity
during encapsulation of the assembly. The carrier and each
semiconductor die assembled therewith are electrically connected to
one another by way of intermediate conductive elements, such as
bond wires, thermocompression bonded leads, conductive
tape-automated bonding (TAB) elements carried by a dielectric
polymeric film, or the like, for electrical interconnection of the
carrier to each semiconductor die thereon.
[0018] In use of a coating element according to the present
invention, a semiconductor device assembly including a
semiconductor die with a coating element on a back side thereof may
be positioned within a cavity of a mold. This may be done by
placing a portion of the assembly in either a first cavity segment
of a first mold section or a second cavity segment of a second mold
section. In other words, the semiconductor device assembly may be
positioned with the coating element adjacent a mold cavity surface
of either mold section. As the first and second mold sections are
assembled with one another, the semiconductor device assembly is
enclosed within the cavity formed by the first and second cavity
segments, with at least a portion of the carrier sitting between
the first and second mold sections. With this arrangement, the
coating element on the back side of a semiconductor die of the
assembly may be positioned and sealed against the inside surface of
a cavity half of one of the mold sections. Molten dielectric
encapsulation material may then be introduced into the mold under
pressure so that particular sensitive portions of the assembly,
such as a lateral periphery and active surface of the semiconductor
die and the intermediate conductive elements electrically
interconnecting the die to the carrier, are encapsulated. The seal
created against the surface of the mold cavity by the coating
element on the back side of the semiconductor die prevents
dielectric encapsulation material from flowing over or flashing
onto and, thus, covering a substantial portion of the back side of
the semiconductor die. By preventing the dielectric encapsulation
material from covering the back side of the semiconductor die, heat
may readily dissipate from the back side thereof. Further, the
coating element provides a compressible surface on the back side of
the semiconductor die to reduce potential stresses to the
semiconductor die, such as stresses applied to the semiconductor
die from the mold wall abutting the back side, during the
encapsulation process.
[0019] The inside surface or wall of a portion of a mold cavity
segment may include a surface finish of enhanced smoothness
relative to the finish of the remainder of the mold cavity
surfaces. Such a finish may be effected by grinding, lapping or
polishing and be at least sized, shaped and positioned on a portion
of the inside surface of the mold cavity segment to correspond with
the dimensions of the back side of the semiconductor die. During
encapsulation of the assembly, the enhanced smoothness surface
finish provides a surface that readily creates a seal with the
coating element on the back side of the semiconductor die so that
the encapsulation material cannot extrude between the back side of
the die and the inside surface to form flash on the back side
during the encapsulation of portions of the assembly.
[0020] Following encapsulation, the packaged semiconductor device
assembly may be mounted to higher-level packaging such as a circuit
board for use in an electronic system, such as a computer system.
In the electronic system, the circuit board electrically
communicates with a processor, which electrically communicates with
one or more input devices and output devices of the electronic
system.
[0021] Other features and advantages of the present invention will
become apparent to those of skill in the art through a
consideration of the ensuing description, the accompanying drawings
and the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0022] While the specification concludes with claims particularly
pointing out and distinctly claiming that which is regarded as the
present invention, the advantages of this invention may be
ascertained from the following description of the invention when
read in conjunction with the accompanying drawings, wherein:
[0023] FIG. 1 illustrates a simplified side view of a wafer having
a coating element disposed thereon, according to the present
invention;
[0024] FIG. 2 illustrates a simplified bottom view of a
board-on-chip semiconductor assembly, depicting the coating element
disposed over substantially an entire back surface of the
semiconductor die, according to a first embodiment of the present
invention;
[0025] FIG. 2(a) illustrates a simplified bottom view of a
board-on-chip semiconductor assembly, depicting the coating element
disposed proximate a periphery of the back surface of the
semiconductor die, according to a variation of the first embodiment
of the present invention;
[0026] FIG. 3 illustrates a simplified cross-sectional side view
taken along line 3-3 in FIG. 2, depicting the board-on-chip
semiconductor assembly with bond wires extending between the
semiconductor die and the carrier substrate, according to the first
embodiment of the present invention;
[0027] FIG. 3(a) illustrates a simplified cross-sectional side view
taken along line 3a-3a in FIG. 2(a), depicting the board-on-chip
semiconductor assembly with the coating element disposed proximate
the periphery of the back surface of the semiconductor die,
according to a variation of the first embodiment of the present
invention;
[0028] FIG. 4 illustrates a simplified cross-sectional side view of
the board-on-chip semiconductor assembly in a mold, depicting a
surface of the mold abutting a surface of the coating element,
according to the first embodiment of the present invention;
[0029] FIG. 4(a) illustrates a simplified partial cross-sectional
view of the mold in an unengaged position with the coating element
on the semiconductor die, according to the present invention;
[0030] FIG. 4(b) illustrates a simplified partial cross-sectional
view of the mold in an engaged position with the coating element on
the semiconductor die, according to the present invention;
[0031] FIG. 5 illustrates a simplified view of the inside surface
of the mold, depicting a matte finish and a finely ground finish on
the inside surface, according to the present invention;
[0032] FIG. 6 illustrates a simplified cross-sectional view of a
board-on-chip wire bonded semiconductor package, depicting the
coating element exposed through the encapsulation material,
according to a first embodiment of the present invention;
[0033] FIG. 7 illustrates a simplified cross-sectional view of a
board-on-chip flip-chip semiconductor package, depicting the
coating element exposed through the encapsulation material,
according to a second embodiment of the present invention;
[0034] FIG. 8 illustrates a simplified cross-sectional view of a
lead-on-chip semiconductor package, depicting the coating element
exposed through the encapsulation material, according to a third
embodiment of the present invention; and
[0035] FIG. 9 illustrates a simplified block diagram of the
semiconductor assembly of the present invention integrated in an
electronic system.
DETAILED DESCRIPTION OF THE INVENTION
[0036] Embodiments of the present invention will be hereinafter
described with reference to the accompanying drawings. It would be
understood that these illustrations are not to be taken as actual
views of any specific apparatus or method of the present invention,
but are merely exemplary, idealized representations employed to
more clearly and fully depict the present invention than might
otherwise be possible. Additionally, elements and features common
between the drawing figures retain the same or similar reference
numerals.
[0037] FIG. 1 illustrates a side view of a wafer 100. Wafer 100
includes multiple semiconductor dice 110 in a physically
interconnected array of columns and rows (not shown), each
semiconductor die 110 distinguished from others on wafer 100 by
broken lines 118, along which the semiconductor dice are separated
or singulated, as by sawing or scribing. Wafer 100, and each of the
multiple semiconductor dice 110 thereof, includes an active surface
112 and a back side 114. The wafer 100 is formed from a
semiconducting material and is preferably formed from silicon, but
may be formed from gallium arsenide, indium phosphide or any other
known semiconducting material, the electrical conductivity and
resistivity of which lie between those of a conductor and an
insulator. Other bulk substrates, including partial wafers, as well
as silicon-on-insulator (SOI) substrates (e.g., silicon-on-glass
(SOG), silicon-on-ceramic (SOC), silicon-on-sapphire (SOS), etc.)
are also within the scope of the present invention and included
within the meaning of the term "wafer."
[0038] According to the present invention, wafer 100 may receive a
coating element 150 formed on the back side 114 thereof. Coating
element 150 is configured to be compressible or compliant so as to
act as a sealant, which will be further described herein. Coating
element 150 may be a coating element applied to the semiconductor
dice 110 to reduce stresses thereto and/or prevent chipping of the
back side 114 thereof during procedures of testing, general
handling, singulation and encapsulation procedures. Coating element
150 may be configured to readily conduct and dissipate heat,
wherein coating element 150 provides a surface that easily allows
heat to dissipate from the semiconductor dice 110. The coating
element 150 may have a coefficient of thermal expansion (CTE)
similar to that of the adjacent semiconductor or insulator (in the
case of nonwafer bulk substrates) material.
[0039] Coating element 150 may be applied to the back side 114 of
each of the semiconductor dice 110 by flowing a polyimide material
thereon (e.g., by known spin-on, screen printing, spray-on, or
spreading processes). Such a technique may be especially desirable
to employ at the wafer scale. If required, filler material, such as
polysilicon, may be added to the polyimide material to adjust the
coefficient of thermal expansion to substantially match the
coefficient of thermal expansion of the back side 114 of the
semiconductor die 110. A photosensitive material such as is
employed for etch masking may also be applied, exposed, and
developed and undesired portions of the coating element 150 removed
from the back sides 114 of semiconductor dice 110, individually but
preferably at the wafer scale. In the alternative, the coating
element 150 may be already prepared as a preformed polyimide sheet
or film, wherein the polyimide sheet or film may be adhesively
attached to the back side 114 of the semiconductor die 110 using,
for example, a pressure-sensitive adhesive. Such a structure may be
termed a "wafer back side laminate." As a further variation, a
resin may be applied to a sheet, tape or film to form a composite
coating element providing sufficient adherency to the wafer 100 or
a semiconductor die 110 along with sufficient resiliency and
compressibility. The resin may provide adhesion for the sheet, tape
or film to the back sides 114 of semiconductor dice 110.
[0040] In whatever form, coating element 150 may be of sufficient
thickness such that, in combination with a selected
compressibility, it accommodates when compressed at least an
average bondline deviation (the deviation between the semiconductor
die surface and carrier substrate, such as an interposer, surface
during die mount) of between about 20 and 30 .mu.m to prevent flash
over the back side 114 during encapsulation. Thus, for example and
without limitation, an initial, resiliently compressible coating
element thickness of between about 50 and 100 .mu.m may be used to
allow for and accommodate bondline deviation while still minimizing
the height of the finished package and any thermal barrier to heat
transfer from the back side 114 of semiconductor die 110.
[0041] The wafer 100 may be singulated along broken lines 118 to
provide multiple semiconductor dice 110. The coating element 150
may be disposed on the back side 114 of each of the semiconductor
dice 110 prior to, or subsequent to, singulation thereof from the
wafer 100. In either case, each of the individual semiconductor
dice 110 receives the coating element 150 prior to a die attach
process wherein a semiconductor die 110 is secured to a carrier
substrate such as an interposer or lead frame.
[0042] FIG. 2 illustrates a bottom view of a board-on-chip (BOC)
assembly subsequent to the die attach process. The singulated
semiconductor die 110 having the coating element 150 formed on a
back side 114 thereof may be attached to a carrier substrate 120.
Specifically, as shown, the semiconductor die 110 is attached with
its active surface toward the carrier substrate 120 so that the
coating element 150 is facing outward.
[0043] FIG. 3 is a cross-sectional view taken along line-3-3 in
FIG. 2, illustrating the carrier substrate 120 and semiconductor
die 110 and the interconnections therebetween. The carrier
substrate 110 includes a first surface 122 and a second surface 124
with an opening 126 that may be centrally located in the carrier
substrate 120 and extends between the first surface 122 and the
second surface 124 on the carrier substrate 120. Carrier substrate
120 may be any suitable carrier-type substrate known in the art,
such as an interposer or printed circuit board. Carrier substrate
120 may also be made of any type of substrate material known in the
art, such as bismaleimide triazine (BT) resin, ceramics, flexible
polyimides, FR-4 or FR-5 materials, glass, insulator-coated
silicon, or the like.
[0044] The semiconductor die 110 includes an active surface 112 and
a back side 114 with bond pads 116 formed on the active surface 112
thereof. The bond pads 116 may be centrally located and exposed on
the active surface 112 of the semiconductor die 110 and
interconnected with integrated circuitry (not shown) on the active
surface 112 of the semiconductor die 110. With this arrangement,
the carrier substrate 120 may be secured to a peripheral region of
the active surface 112 of the semiconductor die 110 so that the
bond pads 116 may be exposed through the opening 126 of the carrier
substrate 120. The semiconductor die 110 may be attached to the
carrier substrate 120 with one or more adhesive elements 130. The
adhesive element 130 may be any known adhesive structure, such as
an adhesive decal, adhesive-coated tape, a liquid or gel adhesive
material, or the like. Bond wires 132 or other intermediate
conductive elements (e.g., conductive tape-automated bonding (TAB)
conductive elements carried upon a dielectric polymer film,
thermocompression-bonded leads, etc.) may then be formed or
extended between the bond pads 116 on the active surface 112 of the
semiconductor die 110 and their corresponding conductive pads 128
on the second surface 124 of the carrier substrate 120, with bond
wires 132 or other intermediate conductive elements extending
through the opening 126.
[0045] As illustrated in FIGS. 2 and 3, the coating element 150 may
substantially cover the entire back side 114 of the semiconductor
die 110 and face outward from the assembled semiconductor die 110
and carrier substrate 120.
[0046] FIG. 2(a) illustrates a variation of the coating element
150. In this variation, coating element 150' is disposed on the
back side 114 and forms a frame proximate only a periphery 115 of
the semiconductor die 110. This variation provides that a central
portion of the back side 114 of the semiconductor die 110 is left
without the coating element 150'. In this alternative, it is
contemplated that the coating element 150' may be applied to the
back side 114 utilizing a masking and patterning type process, as
is well known in the art, using a positive or negative photoresist.
Coating element 150' may also be applied by use of a stencil, as is
also known. The coating element 150' may be applied to the back
side 114 at a wafer level or to each semiconductor die 110 on an
individual basis.
[0047] Illustrated in FIG. 3(a) is a cross-sectional bottom view
taken along line 3a-3a in FIG. 2(a), depicting the carrier
substrate 120 and semiconductor die 110 with the coating element
150' on the back side 114 of the semiconductor die 110 according to
a variation of the first embodiment. In particular, the coating
element 150' is provided on the back side 114 proximate periphery
115 of the semiconductor die 110 so that a central portion of the
back side 114 is left without the coating element 150'.
[0048] Turning to FIG. 4, the board-on-chip assembly is positioned
in a mold 140 preparatory to encapsulating the assembly in a
transfer molding process. The term "transfer molding" is
descriptive of an example of this process, as a filled polymer
thermoplastic molding compound, in a liquid or molten state, is
transferred under pressure to a plurality of remotely located mold
cavities containing semiconductor device assemblies to be
encapsulated. However, for purposes of simplicity, only one mold
cavity 146 associated with the mold 140 is depicted in drawing FIG.
4. Pot molding processes, injection molding processes and other
encapsulation techniques may also be used with, and benefit from,
the present invention.
[0049] The mold 140 includes a first mold section 142 and a second
mold section 144, each of which includes recesses that together
form multiple mold cavities, such as the depicted mold cavity 146.
The mold cavity 146 is sized and configured to contain the
semiconductor die 110 in the assembly and, specifically, an inside
surface 148 of the mold 140 is configured with at least a portion
located and oriented to abut with the coating element 150 on the
back side 114 of the semiconductor die 110. The mold cavity 146 is
also sized and configured to contain, without contacting, the bond
wires 132 or other intermediate conductive elements that
electrically interconnect the semiconductor die 110 to the carrier
substrate 120. In this manner, the mold cavity 146 is filled with a
dielectric encapsulation material 134 (FIG. 6), such as a molding
compound introduced by transfer or injection molding, to coat,
cover and protect at least a periphery of the semiconductor die
110, the bond wires 132, bond pads 116 and conductive pads 128.
[0050] Each mold cavity 146 in a transfer mold includes a gate and
vent (not shown), as known in the art. The gate is used as an inlet
for a thermoplastic dielectric encapsulation material 134 to flow
into the mold cavity 146. The vent, typically located at an
opposite end of the mold cavity 146 from the gate, permits air or
other gases in the mold cavity 146 to be displaced by the wave
front of the dielectric encapsulation material and escape from the
mold cavity 146 upon introduction of the dielectric encapsulation
material 134 thereinto. After entry into the mold cavity 146, the
dielectric encapsulation material 134 solidifies and forms a part
of the semiconductor device assembly.
[0051] FIGS. 4(a) and 4(b) illustrate the semiconductor die 110 and
an inside surface 148 of the mold 140 in an unengaged position and
a fully engaged position, respectively. According to the present
invention, the inside surface 148 of the mold 140 may include some
regions with a relatively smoother, ground, lapped or polished
finish 154 and other regions with a rougher, matte finish 156. The
area of the enhanced smoothness finish 154 is substantially sized
and shaped to correspond with the back side 114 of the
semiconductor die 110 and may be square shaped and centrally
located within the matte finish 156 area, as depicted in FIG. 5,
illustrating a top inside view of the central, bottom portion B and
side portions S of the mold cavity segment of the first mold
section 142. The matte finish 156 area may comprise the raw, as
cast or machined, inside surface 148 of the mold 140 without
further grinding or polishing thereof. With respect to the enhanced
smoothness finish 154 area, it exhibits a fine finish, such as a
ground, lapped or polished finish, having a surface topography
configured to facilitate a seal 158 between the coating element 150
and the inside surface 148 of the mold 140. The seal 158 is
provided by coating element 150 when the semiconductor die 110 is
in the fully engaged position with the first mold section 142, such
as when the first and second mold sections 142 and 144 are
assembled with one another. In this manner, seal 158 provided by
the coating element 150 resiliently compressed between the
semiconductor die 110 and the first mold section 142 in the fully
engaged position is configured to prevent the encapsulation
material 134 from flowing over, and flashing onto, the back side
114 of the semiconductor die 110.
[0052] It will be appreciated that, once the semiconductor die 110
has been removed from the mold cavity 146, coating element 150 may
remain in a substantially compressed state and thus have an outer
surface substantially coplanar with that of the hardened dielectric
encapsulation material 134 surrounding the coating element 150.
Alternatively, the coating element 150 may have sufficient
resiliency so as to spring back to an uncompressed thickness or to
regain at least a portion thereof, in which instance the outer
surface of the coating element 150 may project slightly above the
outer surface of the surrounding, hardened dielectric encapsulation
material 134.
[0053] Turning to FIG. 6, a board-on-chip semiconductor package 160
having portions of the semiconductor die 110 and carrier substrate
120 and the electrical interconnections therebetween encapsulated
by dielectric encapsulation material 134 is illustrated. A
significant aspect of the present invention is exposure in the
finished semiconductor device package of the relatively thin
coating element 150 through the encapsulation material 134 on the
back side 114 of the semiconductor die 110. With this arrangement,
heat may readily transfer through the substrate of semiconductor
die 110 from the active surface 112 and dissipate from the back
side 114 of the semiconductor die 110. It is notable that coating
element 150, due to its relative thinness, is not a significant
impediment to heat transfer from the semiconductor die 110 and thus
need not be removed from back side 114 and remains as part of
semiconductor package 160. If desired, coating element 150 may be
colored and may include graphics thereon to identify the
manufacturer, part number, etc. Alternatively, coating element 150
may be formulated to be sensitive to heat or to specific
wavelengths of electromagnetic radiation to facilitate marking, as
by a laser, of the semiconductor package after fabrication as well
as after various stages of testing. As shown at 170, a plurality of
discrete conductive elements in the form of solder bumps,
conductive or conductor-filled epoxy pillars or columns or other
suitable structures may be applied to or formed on carrier
substrate 120 in communication with conductive traces (not shown)
of carrier substrate 120 extending to conductive pads 128 to
provide external electrical connections from semiconductor die 110
to higher-level packaging.
[0054] FIG. 7 illustrates a second embodiment of a semiconductor
package 260. The semiconductor package 260 includes a flip-chip
type assembly, wherein a semiconductor die 210 is attached facedown
to a carrier substrate 220 with discrete conductive elements such
as conductive bumps 232 therebetween. The semiconductor die 210
includes an active surface 212 and a back side 214, wherein the
back side 214 includes coating element 250 disposed thereon. The
carrier substrate 220 includes a first surface 222 and a second
surface 224. The conductive bumps 232 electrically and mechanically
interconnect the semiconductor die 210 to the carrier substrate 220
by being disposed between and bonded to bond pads 216 on the active
surface 212 of the semiconductor die 210 and conductive pads 226 on
the first surface 222 of the carrier substrate 220. A dielectric
encapsulation material 234 is introduced in a gap between the
semiconductor die 210 and carrier substrate 220, as well as around
a periphery 211 of the semiconductor die 210. Similar in fashion to
the first embodiment, the back side 214 of the semiconductor die
210 having coating element 250 thereon is exposed through the
encapsulation material 234, thereby providing an outlet for heat to
dissipate from the semiconductor die 210. Further, the exposed
coating element 250 seals to an inside surface of a mold (not
shown) during the encapsulation process, in a manner similar to
that described in the first embodiment.
[0055] With respect to FIG. 8, a third embodiment of a
semiconductor package 360 is illustrated. Semiconductor package 360
includes a leads-over-chip (LOC) type assembly, wherein there is a
carrier 320, or leads, attached to an active surface 312 of a
semiconductor die 310 via adhesive tape 330 or the like. The
carrier 320 includes a first surface 322 and a second surface 324
and is electrically interconnected to the semiconductor die 310 by
bond wires 332 or other intermediate conductive elements extending
from bond pads 316 on the active surface 312 of the semiconductor
die 310 to conductive pads 338 on second surface 324 of the carrier
320. The back side 314 of the semiconductor die 310 includes
coating element 350 disposed thereon. With this arrangement, the
leads-over-chip assembly may be encapsulated in a mold (not shown)
with encapsulation material 334 to encapsulate portions of the
semiconductor die 310, the carrier 320 and the bond wires 332 and
interconnections thereof. As in the previous embodiments, the
coating element 350 is exposed through the encapsulation material
334. Such an exposed coating element 350 may provide an outlet for
heat to dissipate from the semiconductor die 310. Other types of
lead frame-type assemblies may be utilized in the present invention
as long as the coating element 350 on the back side 314 of the
semiconductor die 310 is exposed through the encapsulation material
334 to provide a heat dissipation outlet for the semiconductor
package 360.
[0056] As illustrated in block diagram form in drawing FIG. 9,
semiconductor packages 160, 260 and/or 360 may be mounted to a
circuit board 410 in an electronic system 400, such as a computer
system. In the electronic system 400, the circuit board 410 may be
connected to a processor device 420 which communicates with an
input device 430 and an output device 440. The input device 430 may
comprise a keyboard, mouse, joystick or any other type of
electronic input device. The output device 440 may comprise a
monitor, printer or storage device, such as a disk drive, or any
other type of output device. The processor device 420 may be, but
is not limited to, a microprocessor or a circuit card including
hardware for processing instructions for the electronic system 400.
Additional structure for the electronic system 400 is readily
apparent to those of ordinary skill in the art.
[0057] While the present invention has been disclosed with
reference to certain illustrated embodiments, those of ordinary
skill in the art will recognize and appreciate that it is not so
limited. Rather, additions, deletions and modifications to the
illustrated embodiments may be made, and features and elements from
one embodiment employed, as appropriate, in another. In addition,
the coating element of the present invention may be applied between
the die and a carrier substrate such as an interposer to
accommodate bondline deviation and provide the necessary resiliency
while leaving the back side of the die bare. Further, the coating
element may be placed on the side of the carrier substrate opposite
the semiconductor die for bondline deviation accommodation and to
provide compressibility. The present invention and the scope
thereof is defined by the following claims and equivalents of the
elements, features and acts recited therein.
* * * * *