U.S. patent application number 10/766932 was filed with the patent office on 2004-09-23 for method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask.
Invention is credited to Ahn, Tae-Hyuk, Kim, Ji-Soo, Lee, Won-Seok, Park, Wan-Jae.
Application Number | 20040185664 10/766932 |
Document ID | / |
Family ID | 19617197 |
Filed Date | 2004-09-23 |
United States Patent
Application |
20040185664 |
Kind Code |
A1 |
Kim, Ji-Soo ; et
al. |
September 23, 2004 |
Method of and apparatus for manufacturing a semiconductor device
using a polysilicon hard mask
Abstract
A method and apparatus for use in manufacturing a semiconductor
device strips a polysilicon hard mask without damaging the layer
left exposed by openings formed by using the polysilicon hard mask
as an etching mask. The method includes forming a polysilicon hard
mask in a pattern on a first layer to expose a portion of the first
layer, dry etching the exposed portion of the first layer using the
polysilicon hard mask as an etching mask to form an opening in the
first layer, and thereafter removing the polysilicon hard mask by
supplying an etching gas onto the polysilicon hard mask in a
direction parallel to the major surface of the semiconductor
substrate. The processing apparatus includes a reaction chamber
including a spin chuck which supports the semiconductor substrate
for rotation, a gas supply unit for supplying a process gas to the
reaction chamber, a gas injection unit for injecting the process
gas supplied by the gas supply unit into the reaction chamber in a
direction parallel to the major surface of the semiconductor
substrate, and an exhaust unit for exhausting gases from the
reaction chamber.
Inventors: |
Kim, Ji-Soo; (Sungnam-city,
KR) ; Ahn, Tae-Hyuk; (Yongin-city, KR) ; Lee,
Won-Seok; (Sungnam-city, KR) ; Park, Wan-Jae;
(Suwon-city, KR) |
Correspondence
Address: |
JONES VOLENTINE, L.L.C.
Suite 150
12200 Sunrise Valley Drive
Reston
VA
20191
US
|
Family ID: |
19617197 |
Appl. No.: |
10/766932 |
Filed: |
January 30, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10766932 |
Jan 30, 2004 |
|
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|
09695068 |
Oct 25, 2000 |
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6719808 |
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Current U.S.
Class: |
438/689 |
Current CPC
Class: |
H01L 21/31144 20130101;
H01L 21/32137 20130101 |
Class at
Publication: |
438/689 |
International
Class: |
H01L 021/302; H01L
021/461 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 27, 1999 |
KR |
99-46909 |
Claims
What is claimed is:
1. An etching process for use in manufacturing a semiconductor
device, comprising: forming a first layer on a semiconductor
substrate; forming a polysilicon hard mask on the first layer, the
polysilicon hard mask having a pattern such that a portion of the
first layer is exposed; dry etching the exposed portion of the
first layer using the polysilicon hard mask as an etching mask to
form an opening in the first layer; and supplying an etching gas
onto the polysilicon hard mask in a direction substantially
parallel to the major upper surface of the semiconductor substrate
to thereby dry etch the polysilicon hard mask.
2. The process of claim 1, and further comprising forming a
conductive layer on the semiconductor substrate, and wherein the
forming of the first layer comprises forming a dielectric film on
the conductive layer.
3. The process of claim 1, wherein the dry etching of the first
layer forms an opening which exposes the surface of the
semiconductor substrate, and further comprising subsequently
etching the exposed portion of the semiconductor substrate to form
a trench in the semiconductor substrate.
4. The process of claim 1, wherein the supplying of an etching gas
comprises supplying an etching gas which reacts with the silicon of
the polysilicon hard mask.
5. The process of claim 1, wherein the supplying of an etching gas
comprises supplying a fluorine-containing compound.
6. The process of claim 5, wherein the etching gas comprises at
least one halogen fluoride selected from the group consisting of
CIF, CIF.sub.3, BrF, BrF.sub.3, BrF.sub.5, IF, IF.sub.3 and
IF.sub.5.
7. The process of claim 5, wherein the etching gas comprises
XeF.sub.2.
8. The process of claim 1, wherein the dry etching of the
polysilicon hard mask comprises supplying the etching gas along
with a carrier gas.
9. The process of claim 8, wherein the carrier gas is one of
nitrogen and argon.
10. The process of claim 1, wherein the dry etching of the
polysilicon hard mask comprises rotating the semiconductor
substrate while the polysilicon hard mask is exposed to the etching
gas.
11. The process of claim 1, wherein the dry etching of the
polysilicon hard mask comprises supplying the etching gas in a
series of pulses of a predetermined period.
12. The process of claim 11, wherein the dry etching of the
polysilicon hard mask is carried out at a pressure of at most
several tens of mTorr.
13. The process of claim 11, wherein the dry etching of the
polysilicon hard mask is carried out at room temperature.
14. The process of claim 11, wherein the dry etching of the
polysilicon hard mask comprises rotating the semiconductor
substrate while the polysilicon hard mask is exposed to the etching
gas.
15. An apparatus for use in manufacturing a semiconductor device,
comprising: a reaction chamber comprising a casing, and a spin
chuck disposed within said casing, said spin chuck being configured
to support a semiconductor substrate and being rotatable, whereby a
semiconductor substrate supported thereon can be rotated; a gas
supply unit connected to said reaction chamber, said gas supply
unit supplying the reaction chamber with a process gas for removing
unnecessary material from a semiconductor substrate mounted to the
spin chuck in the reaction chamber; a gas injection unit connecting
said gas supply unit to said reaction chamber, said gas injection
unit having at least one gas injection opening, each said at least
one gas injection opening being oriented such that the gas
injection unit injects the process gas, supplied by the gas supply
unit, into the reaction chamber in a horizontal direction
substantially parallel to the major upper surface of a
semiconductor substrate mounted to the spin chuck in the reaction
chamber, and an exhaust unit connected to said reaction chamber so
as to exhaust gases from the reaction chamber.
16. The apparatus of claim 15, wherein said gas supply unit
comprises a source of a fluorine-containing gaseous compound.
17. The apparatus of claim 16, wherein the compound is a gas
selected from the group consisting of CIF, CIF.sub.3, BrF,
BrF.sub.3, BrF.sub.5, IF, IF.sub.3, IF.sub.5 and XeF.sub.2.
18. The apparatus of claim 16, wherein said gas supply unit further
comprises a source of a carrier gas.
19. The apparatus of claim 15, wherein said gas injection unit is
disposed on an inner side wall of said casing of the reaction
chamber, and comprises a shower head having a plurality of gas
injection openings through which the process gas flows into the
reaction chamber in a horizontal direction above said spin
chuck.
20. The apparatus of claim 15, and further comprising a puff valve
connected in-line between said gas supply unit and said reaction
chamber, said puff valve being operative to supply the process gas
flowing from the gas supply unit into the reaction chamber as a
series of pulses of a predetermined period.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method of manufacturing a
semiconductor device. More particularly, the present invention
relates to a method of selectively etching a layer using a
polysilicon hard mask, and to an apparatus for etching away the
polysilicon hard mask, in manufacturing a semiconductor device.
[0003] 2. Description of the Related Art
[0004] The increasing demand for highly integrated, high-capacity
and high-performance semiconductor devices has fueled the need for
advances in semiconductor integrated circuit manufacturing
technology. The manufacturing of integrated circuits typically
involves selectively etching a variety of material layers to form
openings such as contact holes or trenches. To produce an
integrated circuit having a high integration density, the openings
in the material layers must be formed by a wafer processing
technique for creating a fine pattern having a line width on the
order of several micrometers at most. Research and development in
the area of such a technique, with the aim of forming deeper and
smaller openings, has concentrated on so-called dry etching.
[0005] In a common etching technique used to form openings, such as
contact holes, in a target layer on a semiconductor wafer, a
photoresist pattern is formed on the target layer (for example, on
an oxide layer), and the portions of the target layer which are
exposed by the photoresist pattern are dry etched using the
photoresist pattern as an etching mask. The smaller the desired
contact holes, the lower the etching rate must be. Because the
thickness of the photoresist pattern can dictate the etching rate,
the photoresist pattern to be used as an etching mask must be thick
if the contact holes are to be small. For instance, for a 280 nm
metal contact, if an oxide layer to be dry etched has a thickness
of about 1.5 .mu.m, a photoresist pattern having a relatively high
thickness of about 1.6 .mu.m is required.
[0006] However, future generation photolithography processes use an
ArF eximer laser. On the other hand, a photoresist layer having a
thickness of 300 nm or more is not sensitive to light of the
wavelength produced by an ArF laser. Therefore, the typical
photoresist is impractical for use in forming small contact
holes.
[0007] Thus, a hard mask formed of polysilicon, Al.sub.2O.sub.3,
Si.sub.3N.sub.4 or SiON must be used in forming deeper and smaller
contact holes. Of these masks, the one of polysilicon is now widely
being used.
[0008] In a conventional manufacturing technique using a hard mask
of polysilicon, after the polysilicon mask is used in the etching
process, the mask is stripped by chemical mechanical polishing
(CMP), wet etch back, or dry etch back processes.
[0009] However, stripping the polysilicon hard mask using CMP is
costly and CMP cannot completely remove the hard mask due to steps
on the wafer. The wet etch back technique exhibits a good etching
selectivity with respect to other layers, but it can cause damage
during a drying step after the etching process. In addition, the
etchant used in the wet etch back technique can penetrate to other
non-target layers, whereby the other layers are inadvertently
etched.
[0010] The conventional dry etching process employed in removing
the polysilicon hard mask is relatively simple. However, the etch
selectivity with respect to other non-target layers is not very
good. Therefore, a non-target material layer can be removed along
with the hard mask during the stripping process. In particular, if
pads or conductive layers exposed through the contact holes formed
by the dry etching are of the same material as the polysilicon hard
mask, e.g. are of the same polysilicon, single crystal silicon or
metal silicide, the pads or the conductive layers can be removed
when the hard mask is stripped from the target layer.
SUMMARY OF THE INVENTION
[0011] It is an object of the present invention to solve the
above-described problems of the prior art
[0012] More specifically, a first object of the present invention
is to provide a method of manufacturing a semiconductor device, in
which a polysilicon hard mask used for forming openings in a
semiconductor wafer can be removed easily and at low cost without
adversely affecting material layers left exposed by the
openings.
[0013] Another object of the present invention is to provide an
apparatus for manufacturing a semiconductor device, by which a hard
mask only can be removed from a semiconductor substrate even after
a layer of the same material as the hard mask is left exposed by
openings formed using the hard mask.
[0014] The objects of the present invention are achieved by a
method and apparatus in which an etching gas, used to strip the
polysilicon hard mask after the mask has been used to form openings
in a target layer on a semiconductor substrate, is supplied in a
direction substantially parallel to the major upper surface of the
semiconductor substrate.
[0015] The semiconductor substrate is mounted to a chuck within a
reaction chamber. A gas injection unit in the form of a shower head
mounted to the inner sidewall of the reaction chamber is used to
supply the etching gas into the chamber in the direction parallel
to the major surface of the semiconductor substrate. The chuck is
preferably a spin chuck. The semiconductor substrate is rotated by
the spin chuck while the polysilicon hard mask is exposed to the
etching gas, whereby the etching gas is distributed uniformly to
ensure a uniform dry etching of the polysilicon hard mask.
[0016] The etching gas preferably comprises a halogen fluoride
compound selected from the group consisting of CIF, CIF.sub.3, BrF,
BrF.sub.3, BrF.sub.5, IF, IF.sub.3 and IF.sub.5 or a
flourine-containing compound such as XeF.sub.2. Moreover, the
etching gas can be supplied using a carrier gas, such as nitrogen
or argon. The dry etching of the polysilicon hard mask can be
carried out at a pressure of only several tens of mTorr or less,
and at room temperature.
[0017] Moreover, the process gas is preferably supplied into the
reaction chamber as a series of pulses of a predetermined period. A
puff valve connected in-line between a gas supply unit and the
reaction chamber, and in particular, between the gas supply unit
and the gas injection unit, is operative to supply the etching gas
into the reaction chamber as a series of pulses.
[0018] According to the present invention as summarized above, the
mean free path of the etching gas in the lateral direction of the
semiconductor substrate is significantly longer than that of
etching gas conventionally supplied perpendicular to the major
upper surface of a semiconductor substrate. Therefore, even if the
layer exposed in the openings in the polysilicon hard mask is of a
silicon-containing material, the polysilicon hard mask can be
effectively removed without damaging that silicon-containing
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other objects, features and advantages of the
present invention will become more apparent by referring to the
following detailed description of the preferred embodiments thereof
made with reference to the attached drawings, of which:
[0020] FIG. 1 is a schematic diagram of an apparatus for
manufacturing a semiconductor device according to the present
invention;
[0021] FIG. 2A is an illustration of a gas pulsing technique
executed according to the present invention;
[0022] FIG. 2B is an illustration of a pressure variation within
the reaction chamber of the semiconductor manufacturing apparatus
during the course of the gas pulsing technique;
[0023] FIGS. 3A and 3B are sectional views of a semiconductor
wafer, illustrating an embodiment of a method for use in
manufacturing a semiconductor device according to the present
invention; and
[0024] FIGS. 4A and 4B are sectional views of a semiconductor
wafer, illustrating another embodiment of a method for use
manufacturing a semiconductor device according to the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] With reference to FIG. 1, the semiconductor device
manufacturing apparatus includes a reaction chamber 20, in which an
unnecessary material layer on a semiconductor wafer W is dry etched
in a predetermined atmosphere, and a gas supply unit for supplying
process gases into the reaction chamber 20.
[0026] The gas supply unit includes two gas supply sources 32 and
42 which contain process gases used for removing unnecessary
material from the semiconductor wafer W. In particular, the first
gas supply source 32 contains a source(s) of etching gases for
etching away the unnecessary material, and the second gas supply
source 42 contains a carrier gas. The etching gases of the first
gas supply source 32 include halogen fluorides such as CIF,
CIF.sub.3, BrF, BrF.sub.3, BrF.sub.5, IF, IF.sub.3 and IF.sub.5, or
a fluorine-containing compound such as XeF.sub.2. However, the
process gas is not limited to these gases. The carrier gas
contained in the second gas supply source 42 may be nitrogen or
argon.
[0027] In addition, the semiconductor device manufacturing
apparatus according to the present invention includes a gas
injection unit 64 for injecting the process gases from the first
and second gas supply sources 32 and 42 into the reaction chamber
20 in the direction indicated by arrows A in FIG. 1, i.e., parallel
to the major surface of the semiconductor wafer W.
[0028] The gas injection unit 64 is connected to the first and
second gas supply sources 32 and 42 through a pipe 68. The
supplying of gas from the first and second gas supply sources 32
and 42 is controlled by shut-off valves 34 and 44, which are
connected to the first and second gas supply sources 32 and 42,
respectively. The flow rate of the gas is controlled by mass flow
controllers (MFCs) 36 and 46, which are connected in respective
lines extending from the first and second gas supply sources 32 and
42.
[0029] The process gases from the first and second gas supply
sources 32 and 42 are mixed in a reservoir 60, and introduced into
the reaction chamber 20 through the feed pipe 68 and the gas
injection unit 64. Also, a pressure gauge 66 is disposed on the
feed pipe 68 so as to monitor the pressure of the process gases
issuing from the reservoir 60.
[0030] However, the reservoir 60 can be omitted. In this case, the
process gases from the first and second gas supply sources 32 and
42, whose flow rates are controlled by the MFCs 36 and 46, are
supplied directly into the reaction chamber 20. During an etching
process, the etching gas and the carrier gas can be simultaneously
supplied by appropriately controlling the shut-off valves 34 and 44
as needed. Alternatively, the shut-off valves 34 and 44 can be
controlled such that only the etching gas from the first gas supply
source 32 is supplied.
[0031] The gas injection unit 64 may comprise a shower head capable
of injecting the process gases in the direction parallel to the
major surface of the semiconductor wafer W, in which case the
shower head is disposed adjacent the inner sidewall of the reaction
chamber 20. The shower head may have a number of gas injection
openings 64a each having a diameter of, for example, several
millimeters. The gas injection openings 64a are uniformly arrayed
over the entire front face of the shower head, so that the number
of the gas injection openings 64a per unit area is constant over
the entire front face of the shower head. As a result, the gas
injection amount, i.e., the amount of gas supplied per unit area at
the front of the shower head, is uniform. The process gases are
thus supplied at a constant rate through the gas injection unit 64
into the reaction chamber 20.
[0032] A spin chuck 22 for supporting the semiconductor wafer W
horizontally is disposed inside the casing 21 of the reaction
chamber 20. The spin chuck 22 can be rotated by a motor 24. The
semiconductor wafer W is rotated by the spin chuck 22 while the
process gas is introduced into the reaction chamber 20 through the
gas injection unit 64, so that the process gas can be uniformly
supplied over the top surface of the semiconductor wafer W.
[0033] A heating means (not shown) can be integrated with the spin
chuck 22 so as to control the temperature of the semiconductor
wafer W during processing.
[0034] An exhaust pump 52 is connected to the reaction chamber 20
through an exhaust pipe 58. The exhaust pump 52 evacuates the
reaction chamber 20 down to near high vacuum levels. The reaction
chamber 20 has a pressure gauge 26 for monitoring the pressure
inside the casing 21.
[0035] When an etching process is carried out in the reaction
chamber 20, the reaction gas is exhausted from the reaction chamber
20 by the exhaust pump 52. The exhaust flows through the exhaust
pipe 58 to a scrubber 54. The scrubber 54 adsorbs toxic gases
exhausted from the reaction chamber 20.
[0036] In addition, a puff valve 62 is disposed in-line upstream of
the gas injection unit 64 to cause the process gases from the
reservoir 60 to be supplied in puffs, i.e. as a series of pulses,
into the reaction chamber 20 in a predetermined sequence.
[0037] FIG. 2A illustrates this sequence of supplying gas into the
reaction chamber 20 using the puff valve 62, and FIG. 2B
illustrates the pressure variation in the reaction chamber 20
during the pulsing of gas by the puff valve 62.
[0038] In FIG. 2A, .DELTA.t1 designates the time during which the
process gas is supplied into the reaction chamber 20. During the
time .DELTA.t1, the process gas from the reservoir 60 is supplied
into the reaction chamber 20 through the pipe 68, and the reaction
chamber 52 is simultaneously evacuated by the exhaust pump 52.
.DELTA.t2 designates the time during which the process gas does not
flow into the reaction chamber 20. During the time .DELTA.t2, the
reaction chamber 20 is being evacuated by the exhaust pump 52,
while the flow of process gas into the reaction chamber 20 is cut
off.
[0039] The rate R of etching polysilicon on a semiconductor wafer
with BrF.sub.3, as a function of the temperature of the
semiconductor wafer in an equilibrium state of the etching
reaction, can be expressed by Arrhenius' equation as follows:
R(.ANG./min)=1.16E-18.times.n.times.T.sup.1/2 exp(-E.sub.a/kT)
(1)
[0040] In formula (1), n represents the density of BrF.sub.3,
E.sub.a represents the effective activation energy of the etching
reaction, k represents the Boltzmann constant
(1.987.times.10.sup.-3 kcal/mole/.degree.K), and T represents the
temperature of the semiconductor wafer in .degree.K (refer to J.
Appl. Phys. 56(10), 2939, 1984, by D. E. Ibbotson et al.).
[0041] As can be understood from the formula (1), when the pressure
of the reaction chamber reaches several hundreds of mTorr to
several Torr as a predetermined amount of BrF.sub.3 flows into the
reaction chamber, the etching rate increases to as fast as several
thousand .ANG./min to several .mu.m/min. In this case, the mean
free path of BrF.sub.3 in the gaseous phase is as short as several
.mu.m.
[0042] In the case where a layer of silicon-containing material
such as polysilicon or a metal silicon is exposed in the openings
in a polysilicon hard mask, a conventional technique of etching
away the polysilicon hard mask using BrF.sub.3 as an etching gas
may also remove the silicon-containing material. Thus, in the case
where the material layer exposed in the openings is of a
silicon-containing material, one could not use the conventional
technique of stripping the polysilicon hard mask using BrF.sub.3
without seriously risking damage to the material layer.
[0043] To avoid this problem, the semiconductor device
manufacturing apparatus according to the present invention supplies
the etching gas in a direction parallel to the major surface of the
semiconductor wafer such that the mean free path of the etching gas
molecules is increased, and the etching rate can be accurately
controlled over the entire surface of the semiconductor wafer.
[0044] In the semiconductor device manufacturing apparatus
according to the present invention, while the pressure of the
reaction chamber 20 is maintained as low as several tens of mTorr,
the process gases are supplied into the reaction chamber 20 in the
direction parallel to the major surface of the semiconductor wafer
W by the gas injection unit 64. In addition, the process gases are
supplied in pulses into the reaction chamber 20 using the puff
valve 62.
[0045] Generally, the capacity of the reaction chamber 20 is
several tens of times greater than the capacity of the reservoir
60. In this case, if the pressure inside the reservoir 60 is
maintained at several Torr, the peak pressure of the reaction
chamber 20, which is determined by the pulse-type supply of the
process gases into the reaction chamber 20, will be as low as about
several tens of mTorr. In this case, the mean free path of the
etching gases in the horizontal direction is increased to the order
of millimeters, and the etching rate in the reaction chamber 20
reaches several hundreds of .ANG./min during the time the etching
gas is flowing into the chamber, i.e., during the time
.DELTA.t1.
[0046] In order to adequately etch the polysilicon layer away in
the horizontal direction, the time .DELTA.t1 for supplying the
etching gas into the reaction chamber 20, as shown in FIG. 2A, is
preferably set within a range of several tens of seconds to several
minutes. The time .DELTA.t2 during which the supply of etching
gases is cut off, is set to be several times the time .DELTA.t1
according to the exhaust capacity. If the time .DELTA.t1 is about 1
minute, the polysilicon hard mask, remaining after the openings are
formed, has a thickness of several thousand .ANG. and can be
completely removed by pulsing the supply gas merely several tens of
times, and without damaging the other material layers exposed in
the openings. In addition, the semiconductor wafer W is preferably
rotated at several tens of rpms while the process gases are
supplied (pulsed) to thereby produce a uniform etching of the
entire surface of the semiconductor wafer W.
[0047] In the operation of the semiconductor device manufacturing
apparatus according to the present invention, a semiconductor wafer
W on which a polysilicon hard mask remains is loaded on the spin
chuck 22 in the reaction chamber 20. Then, the reaction chamber 20
and the reservoir 60 are evacuated down to 1 mTorr or less. The
puff valve 62 is closed so that the reservoir 60 is filled with an
etching gas, for example, BrF.sub.3. Then, the puff valve 62 is
turned on and off such that BrF.sub.3 is supplied to the reaction
chamber 20 in pulses as represented in FIG. 2A. The gas injection
unit 64 causes the etching gas from the reservoir 60 to be supplied
into the reaction chamber 20 in a direction parallel to the major
surface of the semiconductor wafer W. During the pulsing operation
of the puff valve 62, the reaction chamber 20 is continuously
evacuated by the exhaust pump 52. While the etching gas is supplied
into the reaction chamber 20, the semiconductor wafer W is rotated
at a low speed by the spin chuck 22 so that the etching gas is
uniformly distributed over the semiconductor wafer W.
[0048] Because the etching gas is supplied into the reaction
chamber in a direction parallel to the major surface of the
semiconductor wafer in a series of pulses while the pressure of the
reaction chamber is maintained at low levels, the mean free path of
the etching gas in the lateral direction of the semiconductor wafer
is long. As a result, the polysilicon hard mask can be effectively
removed from the semiconductor wafer without the exposed material
layer being damaged even if the exposed material layer contains
silicon.
[0049] Next, preferred embodiments of the method of manufacturing a
semiconductor device according to the present invention will now be
described more fully with reference to FIGS. 3A-4B. In these
drawings, the thickness of layers and regions are exaggerated for
the sake of clarity. It should also be understood that when a layer
is referred to as being "on" another layer or substrate, such a
description means that the layer can be disposed directly on the
other layer or substrate, or intervening layers may be present
therebetween.
[0050] Referring now to FIG. 3A, reference numeral 100 designates a
substrate formed of, for example, silicon or epitaxial silicon. A
field oxide layer 102 is formed over the substrate 100 to define
active regions. A gate oxide layer 104, a gate electrode 106, a
source region 112 and a drain region 114 are formed over the
substrate 100. The gate electrode 106 may be a single conductive
layer of, for example, polysilicon, or a composite layer of
polysilicon and metal silicide stacked one atop the other.
[0051] Reference numeral 122 designates a conductive pattern for
bit lines or conductive pads formed over a first interlayer
dielectric (ILD) film 120. The conductive pad 122 is covered with a
second ILD film 130.
[0052] In the manufacture of common semiconductor devices, via
holes or openings (hereinafter, simply referred to as contact
holes) are formed through the second or first ILD film. The contact
holes are filled with a conductive material such as aluminum (Al),
tungsten (W) or polysilicon. Because the contact holes of a
semiconductor device having a high integration density are so small
and deep, they cannot be made using a typical photolithography
technique. To form such small and deep contact holes, a polysilicon
hard mask 140 must be formed on the second ILD film 130 as an
etching mask.
[0053] Contact holes H1, H2 and H3 are thus formed using the hard
mask 140 as an etching mask. The contact holes H1 are formed
through the second and first ILD films 130 and 120 to expose the
source region 112 and the drain region 114. The contact hole H2 is
formed through the second and first ILD films 130 and 120 to expose
the top of the gate electrode 106, and the contact hole H3 is
formed only through the second IDL film 130 to expose the top of
the conductive pattern 122.
[0054] Then, the substrate 100 is loaded into the reaction chamber
20 of the semiconductor device manufacturing apparatus, as shown in
FIG. 1, so as to remove the polysilicon hard mask 140.
[0055] Next, the etching gas 0.150, which is effective in removing
the polysilicon hard mask 140, is supplied into the reaction
chamber 20 in the direction indicated by the arrows A in FIG. 1,
i.e., parallel to the major surface of the substrate 100. Compounds
capable of reacting with silicon in a gas-phase without generating
plasma include halogen fluorides such as CIF, CIF.sub.3, BrF,
BrF.sub.3, BrF.sub.5, IF, IF.sub.3 and IF.sub.5, and
fluorine-containing compounds such as XeF.sub.2.
[0056] Most of the exemplary etching gases above include an ionic
bond between elements of different groups of the periodic table,
and have very low bonding energies. In other words, because the
etching gases are in an unstable state, the etching gases are
highly likely to react with silicon.
[0057] Also, the etching gas may be supplied together with a
carrier such as nitrogen or argon. The etching gas is supplied
periodically, i.e., in pulses, over the substrate 100 using, for
example, the puff valve 62 shown in FIG. 1. In order to uniformly
distribute the etching gas 150 over the polysilicon hard mask 140
on the substrate 100, the substrate 100 is rotated by the spin
chuck 22 at relatively low speeds, for example, at several tens of
rpms.
[0058] As a result, the mean free path of the etching gas 150 is
rather long. While the etching gas 150 is supplied over the
substrate 100, parallel to the major surface of the substrate 100,
the reaction chamber 20 is evacuated by the exhaust pump 52. By
flowing horizontally over the substrate 100, the etching gas 150
contacts the polysilicon hard mask 140 but does not to flow into
the contact holes H1, H2 and H3.
[0059] Thus, as shown in FIG. 3B, the polysilicon hard mask 140 can
be completely removed without damaging the gate electrode 106, the
source region 112, the drain region 114 and the conductive pattern
122, which are all exposed in the contact is holes H1, H2 and
H3.
[0060] Although the present invention has been described with
respect to the formation of contact holes used, in turn, for
forming connections with conductive patterns, such as gate
electrodes, source regions, drain regions, bit lines or pads, the
method of the present invention can also be applied to other
semiconductor manufacturing processes for forming small openings.
For example, the method can be applied to forming via holes between
first and second metal layers, second and third metal layers, or
first and third metal layers.
[0061] In addition, the method of manufacturing a semiconductor
device according to the present invention can be applied to forming
openings other than contact holes. For example, as shown in FIGS.
4A and 4B, the method of manufacturing a semiconductor device
according to the present invention can be applied to forming
isolation trenches which are smaller than those which can be formed
using a typical lithography process.
[0062] In FIG. 4A, reference numeral 200 designates a substrate
made of, for example, silicon or epitaxial silicon. Reference
numeral 212 designates a pad oxide layer, reference numeral 214
designates a silicon nitride layer, and reference numeral 216
designates a silicon oxide layer.
[0063] A polysilicon hard mask 220, which defines a trench region,
is formed on the silicon oxide layer 216. Then, the silicon oxide
layer 216, the silicon nitride layer 214 and the pad oxide layer
212 are anisotropically etched using the polysilicon hard mask 220
as an etching mask. Then, the exposed substrate 200 is further
etched to form a trench T.
[0064] Next, the polysilicon hard mask 220 is removed by the same
technique described with reference to FIG. 3A. As a result, as
shown in FIG. 4B, the polysilicon hard mask 220 is completely
removed without damaging the exposed surface of the substrate 200
defining the bottom of the trench T.
[0065] Still further, the process for use in manufacturing a
semiconductor device according to the present invention is not
limited to the embodiments described above. For example, the
inventive method can be adopted in etching the back side of a
wafer. That is, a compound capable of etching a silicon material
layer in a gas-phase without generating plasma is used as an
etching gas, and the etching gas is supplied to the back side of a
wafer in a direction parallel to the major surface of the wafer, so
that the back side of the wafer can be selectively etched. In this
case, compared to a common technique for etching the back side of a
wafer by wet or plasma etching, the number of processing steps can
be decreased, thereby lowering the processing cost.
[0066] Finally, although the present invention has been
particularly shown and described with reference to the preferred
embodiments thereof, various changes in form and details, as will
be apparent to those of ordinary skill in the art, may be made
thereto without departing from the true spirit and scope of the
invention as defined by the appended claims.
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