U.S. patent application number 10/743079 was filed with the patent office on 2004-09-09 for input/output architecture for integrated circuits with efficeint positioning of integrated circuit elements.
Invention is credited to Ko, Uming.
Application Number | 20040174646 10/743079 |
Document ID | / |
Family ID | 26871383 |
Filed Date | 2004-09-09 |
United States Patent
Application |
20040174646 |
Kind Code |
A1 |
Ko, Uming |
September 9, 2004 |
Input/output architecture for integrated circuits with efficeint
positioning of integrated circuit elements
Abstract
A described embodiment of the present invention includes an
integrated circuit having a plurality of I/O modules. The I/O
modules include a bond pad formed on a substrate. The I/O modules
also include an electrostatic discharge device formed in the
substrate. The electrostatic discharge device is at least partially
formed beneath the bond pad. The I/O module also includes an I/O
buffer formed in the substrate. The I/O buffer is connected to the
bond pad. The I/O buffer provides communication between the bond
pad and circuitry formed in the substrate. The circuitry is
positioned substantially adjacent to both the electrostatic
discharge device and the I/O buffer.
Inventors: |
Ko, Uming; (Plano,
TX) |
Correspondence
Address: |
Texas Instruments Incorporated
M/S 3999
P.O. Box 655474
Dallas
TX
75265
US
|
Family ID: |
26871383 |
Appl. No.: |
10/743079 |
Filed: |
December 23, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10743079 |
Dec 23, 2003 |
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09723563 |
Nov 28, 2000 |
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60175613 |
Jan 11, 2000 |
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Current U.S.
Class: |
361/56 |
Current CPC
Class: |
H01L 27/0203 20130101;
H01L 27/0248 20130101 |
Class at
Publication: |
361/056 |
International
Class: |
H02H 009/00 |
Claims
Having thus described my invention, what I claim as new and desire
to secure by Letters Patent is set forth in the following
claims.
1. An integrated circuit having a plurality of I/O modules
comprising: a bond pad formed on a substrate; an electrostatic
discharge device formed in the substrate, the electrostatic
discharge device being at least partially formed beneath the bond
pad; an I/O buffer formed in the substrate and connected to the
bond pad, the I/O buffer providing communication between the bond
pad and circuitry formed in the substrate, wherein the circuitry is
positioned substantially adjacent to both the electrostatic
discharge device and the I/O buffer.
2. The integrated circuit of claim 1 wherein the substrate is a
silicon substrate.
3. The integrated circuit of claim 1 wherein the I/O buffer is an
output buffer.
4. The integrated circuit of claim 1 wherein the I/O buffer is an
input buffer.
5. The integrated circuit of claim 1 wherein the I/O buffer is a
complementary output buffer.
6. The integrated circuit of claim 1 wherein the circuitry is CMOS
circuitry.
7. The integrated circuit of claim 1 wherein the circuitry is
BiCMOS circuitry.
8. The integrated circuit of claim 1 wherein the circuitry is an
application specific integrated circuit.
9. The integrated circuit of claim 1 wherein the circuitry is
digital signal processor.
10. The integrated circuit of claim 1 wherein the entire surface of
the substrate beneath the bond pad is occupied by the electrostatic
discharge device.
11. An integrated circuit comprising: a functional core formed on a
substrate, the functional core being positioned centrally on the
substrate; and an I/O region positioned at the periphery of the
functional core, the I/O region including a plurality of I/O
modules, the I/O modules including: a bond pad formed on a
substrate; an electrostatic discharge device; and an I/O buffer
wherein the I/O buffer is not positioned between the bond pad and
the functional core.
12. The integrated circuit of claim 11 wherein the substrate is a
silicon substrate.
13. The integrated circuit of claim 11 wherein the I/O buffer is an
output buffer.
14. The integrated circuit of claim 11 wherein the I/O buffer is an
input buffer.
15. The integrated circuit of claim 11 wherein the I/O buffer is a
complementary output buffer.
16. The integrated circuit of claim 11 wherein the functional core
is CMOS circuitry.
17. The integrated circuit of claim 11 wherein the functional core
is BiCMOS circuitry.
18. The integrated circuit of claim 11 wherein the functional core
is an application specific integrated circuit.
19. The integrated circuit of claim 11 wherein the functional core
is digital signal processor.
20. The integrated circuit of claim 11 wherein the entire surface
of the substrate beneath the bond pad is occupied by the
electrostatic discharge device.
21. An integrated circuit comprising: a functional core formed on a
substrate, the functional core including a plurality of integrated
circuit elements and being positioned centrally on the substrate;
and an I/O region positioned at the periphery of the functional
core, the I/O region including a plurality of I/O modules, the I/O
modules including: a bond pad formed on a substrate, the bond pad
including a conductive surface for providing electrical connection
to external devices; an electrostatic discharge device formed
beneath the bond pad; and a CMOS I/O buffer wherein the I/O buffer
is not positioned between the bond pad and the functional core.
22. A method for forming an integrated circuit having a plurality
of I/O modules comprising: forming a bond pad formed on a
substrate; forming an electrostatic discharge device formed in the
substrate, the electrostatic discharge device being at least
partially formed beneath the bond pad; and forming an I/O buffer
formed in the substrate and connected to the bond pad, the I/O
buffer providing communication between the bond pad and circuitry
formed in the substrate, wherein the circuitry is positioned
substantially adjacent to both the electrostatic discharge device
and the I/O buffer.
23. The method of claim 22 wherein the substrate is a silicon
substrate.
24. The method of claim 22 wherein the I/O buffer is an output
buffer.
25. The method of claim 22 wherein the I/O buffer is an input
buffer.
26. The method of claim 22 wherein the I/O buffer is a
complementary output buffer.
27. The method of claim 22 wherein the circuitry is CMOS
circuitry.
28. The method of claim 22 wherein the circuitry is BiCMOS
circuitry.
29. The method of claim 22 wherein the circuitry is an application
specific integrated circuit.
30. The method of claim 22 wherein the circuitry is digital signal
processor.
31. The method of claim 22 wherein the entire surface of the
substrate beneath the bond pad is occupied by the electrostatic
discharge device.
32. A method for forming an integrated circuit comprising:
providing a functional core formed on a substrate, the functional
core being positioned centrally on the substrate; and in an I/O
region positioned at the periphery of the functional core, forming
a plurality of I/O modules, the steps for forming the I/O modules
including: forming a bond pad formed on a substrate; forming an
electrostatic discharge device; and forming an I/O buffer wherein
the I/O buffer is not positioned between the bond pad and the
functional core.
33. The method of claim 32 wherein the substrate is a silicon
substrate.
34. The method of claim 32 wherein the I/O buffer is an output
buffer.
35. The method of claim 32 wherein the I/O buffer is an input
buffer.
36. The method of claim 32 wherein the I/O buffer is a
complementary output buffer.
37. The method of claim 32 wherein the functional core is CMOS
circuitry.
38. The method of claim 32 wherein the functional core is BiCMOS
circuitry.
39. The method of claim 32 wherein the functional core is an
application specific integrated circuit.
40. The method of claim 32 wherein the functional core is digital
signal processor.
41. The method of claim 32 wherein the entire surface of the
substrate beneath the bond pad is occupied by the electrostatic
discharge device.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field
[0002] The present invention relates to the field of integrated
circuit layout and design. More specifically, the present invention
relates to a design process and structure for providing
input/output components on an integrated circuit.
[0003] 2. Description of the Related Art
[0004] The development of the technology for the fabrication and
design of integrated circuits has allowed designers to place ever
increasing functionality onto a smaller area of integrated
circuits. This makes the surface area of an integrated circuit
extremely valuable. A component of integrated circuits that
occupies a relatively large area are the input/output (I/O)
modules.
[0005] I/O Modules provide the attachment point for electrical
bonding to the integrated circuit die. I/O modules generally
consist of a bond pad, an electrostatic discharge protection device
and I/O buffer circuitry. The core circuitry is generally composed
of very small devices. These devices are fast and densely packed,
but fragile. The I/O modules provide protection to the core
circuitry as well as a connection point for getting signals on and
off of the integrated circuit. Because they must provide this
protection function, I/O modules use relatively large devices and
occupy a disproportionate area on the integrated circuit die.
[0006] I/O modules are generally positioned on the periphery of the
integrated circuit die. This makes the process of bonding to the
bond pads easier and helps buffer the core circuitry from the
physical stresses of cutting the die from the semiconductor wafer
during manufacturing. The area occupied by the I/O modules is
determined by the height (distance from the edge of the die to
interior edge of the I/O modules) of the I/O modules. The remaining
portion of the chip is available for core circuitry. Designers are
always looking for ways to put more functionality onto an
integrated circuit. Because of this, it is desirable to use the
minimum area necessary for I/O modules to provide as much area as
possible for the core circuitry.
BRIEF SUMMARY OF THE INVENTION
[0007] It is an object of the present invention to provide a
structure and method allowing the positioning of integrated circuit
elements efficiently.
[0008] It is a further object of the present invention to minimize
the area necessary for the I/O periphery in an integrated
circuit.
[0009] These and other objects are provided by a described
embodiment of the present invention, which includes an integrated
circuit having a plurality of I/O modules. The I/O modules include
a bond pad formed on a substrate. The I/O modules also include an
electrostatic discharge device formed in the substrate. The
electrostatic discharge device is at least partially formed beneath
the bond pad. The I/O module also includes an I/O buffer formed in
the substrate. The I/O buffer is connected to the bond pad. The I/O
buffer provides communication between the bond pad and circuitry
formed in the substrate. The circuitry is positioned substantially
adjacent to both the electrostatic discharge device and the I/O
buffer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] For a more complete understanding of the present invention
and the advantages thereof, reference should be made to the
following Detailed Description taken in connection with the
accompanying drawings in which:
[0011] FIG. 1 is a layout diagram of a prior art I/O module;
[0012] FIG. 2 is a layout diagram of the I/O module of FIG. 1
positioned on an integrated circuit die;
[0013] FIG. 3 is a layout diagram showing a plurality of prior art
I/O modules positioned next to a functional core;
[0014] FIG. 4 is a layout diagram of an embodiment of the present
invention;
[0015] FIG. 5 is a layout diagram another embodiment of the present
invention in which a plurality of I/O modules positioned by a
functional core;
[0016] FIG. 6 is a chart showing the die area recovered using the
described embodiments of the present invention;
[0017] FIG. 7 is a detailed layout diagram of the embodiment of
FIG. 4;
[0018] FIG. 8 is a schematic diagram of an output circuit suitable
for used with the described embodiments of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0019] FIG. 1 is a layout diagram of a prior art I/O module. I/O
module 10 includes a bond pad 12, electrostatic discharge (ESD)
device 14 and I/O buffer 16. Also included in FIG. 1 are scribe
area 20 and scribe seal 22. Scribe area 20 provides space for the
saw that separates a wafer into die. Scribe seal 22 is a physical
buffer area between the dice and the scribe area. Scribe seal
allows for the dissipation of physical stress during the dicing
process.
[0020] The components of I/O module 10 are laid out in the
conventional manner with the bond pad and the edge of the
integrated circuit die and the I/O buffer 16 positioned between the
functional core 40 and bond pad 12. I/O module 10 is an advanced
module in that ESD device 14 is positioned beside bond pad 12.
[0021] FIG. 2 is a layout diagram showing the position of I/O
modules 10 on die 30 in I/O region 32. Functional core 40 is
surrounded by I/O region 32. The overall size of the die 30 is
determined by the width of core 40 (X) plus twice the height of the
I/O modules 10 times the length of core 40 (Y) plus twice the
height of the 1,0 modules 10. The formula for the area is
Area=(X+2H)*(Y+2H)
[0022] which can be written as
Area=XY+2HY+2HX+4H.sup.2.
[0023] As can be seen from the above formula, the height of the I/O
modules 10 has a large impact on the overall area of the die 30.
Although FIG. 2 includes fourteen I/O modules 10, it is more common
for an integrated circuit to include from 64 to 300 I/O modules.
FIG. 3 is an enlarged portion of the layout of FIG. 2 showing four
I/O modules 10 and their position relative to functional core
40.
[0024] FIG. 4 is a layout diagram of a novel I/O module 100, which
is structured according to the teachings of the present invention.
I/O module 100 is preferably formed on a crystalline semiconductor
substrate. Bond pad 112 is positioned adjacent to scribe seal 122
as in the I/O module 10 of FIG. 1. Bond pad 112 is preferably
formed of an aluminum composite layer, copper layer or gold clad
copper layer having conductive upper surface for ball bonding. I/O
buffer 116 is a similar I/O buffer circuit with a similar layout to
that of I/O buffer 16. However, because I/O buffer 116 is
positioned adjacent to scribe seal 122, the overall height Z of I/O
module 100 is the height of I/O buffer 116 plus the width of scribe
seal 122 and one half of scribe line 120.
[0025] In contrast, the height H of prior art I/O Module is height
of I/O buffer 16 plus the height of ESD device 14 plus the width of
scribe seal 22 and one half of scribe line 20. For example, the
height of I/O buffer 16 may be 71.mu., the height of ESD device 14
may be 21.mu., the height of bond pad 12 may be 50.mu. and the
combined height of the scribe seal 22, scribe line 20 and
additional spacing may be 46.mu.. This provides an overall height H
of 188.mu..
[0026] The inventive I/O module 100, however, provides a much
smaller height Z using the same design rules. With the same
dimensions for components of I/O module 10, I/O module 100 has a
height of 81.mu. for I/O module 116 plus 46.mu. for scribe line 120
and scribe seal 122. By careful layout of I/O module 116, its
height can be reduced to 74.mu., thus providing an overall height Z
of 120.mu..
[0027] FIG. 5 shows I/O modules 100 as positioned adjacent to
functional core 40. Functional core 40 may be any function capable
of being implemented with integrated circuitry. For example,
functional core 40 may comprise an application specific integrated
circuit or a digital signal processor. Preferably, the circuitry of
functional core 40 is fabricated using CMOS or BiCMOS processes.
Because I/O modules 100 are wider than corresponding prior art
modules, fewer I/O modules 100 can be provided for a given size of
functional core 40. However, integrated circuit designs are rarely
constrained by the number of I/O buffers. More often, the number of
input/output connections is limited by the package. Packages that
provide more that 200 connection points (for advanced ball grid
arrays) can be cost prohibitive. Therefore, I/O modules 100
significantly reduce the die size for a given functionality without
constraining the operational characteristics of the integrated
circuit. Conversely, I/O modules 100 allow for a larger functional
core for a given die size.
[0028] FIG. 6 is a chart comparing the die size and wasted area
using the prior art I/O module. Six functional core sizes are
listed. For each core size, a prior art I/O module with height H is
listed and a corresponding novel module with the height Z is
listed. Also listed is the total area using each module, the
maximum number of I/O modules that can be placed on the die, the
wasted area and the percentage of area wasted using the prior art.
As can be seen from FIG. 6, the novel I/O module 100 reduces wasted
space by 6%-13%, depending on functional core size.
[0029] FIG. 7 is a layout diagram showing the specific
topographical features of I/O module 100. ESD device 114 can be any
number of electrostatic discharge devices. Examples of suitable
devices can be found in Chen et al., U.S. Pat. No. 5,982,217, which
is assigned to the assignee of this application and which is
incorporated herein by reference.
[0030] I/O buffer 116 can be any number of known designs for
providing input and output drivers. An example is shown in FIG. 8.
I/O buffer 116 is preferably fabricated using a multi-level metal
system and a device fabrication process such as that shown in
Smayling et al., U.S. Pat. No. 5,767,551, which is assigned to the
assignee of this application and which is hereby incorporated by
reference. I/O buffer 116 is a three stage, complementary output
buffer designed for high speed and to provide a well conditioned
output signal.
[0031] The input signal on input A of I/O buffer 116 is inverted by
transistor 202 and a push-pull inverter formed by transistors 204
and 206. Transistor 208 prevents saturation of transistor 206 for
high speed operation. The output from transistors 204 and 206 is
inverted again by transistors 210 and 212 with a pull up (when
appropriate) from transistor 214. The drain of transistor 214 is
connected to the high VDD voltage supply (symbolized by a circle).
The output from transistors 204 and 206 also drives the push-pull
inverter formed by transistors 216 and 218. The output from
transistors 210 and 212 drives the gate of drive transistor 220.
The output from transistors 216 and 218 drives the gate of drive
transistor 222. The output from transistors 210 and 212 also drives
the gate of pull-up transistor 224.
[0032] The inverse of input A, A' is applied to the gates of
transistors 226, 228 and 230. Transistors 226, 228, 230, 232, 234,
236, 238, 240, 242 and 244 provide the same functions as
transistors 202, 204, 206, 208, 214, 210, 212, 216, 218, and 224,
respectively. Additionally, transistors 245 and 248 invert and
delay the output of transistors 236 and 238. In addition,
transistors 250 and 252 invert and delay the output of transistors
240 and 242. The output of transistors 236 and 238 drives the gate
of output transistor 254. The output of transistors 250 and 252 are
used to drive the gate of output transistor 256.
[0033] Transistors 258, 260, 262, 264 and 266 constitute a pull
down AND gate driving output transistor 278. Transistors 268, 270,
272, 274 and 276 constitute a pull-down AND gate driving output
transistor 280. The pull-down portions of the gates are voltage
limited by transistors 262 and 272 in that are gate strapped to VDD
(the lower voltage supply symbolized by a horizontal line). This
prevents saturation of transistors 278 and 280. The parallel
pull-up transistors 258, 260, 268 and 270 provide rapid shut off of
transistors 278 and 280. The gate inputs of transistors 258-270 are
timed to provide staggered gate charging or draining capacity and
to avoid race conditions where all transistors in a series are
on.
[0034] Transistors 282-290 provide a complementary pull-up function
for output transistors 298 and 300 to the function provided by
transistors 258-270 for output transistors 278 and 280. In summary,
transistors 220, 222, 254 and 256 provide rapid medium drive
signals to begin and signal transition. Transistors 278, 280, 298
and 300 provide high capacity drive with gate drive signals that
are carefully controlled. I/O buffer 116 in FIG. 8 is an output
buffer of a certain preferred structure. However, the structure of
FIG. 8 in no way limits the intended scope of the invention. The
invention contemplates the use of any input or output buffer.
[0035] Although specific embodiments of the present invention are
described herein, they are not to be construed as limiting the
scope of the invention. For example, although specific circuits and
device fabrication techniques are described and referred to herein,
many specific devices and fabrication techniques may be
advantageously used within the scope of the invention. Many
embodiments of the invention will become apparent to those skilled
in the art in light of the teachings of this specification. The
scope of the invention is only limited by the claims appended
hereto.
* * * * *