U.S. patent application number 10/653596 was filed with the patent office on 2004-05-06 for etching method and etching signal layer for processing semiconductor wafers.
Invention is credited to Birner, Albert, Gutsche, Martin, Hecht, Thomas, Jakschik, Stefan, Kudelka, Stephan, Schroeder, Uwe, Seidl, Harald.
Application Number | 20040087045 10/653596 |
Document ID | / |
Family ID | 31197537 |
Filed Date | 2004-05-06 |
United States Patent
Application |
20040087045 |
Kind Code |
A1 |
Hecht, Thomas ; et
al. |
May 6, 2004 |
Etching method and etching signal layer for processing
semiconductor wafers
Abstract
An etching signal layer which is formed by a sequential gas
phase deposition with a layer thickness of less than 20 nanometers,
and which is composed of a metal oxide or of an oxide of rare
earths is provided between a substrate, which is located underneath
it, and a process layer. The etching signal layer produces an
etching signal, which is independent of the stack layer systems
that are to be removed, and contains two or more materials that
contain silicon, and can be removed quickly and with narrow process
tolerances. One substrate surface of the substrate is protected
irrespective of the topography. Etching methods based on the
etching signal layer can be carried out precisely, and can be used
in a variable manner.
Inventors: |
Hecht, Thomas; (Dresden,
DE) ; Schroeder, Uwe; (Dresden, DE) ; Seidl,
Harald; (Feldkirchen, DE) ; Gutsche, Martin;
(Dorfen, DE) ; Jakschik, Stefan; (Dresden, DE)
; Kudelka, Stephan; (Ottendorf-Okrilla, DE) ;
Birner, Albert; (Dresden, DE) |
Correspondence
Address: |
LERNER AND GREENBERG, P.A.
POST OFFICE BOX 2480
HOLLYWOOD
FL
33022-2480
US
|
Family ID: |
31197537 |
Appl. No.: |
10/653596 |
Filed: |
September 2, 2003 |
Current U.S.
Class: |
438/9 ;
257/E21.2; 257/E21.256; 257/E21.274; 257/E21.281; 257/E21.576;
257/E21.664; 257/E27.104; 257/E29.042; 257/E29.157; 428/446;
438/706 |
Current CPC
Class: |
H01L 21/76828 20130101;
H01L 21/76832 20130101; H01L 29/4941 20130101; H01L 21/76831
20130101; H01L 21/02178 20130101; H01L 21/28061 20130101; H01L
21/31138 20130101; H01L 27/11502 20130101; H01L 21/31604 20130101;
H01L 28/57 20130101; H01L 29/0895 20130101; H01L 21/3162 20130101;
H01L 21/76829 20130101; H01L 27/11507 20130101; H01L 21/76802
20130101; H01L 21/02181 20130101 |
Class at
Publication: |
438/009 ;
428/446; 438/706 |
International
Class: |
H01L 021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 30, 2002 |
DE |
102 40 106.3 |
Claims
We claim:
1. An etching method for removing material in a course of
processing semiconductor wafers, which comprises the steps of:
providing a semiconductor wafer as a substrate; performing one of a
sequential gas phase deposition process and a molecular beam
epitaxy process for producing an etching signal layer at least on
sections of one substrate surface of the substrate, the etching
signal layer being a dielectric layer composed of a material
selected from the group consisting of metal oxides and oxides of
rare earths; providing a process layer at least on sections of the
etching signal layer; removing at least sections of the process
layer in a course of an etching process; producing an etching
signal upon exposure of sections of the etching signal layer
disposed underneath removed sections of the process layer and
resulting in exposed sections; and ending the etching process in
dependence on the etching signal.
2. The etching method according to claim 1, which further comprises
forming the etching signal layer from a material selected from the
group consisting of HfO.sub.2, ZrO.sub.2, Ta.sub.2O.sub.5,
Al.sub.2O.sub.3, Pr.sub.2O.sub.5, La.sub.2O.sub.3 and
Nb.sub.2O.sub.5.
3. The etching method according to claim 1, which further comprises
forming the etching signal layer with a layer thickness which
allows significant charge carrier transport, based on a
quantum-mechanical tunnel effect, through the etching signal
layer.
4. The etching method according to claim 1, which further comprises
depositing the etching signal layer with a layer thickness of less
than 20 nanometers.
5. The etching method according to claim 1, which further
comprises: forming the etching signal layer from a material having
a signal element not contained in the process layer; observing
spectroscopically a process surface formed as a function of
progress of the etching process on the process layer and on the
etching signal layer; and producing the etching signal on
spectroscopic detection of the signal element.
6. The etching method according to claim 1, which further
comprises: recording an etching rate of the etching process
continuously during the etching process; and producing the etching
signal if there is any significant change in the etching rate.
7. The etching method according to claim 1, which further comprises
stopping the etching process on detection of the etching
signal.
8. The etching method according to claim 1, which further comprises
ending the etching process after a given run-on time, with the
given run-on time being of such a duration that the etching signal
layer is completely removed in the exposed sections during the
given run-on time.
9. The etching method according to claim 1, which further comprises
ending the etching process once a given run-on time has
elapsed.
10. The etching method according to claim 9, which further
comprises setting a duration of given run-on time such that, during
the given run-on time, the substrate is removed in sections which
are disposed underneath the exposed sections as far as a depth
which is actually required for use.
11. The etching method according to claim 9, which further
comprises: applying a first process layer element at least to
sections of the etching signal layer before the etching signal
layer is produced on the substrate surface; applying a second
process layer element at least to sections of the etching signal
layer after provision of the etching signal layer; and setting the
duration of the given run-on time such that, during the given
run-on time, the second process layer element is completely removed
in the sections which are disposed underneath the exposed
sections.
12. The etching method according to claim 1, which further
comprises varying parameters for the etching process in dependence
on a registration of the etching signal.
13. The etching method according to claim 1, which further
comprises forming the process layer from at least two stack
layers.
14. The etching method according to claim 13, which further
comprises forming at least one of the stack layers with a secondary
structure having at least two stack layer sections composed of
different materials.
15. The etching method according to claim 13, which further
comprises: forming at least a first one of the stack layers in
places or completely from silicon; forming a second one of the
stack layers in places or completely from silicon oxide; and
forming a third one of said stack layers in places or completely
from silicon nitride.
16. The etching method according to claim 1, which further
comprises structuring the substrate with trenches and webs defining
a relief, the structuring being performed on a basis of a basic
structure.
17. The etching method according to claim 14, which further
comprises: providing a mask, structured on a basis of a primary
structure, on the process layer; and transferring the primary
structure at least into the process layer by the etching
process.
18. The etching method according to claim 17, which further
comprises forming the secondary structure to be different than the
primary structure.
19. The etching method according to claim 16, which further
comprises: defining a substrate edge by an upper edge of one of the
webs which is highest with respect to the substrate surface;
carrying out the etching process as a chemical-mechanical polishing
method; and removing sections of the process layer disposed above
the substrate edge in a course of the etching process.
20. The etching method according to claim 19, which further
comprises providing the etching signal layer in a structured
manner.
21. The etching method according to claim 20, which further
comprises forming the etching signal layer to have at least two
molecular individual layers using the sequential gas phase
deposition process, with a deposition of each individual layer
being controlled in a direction from the substrate edge into a
depth of the relief, and the etching signal layer being produced in
a vertically structured manner by ending the deposition of each
individual layer before complete coverage.
22. The etching method according to claim 1, which further
comprises compressing the etching signal layer by performing a
heating process.
23. An etching signal layer, comprising: a layer system containing
at least two monomolecular individual layers with a layer thickness
for which significant charge carrier transport, based on a
quantum-mechanical tunnel effect, through the etching signal layer
being possible, said layer system formed of an oxide selected from
the group consisting of metal oxides and oxides of rare earths,
said layer system formed by one of a sequential gas phase
deposition and molecular beam epitaxy.
24. The etching signal layer according to claim 23, wherein said
layer system has a layer thickness of less than 20 nanometers.
Description
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
[0001] The invention relates to an etching method for removing
material in the course of processing semiconductor wafers. The
method includes providing a semiconductor wafer as a substrate,
providing an etching signal layer at least on sections of one
substrate surface of the substrate, providing a process layer at
least on sections of the etching signal layer, and removing at
least sections of the process layer in the course of an etching
process. An etching signal is produced upon an exposure of sections
of the etching signal layer that are located underneath the removed
sections of the process layer. The etching process is ended as a
function of the etching signal.
[0002] The invention also relates to an etching signal layer.
[0003] The processing of semiconductor wafers generally includes
two or more process steps with etching processes, by which either
layers are removed over the entire surface, or mask patterns that
are produced lithographically are transferred to layers or
structures located underneath them.
[0004] In wet-chemical etching processes, solid materials are
dissolved in a chemical solution. In chemical-mechanical polishing
processes (CMP), wet-chemical etching is assisted by the mechanical
influence of a polishing agent on the layer or structure to be
removed. In dry chemical etching processes, the material to be
removed reacts with components of an etching gas, forming volatile
reaction products. In the course of physical dry etching processes,
the material to be removed is subjected to a particle beam, under
the influence of which the material to be removed is vaporized, and
individual atoms are detached from the layer or structure to be
removed. For reactive ion etching (reactive ion beam etching, RIE),
ions are accelerated in the direction of the material to be
removed, and initiate a chemical etching process when they strike
it.
[0005] Isotropic etching processes, for example wet-chemical
etching, remove material independently of the direction while
anisotropic etching processes such as RIE and CMP in contrast
remove the material in a preferred direction.
[0006] The etching processes generally stop at etching stop layers.
The etching stop layers are in each case provided from a material
which does not recede as a result of the respectively used etching
process, or which recedes at an etching rate which is very slow in
comparison with that of the material to be removed.
[0007] It is also normal to use measurement techniques to detect an
etching end point by use of an etching stop signal layer. In the
case of dry etching processes by way of example, the process
surface which has been etched back by the etching process is for
this purpose evaluated spectroscopically, or, in the case of
wet-chemical etching processes, the etching rate is recorded
continuously, and any significant change is evaluated.
[0008] The material of the etching stop layer and/or of the etching
stop signal layer is chosen such that the etching process for the
material to be removed is as selective as possible with respect to
the material of the etching stop layer and of the etching stop
signal layer. Admittedly, silicon, silicon oxide (SiO.sub.2) and
silicon nitride (Si.sub.3N.sub.4) and silicides can in principle be
etched selectively. If materials containing silicon are provided as
etching stop layers with respect to one another, then the etching
stop layers are also attacked by the etching process and must be
provided with a sufficient layer thickness in order to reliably
prevent the etching process from penetrating into the material
which is located under the etching stop layer. If silicon nitride
is used as the etching stop layer or etching stop signal layer when
removing silicon oxide or silicon, then the silicon nitride layer
must be provided with a thickness of several tens of nanometers. In
order to assist in the removal of the etching stop layer itself, a
further barrier layer is then required between the etching stop
layer and the substrate, for example silicon oxide, which is
located underneath it, in order to protect the substrate which is
located underneath during removal of the etching stop layer.
[0009] U.S. Pat. No. 6,593,633 discloses a method for producing a
semiconductor device, in the course of which a silicon carbide
layer (SiC) is deposited in a plasma-enhanced gas phase deposition
method (plasma-enhanced chemical vapor deposition, PECVD) and an
etching stop layer that remains in places is in consequence
provided. After being used as an etching stop layer, the silicon
carbide layer remains in places as an isolator layer with low
permittivity between two semiconductor device structures that need
to be decoupled.
[0010] U.S. Pat. No. 6,518,671 (Yang et al.) names tantalum oxide
(Ta.sub.2O.sub.5) and aluminum oxide (Al.sub.2O.sub.3) as materials
for the etching stop layers. The layer thickness of the etching
stop layer is 20 to 70 nanometers. The etching stop layer is
applied to a planar surface and is structured
photolithographically. The etching stop layer limits material
removal in an anisotropic chemical-physical dry etching
process.
SUMMARY OF THE INVENTION
[0011] It is accordingly an object of the invention to provide an
etching method and an etching signal layer for processing
semiconductor wafers that overcomes the above-mentioned
disadvantages of the prior art devices of this general type, in
which two or more materials which contain silicon can be removed in
a single etching process, irrespective of the etching process that
is used and irrespective of the surface structure of a layer or
structure which is located underneath and needs to be protected
against removal.
[0012] With the foregoing and other objects in view there is
provided, in accordance with the invention, an etching method for
removing material in a course of processing semiconductor wafers.
The method includes providing a semiconductor wafer as a substrate
and performing a sequential gas phase deposition process or a
molecular beam epitaxy process for producing an etching signal
layer at least on sections of one substrate surface of the
substrate. The etching signal layer is a dielectric layer composed
of a metal oxide or an oxide of rare earths. A process layer is
provided at least on sections of the etching signal layer. At least
sections of the process layer are removed in a course of an etching
process. An etching signal is produced upon exposure of sections of
the etching signal layer disposed underneath removed sections of
the process layer and results in exposed sections. The etching
process is ended in dependence on the etching signal.
[0013] In the course of the etching method according to the
invention for removal of material in the course of processing
semiconductor wafers, a semiconductor wafer is first provided as
the substrate. At this time, the semiconductor wafer is typically
already structured with different materials. An etching signal
layer is provided at least in places on one substrate surface of
the substrate. A process layer is provided at least in places on
the etching signal layer. The process layer is either integral and
homogeneous, or is an unstructured or intrinsically structured
layer system. In the course of an etching process, the process
layer is removed completely or in places. If, by way of example,
the process layer is produced by a deposition process, in the
course of which trench structures that extend into the substrate
are filled, then the process layer is removed completely above the
etching signal layer. If a primary structure of an etching mask is
mapped into the process layer, by a photolithographic process, then
the process layer is removed only in places above the etching
signal layer. An etching signal is produced during or after the
exposure of sections of the etching signal layer that are located
under those sections of the process layer which are to be removed.
The etching process is ended as a function of the etching signal.
The etching signal can be evaluated by an etching or polishing
apparatus.
[0014] According to the invention, the etching signal layer is
provided by a sequential gas phase deposition (atomic layer
deposition (ALD)) or molecular beam epitaxy as a dielectric layer
composed of a metal oxide, including oxides of rare earths.
[0015] Metal oxides and oxides of rare earths can be etched in one
step with high etching selectivity with respect to all normal
materials that contain silicon in semiconductor process technology,
such as crystalline silicon, amorphous silicon, silicon dioxide and
silicon nitride. Sequential gas phase deposition can be used to
produce the etching signal layer even on structured substrates with
a uniform layer thickness and with good edge coverage. Layers
deposited by sequential gas phase deposition and composed of metal
oxide or oxides of rare earths are on the one hand robust against
normal chemical etching methods, but on the other hand can
effectively be pulverized and removed in a simple manner by
mechanical processes, for example by particle bombardment,
particularly when the layers are very thin.
[0016] The etching method according to the invention allows not
only standardization of the etching processes which are required in
the course of processing the semiconductor wafers, but also makes
it very simple to remove etching signal layers which are used only
temporarily.
[0017] The etching signal layer is preferably provided with a layer
thickness for which charge carrier transport based on the
quantum-mechanical tunnel effect through the etching signal layer
is still possible to a significant extent. Charge carrier transport
to a significant extent may be assumed to be current densities of
more than 10.sup.-5 A/cm.sup.2 for isolating applications and more
than 10.sup.-2 A/cm.sup.2 for conductive applications, depending on
the purpose and the material that is used.
[0018] In conjunction with the application of the etching signal
layer by sequential gas phase deposition, as a consequence of which
the etching signal layer has a virtually uniform layer thickness
over its entire extent, remanent sections of the etching signal
layer may also be disposed between semiconductor wafer structures
that have to be conductively connected to one another. Therefore,
for certain applications, for example when forming vertical
connecting structures (plugs), there is no need to remove the
etching signal layer.
[0019] The etching signal layer is provided in a particularly
advantageous manner with a layer thickness of less than 20
nanometers. This results in the electrical contact resistance
between conductive structures being increased to a comparatively
minor extent. Furthermore, an etching signal layer is removed
quickly and easily in comparison to conventional etching stop
layers, for example silicon nitride layers. There is no need to
provide a further barrier layer underneath the etching stop layer,
to protect the substrate that is located underneath against removal
of the etching stop layer. Suitable metal oxides for forming the
etching signal layer are, for example, HfO.sub.2, ZrO.sub.2,
Nb.sub.2O.sub.5, Ta.sub.2O.sub.5 and Al.sub.2O.sub.3. Suitable
oxides of rare earths are, for example, Pr.sub.2O.sub.5 and
La.sub.2O.sub.3.
[0020] The etching signal layer is preferably formed from a
material that has a signal element that is not contained in the
process layer, for example a metal. A process surface which is in
each case actually subjected to the etching process (wet-chemical,
RIE, CMP) and which is formed as a function of the progress of the
etching process of the process layer and/or of the etching signal
layer is observed and evaluated spectroscopically. The etching
signal is produced when the signal element is detected
spectroscopically. The etching signal is thus produced in a simple
manner, and precisely synchronized to the progress of the etching
process.
[0021] According to another preferred embodiment of the etching
method according to the invention, an etching rate of the etching
process is recorded continuously, for example during CMP processes,
and an etching signal is produced when a significant change,
normally a significant reduction, occurs in the etching rate.
[0022] The etching process, irrespective of whether this is a
wet-chemical process, RIE or CMP, can be ended at the same time as
the etching signal or with a slight run-on, so that the etching
process stops on the surface of the etching signal layer. However,
it is particularly advantageous for the etching process to be ended
after a first run-on time, which is of such duration that the
etching signal layer in the exposed sections is actually completely
removed during the first run-on time. This is in fact possible
because the etching signal layer has a virtually uniform and very
thin layer thickness since it is produced by sequential gas phase
deposition. The timing for the removal of the etching signal layer
with respect to the previous etching signal can be controlled with
very narrow tolerances, so that the substrate which is located
underneath it is not damaged in the process.
[0023] As an alternative to this, the etching process is ended
after a second run-on time has elapsed. The second run-on time is
then of such a duration that the substrate which is located
underneath the etching signal layer is removed during the second
run-on time as far as the depth which is required for the purpose,
in sections which are located underneath the exposed sections of
the etching signal layer. This type of processing, for example in
conjunction with RIE and CMP processes, results in relatively
narrow manufacturing tolerances, since the etching signal layer is
itself removed within narrow tolerances, owing to its thin layer
thickness and high conformity.
[0024] It is also advantageous to apply a first process layer
element at least to sections of the etching signal layer before the
provision of the etching signal layer on the substrate, and to
apply a second process layer element at least to sections of the
etching signal layer after the provision of the etching signal
layer. The second run-on time may then be of such a duration that,
during the second run-on time, the second process layer element is
actually completely removed in the sections that are located
underneath the exposed sections of the etching signal layer.
[0025] In this case, the etching signal that is produced by the
etching signal layer is used for fine adjustment of an etching
process that acts on the entire process layer formed by the two
process layer elements.
[0026] In certain cases, adaptation of parameters of the etching
process as a function of detection of the etching signal is
advantageous for the various variants mentioned.
[0027] The etching method according to the invention is
particularly advantageous when the process layer is formed from
more than one stack layer, in which case at least one of the stack
layers may be provided with a secondary structure having two or
more stack sections composed of different materials. Layer systems
such as these, which are structured jointly at least in places, and
are removed above an etching signal layer, can occur in
semiconductor process technology in conjunction, for example, with
connecting lines which cross in different levels, but not only in
this case.
[0028] The advantages of the etching method according to the
invention are particularly applicable when the substrate is
provided with a relief, which is structured on the basis of a basic
structure, with trenches and webs on the substrate surface. The
etching method according to the invention ensures that the etching
signal layer is provided with a high degree of uniformity, with a
thin layer thickness, homogeneously and with good edge coverage,
even on the structured substrate surface, so that the advantages
mentioned above are also still obtained for structured surfaces, in
contrast to known etching methods.
[0029] The method according to the invention is suitable for
photolithographic methods, in the course of which a primary
structure of a photolithographic mask is mapped by an etching
process into the process layer. A mask which is structured on the
basis of the primary structure is for this purpose provided on the
process layer, and the primary structure is transferred by the
etching process at least into the process layer. In this case, the
secondary structure can be provided independently of the primary
structure, and in a different manner to it.
[0030] Alternatively, the etching process can also be carried out
as a chemical-mechanical polishing method. In this case, sections
of the process layer above a substrate edge that is defined by an
upper edge of a web that is the highest with respect to the
substrate surface are removed in the course of the etching
process.
[0031] In certain cases, the etching signal layer may also be
vertically structured or may be deposited such that it is already
structured in the course of the etching method according to the
invention.
[0032] The etching signal layer is for this purpose provided in a
particularly preferred manner by a sequential gas phase deposition,
in which two or more molecular individual layers are deposited
successively, and in which the deposition process is controlled
such that each individual layer is deposited in the direction from
the substrate edge into the depth of the relief. The process of
depositing each individual layer is ended prematurely before the
respective individual layer completely covers the substrate that is
located underneath it. Therefore, the etching signal layer is
deposited in such a way that it is already vertically structured,
so that there is no need for subsequent vertical structuring, for
example by modification of the etching resistance by oblique
implantation of dopants which influence the etching resistance of
the etching signal layer.
[0033] The etching signal layer is in certain cases compressed and
hardened by a tempering or heat step. In conjunction with the
etching of a process layer composed of material containing silicon,
an aluminum oxide layer with a thickness of about 5 nanometers is
provided which is hardened in a tempering step at 700 to 1,100
degrees Celsius for at least 5 seconds to a maximum duration of
about 10 hours.
[0034] The aluminum produces a unique spectroscopic etching signal.
The aluminum oxide layer which is formed from crystallites of
different crystal structure has chemical/physical characteristics
which are so largely different to silicon and silicon compounds
that silicon, silicon oxide and silicon nitride can be etched back
jointly with high etching selectivity with respect to the etching
signal layer. Aluminum oxide is stable in response to conventional
chemical/physical etching processes, so that layer thicknesses of
less than 20 nanometers and less than 10 nanometers are sufficient
for it to act as an etching signal layer. Aluminum oxide layers of
up to 5 nanometers or 10 nanometers can be effectively pulverized
and can be removed comparatively easily, and in a manner which
protects the substrate, by mechanical processes, just by particle
bombardment. A similar situation applies to hafnium oxide layers
used as etching signal layers.
[0035] The process of carrying out the etching method according to
the invention is associated with the etching signal layer according
to the invention. The etching signal layer according to the
invention is composed of a metal oxide or an oxide of rare earths.
The etching signal layer is produced by sequential gas phase
deposition, or by a molecular beam epitaxial method. The etching
signal layer is provided as a layer system containing two or more
monomolecular individual layers. The layer thickness of the etching
signal layer is characterized in that a significant charge carrier
transport, based on the quantum-mechanical tunnel effect, is still
possible through the etching signal layer. The layer thickness is
preferably less than 20 nm.
[0036] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0037] Although the invention is illustrated and described herein
as embodied in an etching method and an etching signal layer for
processing semiconductor wafers, it is nevertheless not intended to
be limited to the details shown, since various modifications and
structural changes may be made therein without departing from the
spirit of the invention and within the scope and range of
equivalents of the claims.
[0038] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] FIGS. 1A and 1B are diagrammatic, sectional views of a first
exemplary embodiment of an etching method according to the
invention, with an anisotropic etching process that stops on an
etching signal layer;
[0040] FIG. 2 is a sectional view of the exemplary embodiment shown
in FIGS. 1A and 1B, after a first etching run-on duration;
[0041] FIG. 3 is a sectional view of the exemplary embodiment shown
in FIG. 2, after a second etching run-on duration;
[0042] FIGS. 4A and 4B are sectional views of an exemplary
embodiment of the etching method according to the invention, with
fine adjustment of the etching process by use of an etching signal
layer;
[0043] FIGS. 5A and 5B are sectional view of an exemplary
embodiment of the etching method according to the invention, for
removal of multilayer structures;
[0044] FIGS. 6A and 6B are sectional views of an exemplary
embodiment of the etching method according to the invention, with a
chemical-mechanical etching process;
[0045] FIGS. 7A and 7B are sectional views showing an exemplary
embodiment of the etching method according to the invention as
shown in FIGS. 6A and 6B, with a layer system to be removed
composed of different materials;
[0046] FIGS. 8A and 8B are sectional views showing an exemplary
embodiment of the etching method according to the invention with an
isotropic etching process; and
[0047] FIGS. 9A and 9B are sectional views showing an exemplary
embodiment of the method according to the invention with an etching
signal layer which is deposited in a vertically structured
manner.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0048] Referring now to the figures of the drawing in detail and
first, particularly, to FIG. 1A thereof, there is shown a substrate
1. The substrate 1 is composed of monocrystalline silicon, silicon
oxide, silicon nitride, and/or some other material that is normally
used in semiconductor process technology. The substrate 1 is
homogeneous or has structures that are not shown in FIG. 1A or in
the following figures.
[0049] An etching signal layer 2 with a thickness of less than 20
nm is applied to one substrate surface 10 of the substrate 1. The
etching signal layer 2 was produced by sequential gas phase
deposition, and is composed of two or more molecular individual
layers. A process layer 3 is provided on the etching signal layer
2. An etching mask 4, composed of a photoresist material, which has
been structured by a photolithographic process is located on the
process layer 3.
[0050] The structure of the etching mask 4 is transferred by an
etching process to the process layer 3 which is located underneath
it.
[0051] In the example in FIG. 1B, the removal of the material of
the process layer 3 ends at an upper edge of the etching signal
layer 2. Since it is thin, the etching signal layer 2 can be
removed easily and quickly. However, by virtue of its dielectric
character, the etching signal layer 2 may remain underneath a
dielectric structure, which is adjacent in exposed sections, in the
process layer 3 or above a dielectric structure in the substrate 1.
As a result of its conductive characteristics owing to its thin
layer thickness, it may then also remain on the substrate surface
10 if it is provided between two conductive structures that need to
be connected to one another.
[0052] FIG. 2 shows the result of the etching method when the
etching process, possibly in the event of a change to the process
parameters, continues for a predefined time synchronized to the
first occurrence of the etching signal, before it is interrupted.
As a result of the thin, uniform layer thickness, resulting from
the method, of the etching signal layer 2, the etching signal layer
2 is removed uniformly in a comparatively short time during the
run-on time, with narrow tolerances and without any damage to the
substrate surface 10 of the substrate 1. This results in the
structured etching signal layer 2' as shown in FIG. 2.
[0053] The narrow etching tolerances during removal of the etching
signal layer 2 also make it possible, as is shown in FIG. 3, to
etch back the substrate 1 in a second run-on time in a defined
manner in those sections which are located underneath the exposed
sections of the etching signal layer 2 and with narrow tolerances,
by a predetermined run-on dx.
[0054] In contrast to the previous examples, the process layer
element 3 in the exemplary embodiment of the etching method
according to the invention illustrated in FIGS. 4A, 4B is applied
in the form of two process layer elements 31, 32, as is shown in
FIG. 4A. In this case, the second process layer element 32 is
located underneath the etching signal layer 2. The first process
layer element 31 is located on the etching layer signal 2.
Particularly when, for example, the layer thickness of the first
process layer element 31 is not known precisely, or the first
process layer element 31 is intended to be removed comparatively
quickly, the second process layer element 32, or parts of it, can
be removed synchronized to an etching signal that is generated by
the etching signal layer 2. This method is particularly
advantageous in conjunction with chemical-mechanical polishing
methods used as the etching process.
[0055] FIG. 4B shows the process layer elements 31', 32',
structured by the etching process as well as the structured etching
signal layer 2'.
[0056] In comparison to FIGS. 1A, 1B, FIG. 5A shows the process
layer 3 as a layer stack with a first, a second and a third stack
layer 331, 332, 333. In the exemplary embodiment, the second stack
layer 332 is structured and has first and second stack layer
sections 332a, 332b composed of different materials. The material
of the first stack layer is, for example, silicon oxide, and that
of the third stack layer is silicon nitride. The materials of the
first and second stack layer sections 332a, 332b are silicon and
silicon nitride respectively. The second stack layer 332 is
structured on the basis of a secondary structure. An etching mask 4
that is placed on the process layer 3 is structured on the basis of
a primary structure, which is independent of the secondary
structure. The primary structure of the etching mask 4 is mapped by
an etching process, which acts on all the materials of the process
layer 3 that contains silicon independently of the secondary
structure provided in the process layer 3, into the process layer 3
with the assistance of the etching signal layer 2 according to the
invention.
[0057] FIG. 5B shows the result of the structuring of the process
layer, as well as the structured process layer 3' that is produced
in this way.
[0058] The exemplary embodiment illustrated in FIGS. 5A, 5B can be
combined with the exemplary embodiments in FIGS. 2 to 4B.
[0059] FIGS. 6A, 6B relate to a CMP process as the etching process
used according to the invention. Trenches 61 are incorporated in
the substrate 1 and, together with webs 62, structure a substrate
surface 10 of the substrate 1 in the form of a relief. An etching
signal layer 2 is applied to the substrate surface 10 covering the
substrate 1 with a maximum thickness of 20 nm, homogeneously,
uniformly and with good edge coverage. The trenches 61 are filled
during the course of a gas phase deposition process, with the
filling material also being deposited above an upper edge of the
trenches 61, and forming the process layer 3.
[0060] The process layer 3 is removed above the substrate surface
10 in the course of a chemical-mechanical polishing process. On
detection of an etching signal, which is produced by exposed
sections of the etching signal layer 2, the polishing process is
ended. FIG. 6B shows the process layer 3' that has been structured
in this way and is recessed into the trenches 61.
[0061] In comparison to the exemplary embodiment illustrated in
FIGS. 6A, 6B, the exemplary embodiment in FIGS. 7A, 7B shows the
process layer 3 as a layer stack with the first, second and third
stack layers 331, 332, 333.
[0062] FIGS. 8A, 8B shows the etching method according to the
invention in conjunction with an isotropic etching process. FIG. 8A
shows the substrate 1 with the structured surface 10. The etching
signal layer 2 is in the form of a conformal coating on the
substrate 1 in the region of the substrate surface 10. The process
layer 3 with a planar surface is adjacent to the etching signal
layer 2. A structured etching mask 4 is applied to the process
layer 3. The process layer 3 is structured in accordance with the
structure of the etching mask 4, using an etching process with an
isotropic component. The result is illustrated in FIG. 8B. The
conformal configuration of the etching signal layer 2 allows even
complex structures to be reliably protected against isotropic
etching processes.
[0063] A trench 61 is incorporated in the substrate 1 which has two
sections 11, 12 in FIG. 9A. A conductive structure is formed within
the second layer element 12 of the substrate 1 and can be
conductively connected to a filling in the trench 61 with a low
contact resistance. The filling in the trench 61 is produced by a
layer sequence of different materials, which are each deposited
conformally. This results in the process layer 3 being in the form
of a layer stack with three stack layers 331, 332, 333. The layer
stack is etched back, for example, by a chemical-mechanical
polishing method, above a substrate edge 7 that is formed by an
upper edge of the trench 61. The etching signal layer 2 is for this
purpose deposited in a vertically structured manner. The etching
signal layer 2 covers horizontal sections of the substrate surface
10 in the region of the trench edge 7, and upper vertical sections
of the trench 61.
[0064] The process layer 3' is etched back into the trenches 61 by
a chemical-mechanical polishing process. No component of a
dielectric etching signal layer which would increase the contact
resistance between conductive end structures in the second layer
element 12 and in the filling 3' is located between the second
layer element 12, in which conductive structures are formed, and
the filling of the trench 61 or the structured process layer
3'.
* * * * *