U.S. patent application number 10/425783 was filed with the patent office on 2004-02-26 for methods for repairing defects on a semiconductor substrate.
Invention is credited to Uzoh, Cyprian.
Application Number | 20040035709 10/425783 |
Document ID | / |
Family ID | 24131177 |
Filed Date | 2004-02-26 |
United States Patent
Application |
20040035709 |
Kind Code |
A1 |
Uzoh, Cyprian |
February 26, 2004 |
Methods for repairing defects on a semiconductor substrate
Abstract
The present invention relates to methods for repairing defects
on a semiconductor substrate. This is accomplished by selectively
depositing the conductive material in defective portions in the
cavities while removing residual portions from the field regions of
the substrate. Another method according to the present invention
includes forming a uniform conductive material overburden on a top
surface of the substrate. The present invention also discloses a
method for depositing a second conductive material on the first
conductive material of the substrate.
Inventors: |
Uzoh, Cyprian; (Milpitas,
CA) |
Correspondence
Address: |
Legal Department
NuTool, Inc.
1655 McCandless Drive
Milpitas
CA
95035
US
|
Family ID: |
24131177 |
Appl. No.: |
10/425783 |
Filed: |
April 29, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10425783 |
Apr 29, 2003 |
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09534704 |
Mar 24, 2000 |
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6582579 |
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Current U.S.
Class: |
205/123 ;
205/183; 257/E21.175; 257/E21.304; 257/E21.583; 257/E21.585;
257/E21.595 |
Current CPC
Class: |
H01L 21/3212 20130101;
H01L 21/2885 20130101; H01L 21/7684 20130101; H01L 21/76892
20130101; H01L 21/76877 20130101 |
Class at
Publication: |
205/123 ;
205/183 |
International
Class: |
C25D 005/02 |
Claims
What is claimed is:
1. A method for forming a uniform overburden conductive layer over
a non-planar first conductive material on a substrate having a
barrier layer and a seed layer, the method using an anode and a pad
and comprising the steps: applying the pad proximate to the
substrate surface; applying an electric field between the anode and
the first conductive material; and depositing a second conductive
material from a solution over the first conductive material to form
the uniform overburden conductive layer.
2. The method according to claim 1, wherein the first and second
conductive materials comprise a same material.
3. The method according to claim 1, wherein the first conductive
material comprises Cu and second conductive material comprises one
of copper alloy, cobalt alloy, and silver alloy.
4. The method according to claim 3, further comprising the step of
depositing a boundary layer between the first conductive material
and the second conductive material such that the first conductive
material does not intermix with the second conductive material.
5. The method according to claim 1, further comprising the step of
polishing the uniform overburden conductive layer using chemical
mechanical polishing.
6. A method of correcting a non-uniform first deposited conductive
material formed on a conductive surface of a substrate comprising
the steps: coating the first deposited conductive material with a
second conductive material; and planarizing the second conductive
material and the second conductive material to form a substantially
uniform conductive surface on the substrate.
7. The method according to claim 6, wherein the step of coating
includes electroless depositing the second conductive material over
the first conductive material.
8. The method according to claim 6 further comprising a pad and an
anode wherein the step of coating includes: applying the pad
proximate to at least one non-uniform portion of the conductive
surface; applying an electric field between the anode and the
substrate; and depositing the second conductive material from a
solution to the at least one non-uniform portion of the conductive
surface to form the substantially uniform conductive surface.
9. The method according to claim 8, wherein the pad includes fixed
abrasive particles.
10. The method according to claim 8, wherein the substrate includes
field regions and the method of depositing the second conductive
material includes the step of removing residual conductive
materials from the field regions.
11. The method according to claim 8, wherein the conductive surface
and the conductive material comprise a same material.
12. The method according to claim 8, wherein the conductive
material comprises an alloy.
13. The method according to claim 8, wherein the pad includes a
porous material.
14. The method according to claim 8 further comprising the step of
applying a thermal process to the substrate after the depositing
step.
15. The method according to claim 8, wherein the depositing step
creates a distinct boundary between the first deposited conductive
material and the second conductive material deposited in the
depositing step.
16. The method according to claim 15, further comprising the step
of applying a thermal process to the substrate after the depositing
step.
17. The method according to claim 8, wherein the depositing step
enhances corrosion resistance.
18. The method according to claim 12, wherein the depositing step
enhances corrosion resistance.
19. The method according to claim 8, wherein the depositing step
enhances electromigration.
20. The method according to claim 12, wherein the depositing step
enhances electromigration.
21. The method according to claim 8 further comprising the step of
chemically mechanically polishing the substantially uniform
conductive surface.
22. An integrated circuit manufactured including the steps of claim
1.
23. An integrated circuit manufactured including the steps of claim
5.
24. An integrated circuit manufactured including the steps of claim
8.
25. An integrated circuit manufactured including the steps of claim
21.
Description
REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. Ser. No.
09/534,704 filed Mar. 24, 2000.
FIELD OF THE INVENTION
[0002] The present invention relates to methods for repairing
defects on a semiconductor substrate. More particularly, the
present invention is directed to methods for repairing defects on a
top surface of the substrate by selectively plating over the
defective portions while preventing deposition in the non-defective
portions. In addition, the present invention relates to planarizing
a non-planar conductive surface of a substrate.
BACKGROUND OF THE INVENTION
[0003] Depositing a conductive material such as metal in damascene
type cavities (i.e., trenches, holes, and vias) of a semiconductor
substrate (i.e., wiring structure) is an important and necessary
process in fabricating integrated chips and devices. The conductive
material is deposited in the cavities of the substrate to
interconnect layers and components contained therein. Recently,
there is great interest in using copper as the conductive material
as it provides better conductivity and reliability than, for
example, aluminum or aluminum alloys.
[0004] FIG. 1A illustrates a cross sectional view and FIG. 1B
illustrates a perspective view of a substrate after depositing the
conductive material in the cavities. These figures illustrate a
dielectric or insulating layer 2 (e.g., silicon dioxide--SiO.sub.2)
having deposited thereon an adhesive or barrier layer 4. The
insulating layer 2 is generally etched to form the cavities 12
therein before the barrier layer 4 is deposited thereon. The
cavities 12 in the insulating layer 2 are generally etched using a
reactive ion etching (RIE) method. The barrier layer 4 is generally
deposited on the insulating layer 2 using any of the various
sputtering methods, chemical vapor deposition (CVD),
electro-deposition or electroless plating method. The barrier layer
4 may be tantalum (Ta), titanium (Ti), tungsten (W),
titanium-tungsten (TiW), titanium nitride (TiN), Nb, CuWP, CoWP, or
other materials or combinations thereof that are commonly used in
this field.
[0005] After the barrier layer 4 is deposited on the insulating
layer 2, a seed layer (not shown) is generally deposited thereon
before the conductive material 6 such as copper is deposited on the
substrate. In general, the seed layer is the same material as the
conductive material 6. The conductive material 6 can be deposited
using CVD, sputtering, electroless plating, electro-deposition, or
combinations thereof.
[0006] The depths of the cavities 12 in the insulating layer 2 can
range from 0.02 to 200 um for interconnects and up to 1000 um or
more for packages. The conductive material 6 is generally deposited
over the entire top surface of the substrate, i.e. in the cavities
12 as well as on the field regions 3. It should be noted that the
field regions 3 are defined as the top surface area of the
substrate between the cavities 12. The excess material deposited
over the top plane of the field regions 3 is known as the
overburden. The thickness of the overburden may change over the
various features of the substrate depending on their size. For
example, in general, the overburden is thicker over the smaller
cavities than the larger cavities.
[0007] Once the conductive material 6 is formed in the cavities 12
and on the field regions 3, the substrate is typically transferred
to an apparatus for polishing and removing the overburden from the
top surface (i.e., field regions). Typically, the substrate is
polished using a conventional chemical mechanical polishing (CMP)
device and abrasive slurry. While using this method, some
conductive material 6 grains may be removed from the cavities 12,
thereby resulting in substrates with various defects. For example,
certain grains of the conductive material 6 in the cavities 12 may
be corroded away because the abrasive slurry may attach itself to
the conductive material 6 grains. Thus, some grains of the
conductive material 6 may be etched away from the cavities 12,
leaving defective portions 8. Alternatively, defective portions 8
may result from deep scratches during the CMP process.
[0008] Defective portions 8 may also result from the conductive
material 6 deposition process itself. For example, non-optimal
deposition processes may give rise to voids in conductive material
6, and after polishing, such voids may result in the defective
portions 8. Further, residual conductive material 10 may not be
completely removed and left on the barrier layer 4, thereby
resulting in additional defects. As known, defects typically reduce
the quality of the conductive material 6 and device
performance.
[0009] FIG. 2 illustrates a cross sectional view of a substrate
having dishing effects. During the CMP process, "dishing" or
non-planar polishing may result because of over polishing. A large
recess 14 may be formed in a large test pad portion, while a small
recess 16 may be formed in a small bus line portion on the cavities
12 of the substrate. In addition, when the substrate is exposed to
the abrasives during the CMP process, corrosion and other
undesirable characteristics may result (i.e., dishing). Dishing may
also result from wet etching processes. It is well known that
existence of any kind of defects in the deposited conductive
material results in poor device performance and low process
yield.
[0010] Accordingly, there is a need for methods for repairing
defects on semiconductor substrates.
SUMMARY OF THE INVENTION
[0011] In view of the above-described problems of the prior art, it
is an object of the present invention to provide a method for
repairing defects on a semiconductor substrate.
[0012] It is another object of the present invention to provide a
method for repairing defects on a semiconductor substrate by
selectively plating over the defective portions while preventing or
minimizing deposition on the non-defective portions.
[0013] It is another object of the present invention to provide a
method for depositing a conductive material in defective portions
of the cavities on the substrate.
[0014] It is a further object of the present invention to provide a
method for providing a uniform conductive material overburden on
the substrate without depositing the conductive material on the
field regions of the substrate.
[0015] It is yet another object of the present invention to provide
a method for depositing a second conductive material on the first
conductive material of a substrate.
[0016] It is yet another object of the present invention to provide
a method that minimizes the disparity of the conductive material
overburden across a substrate while repairing defects on the
substrate.
[0017] These and other objects are achieved by providing methods
for repairing defects on the substrate in an efficient and reliable
manner. The present invention relates to methods for repairing
defects on a semiconductor substrate. This is accomplished by
selectively depositing the conductive material in defective
portions in the cavities while removing residual portions from the
field regions of the substrate. Another method according to the
present invention includes forming a uniform conductive material
overburden on the top surface of the substrate. The present
invention also discloses a method for depositing a second
conductive material on the first conductive material of the
substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] These and other objects and advantages of the present
invention will become apparent and more readily appreciated from
the following detailed description of the presently preferred
exemplary embodiments of the invention taken in conjunction with
the accompanying drawings, of which:
[0019] FIG. 1A illustrates a cross sectional view of a conductive
material disposed on a substrate having defects;
[0020] FIG. 1B illustrates a perspective view of FIG. 1A of a
conductive material disposed on a substrate having defects;
[0021] FIG. 2 illustrates a cross sectional view of a conductive
material disposed on a substrate having "dishing"
characteristics;
[0022] FIGS. 3A-3D illustrate cross sectional views of a method for
repairing defects in accordance with the preferred embodiment of
the present invention;
[0023] FIGS. 4A-4D illustrate cross sectional views of a method for
repairing defects in accordance with another preferred embodiment
of the present invention; and
[0024] FIGS. 5A-5B illustrate cross sectional views of a method for
depositing a second conductive material on a first conductive
material in accordance with yet another preferred embodiment of the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] The present invention will now be described in greater
detail, which may serve to further the understanding of the
preferred embodiments of the present invention. As described
elsewhere herein, various refinements and substitutions of the
various embodiments are possible based on the principles and
teachings herein.
[0026] The preferred embodiments of the present invention will be
described with reference to FIGS. 3-5, wherein like structures and
materials are designated by like reference numerals throughout the
various figures. Further, specific details and processing
parameters are provided herein and are intended to be explanatory
rather than limiting.
[0027] The inventors of the present invention disclose herein
methods for repairing defects on a substrate. The present invention
can be used with any substrate or workpiece such as a wafer, flat
panel, magnetic film head, integrated circuit, device, chip, and
packaging substrate, and it can be used with various conductive
materials including, but not limited to copper, copper alloys,
magnetic films, ferromagnetic films, lead tin solder alloys or lead
free solder alloys.
[0028] In accordance with the present invention, the defective
substrate is preferably plated using an electro-deposition or
electroless deposition process before removing the barrier layer
from the top surface of the substrate. The barrier layer is used to
conduct the electric current, and depending on the deposition time
and current density, various portions of the substrate is plated
accordingly.
[0029] FIGS. 3A-3D illustrate cross sectional views of a method for
repairing defects in accordance with the first preferred embodiment
of the present invention. In this preferred embodiment, defects in
the cavities of the substrate are repaired by selectively plating
over the defective regions, while simultaneously preventing
deposition in the field regions of the substrate.
[0030] The method shown in FIGS. 3A-3D include the step of
depositing a conductive material in the cavities of the substrate
to repair the defects using an ECMD (electrochemical mechanical
deposition) device having a pad type material attached to an anode.
Such apparatus is described in greater detail in the co-pending
U.S. application Ser. No. 09/373,681, filed Aug. 13, 1999, entitled
"Method and Apparatus for Depositing and Controlling the Texture of
A Thin Film", the contents of which are expressly incorporated
herein by reference.
[0031] FIG. 3A illustrates an insulating layer 2 having deposited
thereon a barrier layer 4, similar to that described above with
reference to FIGS. 1A and 1B. Again, the top surface of the
insulating layer 2 is patterned/etched with cavities 12 before the
barrier layer 4 is deposited thereon. The insulating layer 2 is
preferably SiO.sub.2 or polyimide, but it is understood that other
materials that are commonly used as the insulating layer 2 may be
used in accordance with the present invention.
[0032] In FIG. 3B, a porous pad type material 100 with or without
fixed abrasive particles (not shown) is used to repair the defects
8, 10 on the substrate. This is accomplished by selectively
depositing the conductive material in the defective portion 8 while
removing the residual material 10 from the field regions of the
substrate. The pad type material 100 is preferably attached to an
anode (not shown) and may be rotated in a circular motion,
vibrated, moved side to side or vertically when brought into
contact with the top surface of the substrate. Likewise, the
substrate may be rotated in a circular motion, vibrated, moved side
to side or vertically when brought into contact with the pad type
material 100. In the preferred embodiment, the pad type material
100 and the substrate may rotate between 1 to 400 rpm, but
preferably between 5 to 300 rpm, during the repairing mode. A
suitable electrolyte containing the conductive material to be
deposited is introduced between the pad and the substrate surface
before a potential difference is applied between the anode and the
barrier layer 4 causing the conductive material to deposit out of
the electrolyte onto the substrate surface. An example of the
suitable electrolyte is disclosed in the co-pending provisional
U.S. application Serial No. 06/182,100, filed Feb. 11, 2000,
entitled "Modified Plating Solution for Plating and Planarization",
the contents of which are expressly incorporated herein by
reference.
[0033] Using the barrier layer 4, an electrical current with a
current density in the range of 0.05 to 20 mA/cm.sup.2, but
preferably between 1 to 5 mA/cm.sup.2 is applied to the substrate
using the ECMD device. The repairing process can be performed for a
period of 30 to 180 seconds when the pad 100 is in full contact
with the substrate as shown in FIG. 3C. When such contact is made,
the pad type material 100 removes the residual material 10 residing
on the field regions of the substrate while depositing the
conductive material from the electrolyte into the defective portion
8. During this step, the pad type material 100 makes contact with
the top surface of the substrate at a pressure that may range from
0.0 to 15 psi. Further, the electrolyte containing the conductive
material may emanate from the pad type material 100 and is applied
to the substrate at a rate of 0.2 to 15 liters per minute, but
preferably between 0.5 to 10 liters per minute on a conventional 8
inch diameter wafer. Using this method, a planar defect-free
structure is obtained as shown in FIG. 3D.
[0034] In certain cases it is desirable to have the substrate
surface with a uniform and planar layer of a conductive material.
The method disclosed in FIGS. 4A-4C is used to transform a
defective substrate surface into a substrate having a planar
conductive layer.
[0035] In FIG. 4A, a defective substrate similar to the one
depicted in FIG. 3A is shown. In FIG. 4B, a seed layer 5 is
deposited on the defective substrate surface. The seed layer 5 may
be 50-500 A in thickness. It may be a composite layer consisting of
two or more layers. It is important to note that the seed layer 5
allows growth of a uniform conductive layer over it with good
adhesion to the substrate surface. If the adhesion of the
conductive layer to the barrier layer 4 is adequate, there may not
be the need for the seed layer 5.
[0036] During the repair process, using the barrier layer 4 and
seed layer 5, an electrical current with a current density in the
range of 0.05 to 20 mA/cm.sup.2, but preferably between 1 to 10
mA/cm.sup.2 is applied to the substrate using the ECMD device. In
this case, the pad 100 does not make contact with the substrate,
but does hydroplane over it. The repairing process can be performed
for a period of 20 to 300 seconds when the pad 100 is hydroplaning,
as shown in FIG. 4B. In this manner, the conductive material is
deposited in the defective portion 8 and a uniform metal overburden
7 is built over the entire substrate surface as shown in FIG. 4C,
while burying the residual materials 10. During this step, the
electrolyte solution containing the conductive material 7 may
emanate from the pad type material 100 and may be applied to the
substrate at a rate of 0.2 to 6 liters per minute. The pressure may
be 0.1 to 2 psi. Low pressure between the substrate and the pad 100
and high electrolyte flow allow the pad 100 to hydroplane over the
substrate surface. Both the substrate and the pad 100 may be
rotated during deposition at 5 to 300 rpm.
[0037] It should be noted that the present technique may be used to
planarize a defect free but non-uniform or dished conductive
surface on a substrate as shown in FIGS. 5A and 5B. The non-uniform
layer 110 on the surface of the substrate of FIG. 5A is coated with
a planar layer 120 resulting in the structure of FIG. 5B.
[0038] In certain embodiments, the conductive materials 110, 120
may be the same materials. In the alternative, the conductive
materials 110, 120 may be different materials. For example, the
second conductive material 120 may be Cu--Sn, Cu--In, WCoP or CoP,
or other suitable copper alloys, cobalt alloys, silver alloys,
etc., and the first conductive material 110 may be Cu. Preferably,
the second conductive material 120 should be a material that will
enhance corrosion resistance and electromigration, while providing
excellent adhesion to the first conductive material 110 and to
other subsequently deposited materials that may be formed thereon.
Further, the second conductive material 120 may have an electrical
resistivity that is very similar to the first conductive material
110, preferably within 90-200% of that of the first conductive
material 110.
[0039] When the first and second conductive materials 110, 120 are
the same materials, a distinct boundary between them may not exist.
On the other hand, when the first and second conductive materials
110, 120 are different, a distinct boundary between them may exist
before any subsequent thermal process is performed. The distinct
boundary layer can be used so that intermixing between the first
and second conductive materials 110, 120 is discouraged. For
example, a thin adhesive or barrier layer (e.g., alpha Tantalum,
chrome layer, CoP, WCoP) may be deposited in between the first and
second conductive materials 110, 120 to prevent intermixing between
the two materials when such intermixing is undesired. In other
embodiments, more than two conductive materials can be formed in
the cavities of the substrate using the process disclosed
herein.
[0040] In a further processing step, the entire substrate as shown
in FIG. 5B may be polished by CMP to produce high yield devices.
Alternatively, the overburden can be removed by wet etch,
electropolishing, or electroplating.
[0041] Along with using copper and its alloys as the conductive
material, other conductive materials such as aluminum, iron,
nickel, chromium, indium, lead, tin, lead-tin alloys, nonleaded
solderable alloys, silver, zinc, cadmium, titanium, tungsten
molybdenum, ruthenium, gold, paladium, cobalt, rhondium, platinum,
their respective alloys and various combinations of above materials
with oxygen, nitrogen, hydrogen and phosphorous may be used in the
present invention.
[0042] In addition, the repairing steps described above may be
performed in an electroless deposition bath. Various processing
conditions such as plating bath temperature, pressure, pad
material, pad design, solution flow rate, and the like can be
varied to repair the defects in the substrate material.
[0043] In other embodiments, the conductive material or seed layer
used for repairing the defect does not need to be homogeneous with
the defective conductive material base. For example, in FIG. 4B,
the seed layer 5 need not be copper, but may be silver, or a copper
or silver based alloy such as copper indium alloy, copper silver
alloy or even silver indium alloy. Thus, after depositing the seed
layer 5 on the substrate, the defects are repaired using the
methods described earlier, using the seed layer and barrier to
carry the current. In this case where a substantial uniform
overburden 7 of FIG. 4C is left on the field regions, the
non-homogeneous seed layer is now part of the overburden 7.
[0044] In the previous descriptions, numerous specific details are
set forth, such as specific materials, structures, current density,
chemicals, processes, etc., to provide a thorough understanding of
the present invention. However, as one having ordinary skill in the
art would recognize, the present invention can be practiced without
resorting to the details specifically set forth.
[0045] Although various preferred embodiments have been described
in detail above, those skilled in the art will readily appreciate
that many modifications of the exemplary embodiment are possible
without materially departing from the novel teachings and
advantages of this invention.
* * * * *