U.S. patent application number 10/600947 was filed with the patent office on 2004-01-15 for structures to mechanically stabilize isolated top-level metal lines.
Invention is credited to Selvin, Eric, Seshan, Krishna.
Application Number | 20040009657 10/600947 |
Document ID | / |
Family ID | 27766317 |
Filed Date | 2004-01-15 |
United States Patent
Application |
20040009657 |
Kind Code |
A1 |
Selvin, Eric ; et
al. |
January 15, 2004 |
Structures to mechanically stabilize isolated top-level metal
lines
Abstract
A method is described for providing protective structure to
protect integrated circuits against various types of damages. The
method includes patterning a signal line from a metal material as a
terminal conductive layer of an integrated circuit die, patterning
a first protective structure to surround the signal line, and
patterning a second protective structure to surround the first
protective structure.
Inventors: |
Selvin, Eric; (San Jose,
CA) ; Seshan, Krishna; (San Jose, CA) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD, SEVENTH FLOOR
LOS ANGELES
CA
90025
US
|
Family ID: |
27766317 |
Appl. No.: |
10/600947 |
Filed: |
June 20, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10600947 |
Jun 20, 2003 |
|
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09464058 |
Dec 15, 1999 |
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6614118 |
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Current U.S.
Class: |
438/624 ;
257/E23.142; 257/E23.146; 257/E23.194; 438/622 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 23/525
20130101; H01L 23/562 20130101; H01L 23/522 20130101 |
Class at
Publication: |
438/624 ;
438/622 |
International
Class: |
H01L 021/4763 |
Claims
What is claimed is:
1. A method comprising: patterning a signal line from a metal
material as a terminal conductive layer of an integrated circuit
die; patterning a first protective structure to surround the signal
line; and patterning a second protective structure to surround the
first protective structure.
2. The method of claim 1, further comprising: patterning the first
protective structure as a continuous structure to enclose the
signal line.
3. The method of claim 1, further comprising: patterning the first
and second protective structures to one of a low rail supply line
and a high rail supply line.
4. A method comprising: forming a first interconnection
metallization layer on a substrate; forming a second
interconnection metallization layer on the first interconnection
metallization layer; forming at least one signal line coupled to
the first interconnection metallization layer in the second
interconnection metallization; forming at least one protective
structure that surrounds the at least one signal line in the second
interconnection metallization layer.
5. The method of claim 4, wherein the forming at least one
protective structure that surrounds the at least one signal line
comprises using a continuous loop-like shape protective structure
to enclose the signal line.
6. The method of claim 4, further comprising coupling the at least
one protective structure to a low rail supply voltage.
7. The method of claim 4, further comprising coupling the at least
one protective structure to a high rail supply voltage.
8. The method of claim 4, wherein the at least one protective
structure is spaced from the signal line at approximately 2
microns.
9. The method of claim 4, wherein the first interconnection
metallization layer has a first volume and the second
interconnection metallization layer has a second volume greater
than the first volume.
10. The method of claim 4, wherein the forming at least one
protective structure comprises forming a plurality of protective
structures (PSi) for i=1 . . . N, a first protective structure PSi
surrounding the signal line, each protective structure PS1
surrounding a previous protective structure PSi-1.
Description
RELATED APPLICATION
[0001] The present application is a divisional application of U.S.
Ser. No. 09/464,058, filed Dec. 15, 1999, currently pending.
FIELD OF THE INVENTION
[0002] The invention relates to semiconductor devices and circuit
fabrication. More specifically, the invention relates to integrated
circuits that include structures to protect the integrated circuits
against various types of damages.
BACKGROUND OF THE INVENTION
[0003] Often semiconductor dies are subjected to mechanical agents
(forces) that are likely to damage the dies. Some of these forces
are surface forces that may arise, for example, when semiconductor
dies are packaged. Moreover, packages, which are not completely
rigid, transmit some of the external forces to the die. These
forces cause delamination of various structures located at the top
of the dies such as soft and hard passivation layers as well as top
layer metal lines. Delamination allows moisture and other
impurities to penetrate the semiconductor die.
[0004] FIG. 1 illustrates a top view of die 100. Die 100 includes
die active area 102. Near edges 106 of die active area 102 are
small isolated metal interconnect lines (interconnection
metallization) 104 formed in the top metal layer also known as the
terminal metal layer. The metal interconnect lines typically route
signals on die 100. One current integrated circuit chip technology
utilizes up to five layers of interconnect, referenced by M1, M2,
M3, M4, and M5. In such a scheme, the terminal metal layer is M5.
Lines 104 are portions of signal lines that are routed in lower
layers of metal (not shown) found beneath terminal metal layer M5.
Lines 104 have been shown to fail mechanically when the dies are
packaged or when the packaged dies are subjected to temperature
cycling during reliability testing. It is desired to protect the
above-mentioned lines against the agents that damage these
lines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The features, aspects, and advantages of the invention will
become more fully apparent from the following Detailed Description,
appended claims, and accompanying drawings in which:
[0006] FIG. 1 illustrates a top view of a typical prior art
die.
[0007] FIG. 2 illustrates a die with protective structures
according to one embodiment of the invention.
[0008] FIG. 3 illustrates a cross sectional view through the die
illustrated in FIG. 2.
[0009] FIG. 4 illustrates another embodiment of the invention where
the top metal layer lines are wider than underlying metal
lines.
DETAILED DESCRIPTION OF THE INVENTION
[0010] In the following description, numerous specific details are
set forth to provide a thorough understanding of the invention.
However, one having ordinary skill in the art should recognize that
the invention may be practiced without these specific details. In
some instances, well-known circuits, structures, and techniques
have not been shown in detail to avoid obscuring the invention.
[0011] The invention provides in one embodiment thereof an
integrated circuit. The integrated circuit includes a substrate and
a first interconnection metallization or metal layer formed upon
the substrate. The integrated circuit further includes a second
interconnection metallization or metal layer formed upon the first
metal layer. The second metal layer has formed therein at least one
signal line coupled to the first metal layer. The second metal
layer has formed therein at least one protective structure that
surrounds the at least one signal line.
[0012] FIG. 2 is a top view of die 200 of an integrated circuit
(e.g., chip or die) that has a terminal interconnection
metallization or metal layer (e.g., M5 layer) in which are formed
protective structures 206, 208, and 210. The protective structures
surround isolated signal line 204 formed out of the terminal
metallization or metal layer and absorb the forces exerted at the
surface of the die. A suitable material for the terminal
interconnection metallization or metal layer is a metal material
of, for example, elemental metal or a metal alloy. Aluminum and
copper and their alloys are examples of suitable terminal metal. In
one embodiment, protective structures 206, 208 and 210 surround
signal line 204, with signal line 208 surrounding signal line 210
and signal line 206 surrounding signal line 208 as shown in FIG.
2.
[0013] In one embodiment structures 206, 208, and 210 are
continuous structures (closed loops) that surround at 360 degrees
signal line 204 to protect signal line 204 from forces that may be
exerted from various directions. In FIG. 2, the structures are
rectangular in form. In one embodiment, each structure 206, 208,
and 210 has a width on the order of 2-15 microns with the space
between (i.e., separating) structures 206, 208, and 210
approximately 2 microns according to a current design rule. The
similar design rule example dictates a spacing between signal line
204 and structure 210 of approximately 2 microns. Structures 206,
208, and 210 are formed, in one embodiment, in the terminal
metallization layer through patterning techniques commensurate with
patterning the terminal metallization layer (e.g., M5). Thus, in
one typical technique, a blanket metallization of a metal material
is introduced over the substrate and patterned by, for example,
etching through a mask to define structures 206, 208, and 210 and
signal line 204.
[0014] The multiplicity of structures 206, 208, and 210 serve, in
one aspect, the objective that if the outer structure, say
structure 206, breaks, there are other remaining structures 208 and
210 in place capable of protecting signal lines 204 by absorbing
the forces exerted on the integrated circuit (e.g., chip or die).
In one embodiment structures 206, 208, and 210 may be coupled to
the lower supply rail (ground). In another embodiment, structures
206, 208, and 210 are coupled together to the higher supply rail
(V.sub.CC). Coupling the structures to V.sub.CC or ground serves to
reduce stray charges that may build up on structures 206, 208, and
210 thereby minimizing the capacitive impact that may be introduced
by structures 206, 208 and 210.
[0015] FIG. 3 illustrates a cross sectional view taken through line
A-A of FIG. 2. In this illustration, the terminal interconnection
metallization or metal line (e.g., metal layer M5) includes signal
line 204 surrounded by protective structures 206, 208, and 210.
Below signal line 204 there are two interconnection metallization
or metal four (M4) structures 222 and 224 coupled to isolated line
204 by way of vias or contact plugs 226 and 228, respectively, such
as, for example, titanium and/or titanium-tungsten vias or contact
plugs.
[0016] FIG. 3 also shows contact structure 206 coupled by way of
vias or contact plugs and landing pads to substrate 230, such as a
silicon substrate. Landing pads 225A, 225B, 225C, and 225D are
patterned in their respective metallization layers M4, M3, M2, and
M1 to provide conductive coupling points for vias or contact plugs
227A, 227B, 227C, and 227D. Contact plug 227E couples structure 206
to contact point 229 of substrate 230 that may be coupled, for
example, to the lower or higher supply rail. Similar configurations
can be implemented for contact structures 208 and 210 either
isolated individually or sharing landing pads and the contact print
with structure 206. It is to be appreciated that the landing pads
and vias or contact plugs are generally surrounded by dielectric
material.
[0017] As noted above, the terminal interconnection metallization
and metal structures (signal line 204 and structures 206, 208, and
210) are formed by standard processes including patterning the
metal structures, etching the metal, etc. A passivation layer
including hard passivation layer 212 of, for example, silicon
nitride, and soft passivation layer 213 of, for example, a
polyimide is introduced conformally over the terminal metal
structures.
[0018] In the above embodiment, essentially sacrificial structures
were illustrated surrounding a terminal signal line. It is to be
appreciated that such structures can have a variety of
configurations and may vary in number depending on design. The
structures are incorporated into a terminal metallization layer, in
one measure, to protect the terminal signal line(s). The
actual/degree of protection and thus incorporation and design of
such structures will be dictated, in large part, on design rules
including available area and cost.
[0019] FIG. 4 illustrates another embodiment of the invention where
terminal interconnection metallization signal line 404 is protected
against damaging agents by making it wider. The larger width of
these lines generally enhances the stability of these lines. In one
aspect, interconnection metallization signal line 404 in the
terminal metallization layer (e.g., M5) is much wider than a
corresponding width of interconnection metallization signal lines
formed in inferior layers (e.g., M4, M3, etc.). In the example
shown in FIG. 4, signal line 404 is wide enough to completely cover
vias or contact plugs 405. Using a current design rule where the
thickness of a typical interconnection metallization or metal
signal line (e.g., M4, M3, etc.) is approximately 2 microns, signal
line 404 may have, in one embodiment, a width of approximately 2.5
microns. The additional width provides additional volume and
surface area of the terminal metal signal line provides improved
strength and durability thus improving its resistance to damage by
external forces.
[0020] In the previous detailed description, the invention is
described with reference to specific embodiments thereof. It will,
however, be evident that various modifications and changes may be
made thereto without departing from the broader spirit and scope of
the invention as set forth in the claims. The specification and
drawings are, accordingly, to be regarded in an illustrative rather
than a restriction sense.
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