U.S. patent application number 10/615084 was filed with the patent office on 2004-01-08 for germanium implanted hbt bipolar.
This patent application is currently assigned to STMicroelectronics S.r.l.. Invention is credited to Lombardo, Salvatore, Nicotra, Maria Concetta, Pinto, Angelo.
Application Number | 20040004270 10/615084 |
Document ID | / |
Family ID | 8230652 |
Filed Date | 2004-01-08 |
United States Patent
Application |
20040004270 |
Kind Code |
A1 |
Lombardo, Salvatore ; et
al. |
January 8, 2004 |
Germanium implanted HBT bipolar
Abstract
A vertical structure high carrier mobility transistor on a
substrate of crystalline silicon doped with impurities of the N
type, the transistor having a collector region located at a lower
portion of the substrate. The transistor includes a heterostructure
alloy region positioned in the substrate and comprised of a
heterostructure alloy of silicon and germanium. A base region is
positioned in the substrate above the first conducting region and
doped with P-type impurities. A first dielectric layer is
positioned on, and directly contacts, the heterostructure alloy
region, and defines a first window directly above the
heterostructure alloy region. The transistor also includes an
emitter positioned in the heterostructure alloy region and between
the first window and the base region. The emitter is comprised of
the heterostructure alloy doped with impurities of the first type
and directly contacts the first dielectric layer.
Inventors: |
Lombardo, Salvatore;
(Catania, IT) ; Nicotra, Maria Concetta; (Catania,
IT) ; Pinto, Angelo; (Augusta, IT) |
Correspondence
Address: |
SEED INTELLECTUAL PROPERTY LAW GROUP PLLC
701 FIFTH AVE
SUITE 6300
SEATTLE
WA
98104-7092
US
|
Assignee: |
STMicroelectronics S.r.l.
Agrate Brianza
IT
|
Family ID: |
8230652 |
Appl. No.: |
10/615084 |
Filed: |
July 7, 2003 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10615084 |
Jul 7, 2003 |
|
|
|
09724563 |
Nov 27, 2000 |
|
|
|
6624017 |
|
|
|
|
09724563 |
Nov 27, 2000 |
|
|
|
09087398 |
May 29, 1998 |
|
|
|
Current U.S.
Class: |
257/565 ;
257/E21.335; 257/E21.371 |
Current CPC
Class: |
H01L 21/2658 20130101;
H01L 21/26513 20130101; H01L 21/26506 20130101; H01L 29/66242
20130101 |
Class at
Publication: |
257/565 |
International
Class: |
H01L 027/082; H01L
027/102; H01L 029/70; H01L 031/11 |
Foreign Application Data
Date |
Code |
Application Number |
May 30, 1997 |
EP |
97830259.4 |
Claims
1. A heterostructure bipolar transistor, comprising: a substrate
comprised of a first semiconductor material doped with impurities
of a first type, the substrate including a first conducting region;
a heterostructure alloy region positioned in the substrate and
comprised of a heterostructure alloy of atoms of the first
semiconductor material and atoms of a second semiconductor
material; a base region positioned in the substrate above the first
conducting region and doped with impurities of a second type; a
first dielectric layer positioned on the substrate, the first
dielectric layer defining a first window directly above the
heterostructure alloy region; a second conducting region positioned
in the heterostructure alloy region and between the first window
and the base region, the second conducting region being comprised
of the heterostructure alloy doped with impurities of the first
type; and a contact region positioned in the first window and
comprised of the first semiconductor material, the contact region
directly contacting the heterostructure alloy of the second
conducting region in the heterostructure alloy region.
2. The transistor of claim 1 wherein the first dielectric layer
directly contacts the heterostructure alloy of the of the
heterostructure alloy region.
3. The transistor of claim 1, further comprising: a protective
layer positioned over the semiconductor substrate and defining a
second window above the heterostructure alloy region, the first
dielectric layer being positioned in the second window between the
protective layer and the first window.
4. The transistor of claim 3, further comprising a second
dielectric layer positioned on the first dielectric layer and in
the second window between the protective layer and the first
window.
5. The transistor of claim 4 wherein the first dielectric layer is
silicon dioxide and the second dielectric layer is silicon
nitride.
6. The transistor of claim 1 wherein the first semiconductor
material is silicon, the second semiconductor material is
germanium.
7. The transistor of claim 1, further comprising a metal contact
formed directly on the contact region.
8. A heterostructure bipolar transistor, comprising: a substrate
comprised of a first semiconductor material doped with impurities
of a first type, the substrate including a first conducting region;
a heterostructure alloy region positioned in the substrate and
comprised of a heterostructure alloy of atoms of the first
semiconductor material and atoms of a second semiconductor
material; a base region positioned in the substrate above the first
conducting region and doped with impurities of a second type; a
first dielectric layer positioned on, and directly contacting, the
heterostructure alloy region, the first dielectric layer defining a
first window directly above the heterostructure alloy region; and a
second conducting region positioned in the heterostructure alloy
region and between the first window and the base region, the second
conducting region being comprised of the heterostructure alloy
doped with impurities of the first type and directly contacting the
first dielectric layer.
9. The transistor of claim 8, further comprising: a protective
layer positioned over the semiconductor substrate and defining a
second window above the heterostructure alloy region, the first
dielectric layer being positioned in the second window between the
protective layer and the first window.
10. The transistor of claim 9, further comprising a second
dielectric layer positioned on the first dielectric layer and in
the second window between the protective layer and the first
window.
11. The transistor of claim 10 wherein the first dielectric layer
is silicon dioxide and the second dielectric layer is silicon
nitride.
12. The transistor of claim 8 wherein the first semiconductor
material is silicon, the second semiconductor material is
germanium.
13. The transistor of claim 8, further comprising: a contact region
positioned in the first window and comprised of the first
semiconductor material, the contact region directly contacting the
heterostructure alloy of the second conducting region in the
heterostructure alloy region; and a metal contact formed directly
on the contact region.
14. A vertical structure high carrier mobility bipolar transistor,
comprising substrate of crystalline silicon doped with impurities
of the N type, having a collector region located at a lower portion
of the substrate, the transistor being obtained by a process that
includes: defining a window above the substrate; providing a first
implantation of germanium atoms through said window into the
substrate; providing a second implantation of acceptor dopants
through said window to define a base region in the substrate;
applying an RTA treatment, or treatment in an oven, to re-construct
a crystal lattice within the semiconductor substrate comprising a
silicon/germanium alloy; forming by chemical vapor deposition a
first thin dielectric layer of silicon dioxide on the substrate;
depositing a second dielectric layer onto said first dielectric
layer; depositing a polysilicon layer onto said second dielectric
layer; etching away, within the window region, said first and
second dielectric layers, and the polysilicon layer, to expose the
base region and form isolation spacers at edges of the window; and
forming an N-doped emitter in the base and window regions.
15. The transistor of claim 14 wherein the deposition of the first
thin dielectric layer of silicon dioxide is carried out by an
atmospheric pressure chemical vapor deposition process.
16. The transistor of claim 14 wherein the deposition of the first
thin dielectric layer of silicon dioxide is followed by thermal
treatment.
17. The transistor of claim 14 wherein the second dielectric layer
is silicon nitride.
18. The transistor of claim 14 wherein the emitter directly
contacts the first dielectric layer.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 09/724,563, filed Nov. 27, 2000, now pending, which is a
continuation of U.S. patent application Ser. No. 09/087,398, filed
on Mar. 29, 1998, which applications are incorporated herein by
reference in their entireties.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates generally to a process for
fabricating a vertical structure high carrier mobility transistor
on a crystalline silicon substrate, having a collector region
located at a lower portion of the substrate.
[0004] The invention relates, particularly but not exclusively, to
a process for fabricating a heterostructure bipolar transistor
(HBT) for very high frequency applications, and the description to
follow is given with reference to this applicational field for
convenience of illustration.
[0005] 2. Description of the Related Art
[0006] As skilled persons in the art know well, the application of
heterostructures to solid state electronic devices has prompted a
vast increase of their working range at very high frequencies.
[0007] In particular, this technology has been applied to bipolar
transistor devices, to thereby improve both the injection
efficiency of the charge carriers and the passage frequency
(f.sub.t) value, the latter being closely related to the cut-off
frequency (f.sub.T) of the device.
[0008] Heterostructures can be prepared by different methods, of
which the MBE (Molecular Beam Epitaxy) method is the best known and
provides a structure free of lattice imperfections; other, more
expensive methods are sophisticated versions of CVD which, however,
have a disadvantage in that their throughput adds to the cost of
the silicon die.
[0009] Yet this MBE method has only sparsely been applied to large
volume industrial processes, on account of it involving lengthy
processing steps that command strict control of their physical
parameters.
[0010] Thus, it has often been more convenient to adopt other
methods, such as ion implantation, which could yield similar
heterostructures of a fair quality within acceptable times for
large volume production lines.
[0011] A bipolar transistor implemented with a vertical structure
including a Ge.sub.xSi.sub.1-x heterostructure between the base and
collector regions will now be described in relation to such a field
of application.
[0012] The HBT bipolar transistor under consideration is
illustrated schematically by the enlarged cross-sectional view of
FIG. 1.
[0013] This HBT transistor has a vertical structure of the NPN type
and is formed on a crystalline semiconductor substrate 1 wherein,
by successive implantations, a collector region 2 of the N type, a
base region 3 of the P type, and an emitter region 4 of the N type
have been defined, from the substrate bottom up.
[0014] Specifically, it can be seen that the collector region 2
includes a heavily N-doped layer 5 effective to provide a good
ohmic contact with a collector metal (not shown because
conventional) provided in a lower portion of the substrate 1.
[0015] An added feature of the HBT transistor shown in FIG. 1 is an
opening provided above the substrate 1 to isolate the base region 3
and later allow formation of a contact region 9 above the emitter
region 4.
[0016] This contact region 9 comprises a heavily N-doped layer 7
overlaid by a metal layer 8.
[0017] Having briefly described the HBT transistor, the
Ge.sub.xSi.sub.1-x heterostructure formed within the crystalline
silicon substrate 1 will now be examined to see what changes are
introduced in the energy band curve of the HBT transistor.
[0018] This Ge.sub.xSi.sub.1-x heterostructure is characterized by
the x and 1-x concentrations, respectively associated with the
germanium and silicon atoms, varying with the spatial implant depth
in the substrate 1.
[0019] In FIG. 2, the energy band curve of the bipolar transistor
HBT is plotted as a full line for comparison with the band curve of
a standard bipolar transistor (BJT), plotted as a broken line.
[0020] A comparison of the two band curves of the transistors HBT
and BJT shows that the bipolar transistor HBT has an energy level
in the conduction band which is always below that of the standard
transistor BJT, through the base region to the interface with the
collector region.
[0021] In particular, it can be seen that for the transistor HBT,
when moving from its base region toward its collector region, there
occurs a gradual slow decrease of its energy gap (E.sub.g) which
can be regarded as an effect of spatial modulation of the energy
gap. This modulation is obtained by suitable implantation profiles
of the germanium (Ge) atomic species whose concentration is maximal
at the collector-base interface and minimal or almost nil at the
emitter-base interface.
[0022] An active zone bias of the bipolar transistor HBT conforming
with the above band curve allows of faster injection of the
carriers from the emitter region, thereby greatly reducing their
passage time.
[0023] The net result is a markedly increased cut-off frequency
(f.sub.T) of the HBT transistor and a decreased proportion of
carriers trapped within the base.
[0024] Thus, for HBT transistors biased with collector currents in
the milliampere range, high cut-off frequency values can be
obtained which would not be achievable by conventional bipolar
technology.
[0025] The Ge.sub.xSi.sub.1-x heterostructure provided between the
base and collector regions enables the P-doping of the base region
to be increased, thereby lowering the value of the intrinsic
resistance R.sub.bb in the base region that restricts the
applications of bipolar transistors at high frequencies.
[0026] A previously mentioned method of conventionally forming the
HBT transistor with a Ge.sub.xSi.sub.1-x heterostructure will now
be described with reference, in particular, to FIGS. 3a-3f. The
same reference numerals used for similar elements in FIG. 1 have
been retained for convenience.
[0027] FIG. 3a shows a crystalline silicon substrate 1 which has
been doped with impurities of the N type and formed with a window
10 by selective deposition of a protective material 11. This
protective material comprises a material layer, including
impurities of the P type, which is deposited over the substrate and
insulated by a dielectric capping.
[0028] A first implantation of germanium (Ge) is carried out
through this window 10, and is followed by a second implantation of
acceptor impurities, such as boron (B) atoms or BF.sub.2.sup.+
ions.
[0029] Thereafter, a step of re-construction of the crystal lattice
of the substrate 1 is carried out by an RTA (Rapid Thermal
Annealing) process, or a conventional thermal process in an oven,
which is also applied to aid in driving the implanted ions into
sites freed in the crystal lattice.
[0030] The outcome of this re-construction step is shown in FIG.
3b, where a planar base region 3, extending at the window 10 to a
sufficient depth to allow of the subsequent creation of an emitter
region, is highlighted for the first time.
[0031] Simultaneously with the formation of the base region 3 in
the substrate 1, a collector region 2 is defined which is
incorporated to the remaining portion, not implanted with P-type
impurities, of the substrate 1.
[0032] The base region, extending as far as the interface to the
collector region 2, will presently feature a Ge.sub.xSi.sub.1-x
heterostructure formed during the first implanting step and
characterized by an energy band curve of the kind shown in FIG.
2.
[0033] From now on, as shown in FIG. 3c, the processing over the
substrate 1, at the location of the window 10 and the protective
material 11, will see the following successive operations:
[0034] thermal growth of a first thin dielectric layer 12 of
silicon dioxide (SiO.sub.2);
[0035] deposition of a second dielectric layer 14, typically of
silicon nitride (Si.sub.3N.sub.4), onto the first thin dielectric
layer 12;
[0036] deposition of a polysilicon layer 15.
[0037] To provide an emitter region at the location of the window
10 in the substrate 1, the process for fabricating the HBT
transistor comprises a first chemio-physical etching (RIE) step and
a second etching step, respectively of the polysilicon layer 15 and
the second dielectric layer 14, to partially form isolation spacers
at the edges of the window 10, as shown in FIG. 3d.
[0038] A third wet etching step of the remaining portions of the
polysilicon layer 15, and a fourth etching step of the first thin
dielectric layer 12 only, bring to completion the formation of the
spacers 50, thereby exposing the base region 3 again, as shown in
FIG. 3e.
[0039] The HBT transistor with Ge.sub.xSi.sub.1-x heterostructure
can now be completed by conventional processes for the formation of
an emitter region 4 accommodated within the base region 3 and
overlaid by a corresponding emitter contact 9.
[0040] FIG. 3f is a general view of the HBT transistor with
Ge.sub.xSi.sub.1-x heterostructure being provided with an emitter
contact 9 which comprises a first polysilicon layer 7 heavily doped
with impurities of the N type and metallized on top by a layer
8.
[0041] The HBT transistors with Ge.sub.xSi.sub.1-x heterojunction
fabricated with the above process have revealed upon testing a
behavior of the base current which is less than ideal.
[0042] This deviation from the ideal is brought out by the graph of
FIG. 4, where the collector and base currents are plotted versus
the voltage V.sub.be between the base and the emitter, for two
different HBT transistors formed on a common substrate.
[0043] The HBT transistors (T1, T2) in question have values (At1,
At2) of their emitter surface areas of 2.times.7.4 .mu.m.sup.2 and
0.4.times.7.4 .mu.m.sup.2, respectively, resulting in a ratio
(At1/At2) of five between their emitter areas and a ratio (pt1/pt2)
of 1.2 between the outer perimeters of their emitter regions.
[0044] On the graph, the curves relating to the transistor T1 are
full lines, and those relating to the transistor T2 are broken
lines.
[0045] It can be seen from the graph that the base currents (those
having flatter curves) of T1 and T2 differ little from each other,
although the ratio (At1/At2) of their emitter areas is of five.
[0046] This brings out the existence of a non-ideal component for
the base current which is unaffected by changes in the emitter
surface area. This deviation from the ideal, well recognized in the
art, has been attributed heretofore to attempts of the
Ge.sub.xSi.sub.1-x heterostructure, regarded as being responsible
for re-combination phenomena within the semiconductor substrate, to
relax.
BRIEF SUMMARY OF THE INVENTION
[0047] An embodiment of this invention is directed to a transistor
with Ge.sub.xSi.sub.1-x heterostructure, which can overcome the
limitations described hereinabove so as to further improve its
frequency performance.
[0048] The inventors of this invention recognized that the cause
for HBT transistors deviating from the ideal is because of surface
re-combination phenomena, rather than recombination phenomena
reputedly occurring within the Ge.sub.xSi.sub.1-x
heterostructure.
[0049] Such surface re-combination phenomena have been found to
occur in the neighborhood of the interface between the crystalline
semiconductor substrate, incorporating a HBT transistor, and a thin
layer of silicon dioxide (SiO.sub.2) grown to aid in the formation
of the spacers near an emitter region.
[0050] In one embodiment, the transistor is formed by a process
that includes the steps of: defining a window in the semiconductor
substrate; providing a first implantation of germanium atoms
through said window; providing a second implantation of acceptor
dopants through said window to define a base region; applying an
RTA (Rapid Thermal Annealing) treatment to re-construct the crystal
lattice within the semiconductor substrate comprising a
silicon/germanium alloy; forming a dielectric layer by chemical
vapor deposition; forming spacers at window edges; forming an
emitter region in the substrate through the window; and forming an
emitter contact region.
[0051] The features and advantages of the transistor according to
the invention will be apparent from the following description of an
embodiment thereof, given by way of non-limitative example with
reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0052] FIG. 1 is an enlarged cross-sectional view of a
semiconductor substrate which integrates a high-mobility NPN
transistor with a vertical structure including a Ge.sub.xSi.sub.1-x
heterostructure, according to the prior art.
[0053] FIG. 2 is an energy band plot typical of a high-mobility NPN
transistor;
[0054] FIGS. 3a-3f illustrate conventional process steps yielding
the high-mobility NPN transistor shown schematically in FIG. 1.
[0055] FIG. 4 is a voltage vs. current plot illustrating the
behavior of the base and collector currents for two high-mobility
NPN transistors T1 and T2 with a Ge.sub.xSi.sub.1-x heterostructure
having a ratio At1/At2 of 5 of their respective emitter areas.
[0056] FIG. 5 is an enlarged cross-sectional view of a
semiconductor body of crystalline silicon as implanted to provide a
Ge.sub.xSi.sub.1-x heterostructure, which has been subjected to an
oxidation step for growing a silicon dioxide layer thereon.
[0057] FIG. 6 is a photograph taken by Atomic Force Microscopy
(AFM), which shows an SiO.sub.2/Ge.sub.xSi.sub.1-x interface of a
conventionally made transistor.
[0058] FIG. 7 is a plot illustrating the dependence of surface
roughness at an SiO.sub.2/Ge.sub.xSi.sub.1-x interface on the
amount of germanium segregated in the interface itself.
[0059] FIG. 8 illustrates a similar situation to that of FIG. 7,
but relating to a practical instance of a high carrier mobility
transistor also having an SiO.sub.2/Ge.sub.xSi.sub.1-x
interface.
[0060] FIGS. 9a-9f illustrate the process steps according to this
invention that yield a high-mobility NPN transistor similar to that
shown schematically in FIG. 1.
[0061] FIG. 10 shows an atomic force microphotograph of the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface of an HBT transistor of the
present invention.
[0062] FIG. 11 is a plot showing the behavior of the collector and
base currents versus the base-emitter bias voltage, for profiles of
acceptor impurities in substrates integrating two different types
of HBT transistors.
[0063] FIG. 12 is a plot of the collector current versus the
collector-emitter bias voltage, for two different types of HBT
transistors.
[0064] FIG. 13 is a plot of the concentration FIG. 10 is a
photograph taken by Atomic Force Microscopy (AFM), which shows an
SiO.sub.2/Ge.sub.xSi.sub.1-x interface obtained with the
fabrication process of this invention.
[0065] FIG. 14 is a plot of the cut-off frequency versus the
collector bias current for two different types of HBT
transistors.
DETAILED DESCRIPTION OF THE INVENTION
[0066] The inventors of the present invention have spotted the main
cause of performance deviations from an ideal device which limit,
for example, the performance of a high-mobility HBT transistor, in
the surface re-combination phenomena that appear at the silicon
dioxide-to-germanium/silicon heterostructure,
SiO.sub.2/Ge.sub.xSi.sub.1-- x.
[0067] In order to provide experimental evidence of the above
conclusion, the inventors have conducted a series of atomic force
microscopy (AFM) analyses to photograph the situation at the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface and has gathered useful
elements for evaluation.
[0068] These analyses have shown a situation of the kind
schematically illustrated in FIG. 5, wherein, on a body 30 of
crystalline silicon implanted to produce a Ge.sub.xSi.sub.1-x
heterostructure, a layer 33 of pure germanium develops subsequently
to a step of growing a layer 32 of silicon dioxide on the
crystalline body 30.
[0069] This layer 33 is trapped from beneath by the
Ge.sub.xSi.sub.1-x heterostructure, and from above, by the silicon
dioxide layer 32. This can be explained in theory by that the step
of growing the silicon dioxide (SiO.sub.2) thermally, as carried
out in direct contact with the Ge.sub.xSi.sub.1-x heterostructure,
causes the silicon (Si) atoms present at its top surface to be
depleted upward, thereby promoting the formation of the layer 33 of
pure germanium.
[0070] In so doing, the silicon dioxide layer 32 develops a surface
roughness, due to the underlying germanium layer 33, which is
responsible for the surface re-combination phenomena occurring at
the SiO.sub.2/Ge.sub.xSi.sub.1-x interface.
[0071] This surface roughness is brought out by the atomic force
microphotograph of FIG. 6, showing the surface of the silicon
dioxide layer 32 after the thermal growth process.
[0072] FIG. 7 is a plot showing the linearly increasing dependence
of the amount of segregated germanium in the layer 33 on the
surface roughness (Rms) of the layer 32.
[0073] A similar situation to the above, for an
SiO.sub.2/Ge.sub.xSi.sub.1- -xinterface, is encountered where a
high carrier mobility bipolar transistor (HBT) having a vertical
structure with a Ge.sub.xSi.sub.1-x heterostructure is fabricated
by the process steps described under the Background of the
Invention heading.
[0074] FIG. 8 is a cross-section through the high-mobility
transistor of FIG. 1, with enlarged detail views of the emitter 4
and base 3 regions.
[0075] This figure highlights that the base and emitter regions are
in direct contact with the isolation spacers 50 comprised of a
first thin dielectric layer 12 of silicon dioxide and a second
dielectric layer 14.
[0076] It is to be emphasized, therefore, that a Ge.sub.xSi.sub.1-x
heterostructure is present within the base region 3 whereover the
first thin dielectric layer 12 of silicon dioxide comprising both
isolation spacers 50 has been grown.
[0077] Accordingly, a narrow region of the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface has been marked with a heavy
circle where the presence is displayed of a layer 90 of segregated
germanium resulting from the thermal oxidation process employed for
growing the first thin dielectric layer 12.
[0078] To overcome the drawbacks connected with the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface which limit the performance
of conventional high-mobility transistors (HBT), a process for
fabricating the transistor according to this invention is proposed
herein below with reference to FIGS. 9a-9f.
[0079] For convenient comparison of the present inventive process
with the process described under the Background of the Invention
heading, the same reference numerals have been used to denote
similar items with those shown in FIGS. 1 and 3a-3f.
[0080] FIG. 9a shows a substrate 1 of crystalline silicon (Si),
lightly doped with impurities of the N type and having a bottom
region 5 which is heavily doped with impurities of the N type. This
bottom region 5 corresponds to the ohmic region of a collector
contact (not shown here).
[0081] A window 10 is formed above the substrate 1 by selective
deposition of a protective material 11 over the substrate 1. This
protective material 11 comprises a first layer in direct contact
with the substrate 1 wherein acceptor impurities are embedded and
which is capped by a dielectric material.
[0082] A first step of implanting germanium (Ge) is carried out
through this window 10, followed by a second step of implanting
acceptor impurities, such as boron (B) atoms or BF2+ ions.
[0083] Thereafter, the crystal lattice of the substrate 1 is
re-constructed by an RTA (Rapid Thermal Annealing) process or a
conventional treatment in an oven, also is intended to aid in the
insertion of the implanted atoms into sites left free in the
crystal lattice.
[0084] The outcome of the last-mentioned step is shown in FIG. 9b,
where a planar base region 3, extending at the window 10 to a
sufficient depth in the substrate 1 to allow of the subsequent
creation of an emitter region, is highlighted for the first
time.
[0085] Simultaneously with the definition of the base region 3 in
the substrate 1, a collector region 2 is defined which is included
in the remaining portion, not implanted with acceptor impurities,
of the substrate 1 and, accordingly, also contains the collector
ohmic contact region 5.
[0086] The base region, extending as far as the interface to the
collector region 2, will presently exhibit an energy band curve of
the kind shown in FIG. 2 as a result of a Ge.sub.xSi.sub.1-x
heterostructure having been formed during the first implanting
step.
[0087] At this stage, as shown in FIG. 9c, at the location of the
window 10 and the protective material 11, a first thin dielectric
layer 12' of silicon dioxide (SiO.sub.2) will be formed over the
substrate 1 by chemical vapor deposition (CVD). Other types of CVD,
such as PECVD, APCVD, LPCVD, UV-assisted CVD, could also be
used.
[0088] Unlike the prior art, this thin dielectric layer 12' of
silicon dioxide is formed by a CVD process, not by a thermal growth
process.
[0089] This provides an improved SiO.sub.2/Ge.sub.xSi.sub.1-x
interface, as can be seen in FIG. 10 which shows an atomic force
microphotograph of the SiO.sub.2/Ge.sub.xSi.sub.1-x interface thus
obtained.
[0090] It can be seen that the roughness of the
SiO.sub.2/Ge.sub.xSi.sub.1- -x interface shown in FIG. 10 is
significantly less than that in FIG. 6 where the silicon dioxide
was grown by thermal oxidation.
[0091] Excellent results, as regards to the formation of the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface, were also obtained by
depositing the first thin dielectric layer 12' of silicon dioxide
by an atmospheric pressure chemical vapor deposition (APCVD)
process.
[0092] To further enhance the quality of the interface, and thus
reduce the faults originating local surface re-combination
phenomena, it is contemplated that a thermal process should follow
the deposition of the first thin dielectric layer 12'.
[0093] The process for fabricating a HBT transistor according to
the an embodiment of the invention is carried on through
conventional steps including the deposition of a second dielectric
layer 14 on top of said first thin dielectric layer 12', followed
by the deposition of a polysilicon layer 15.
[0094] In a first alternative embodiment, the second dielectric
layer comprises silicon nitride (Si.sub.3N.sub.4) to ensure proper
adhesion on the underlying dielectric layer 12'.
[0095] Finally, to form an emitter region in the substrate 1, at
the location of the window 10, a first chemio-physical etching
(RIE) step will be carried out on the polysilicon layer 15, and a
second etching step on the second dielectric layer 14, to obtain
the partial formation of isolation spacers at the edges of the
window 10, as shown schematically in FIG. 9d.
[0096] A third, wet etching step carried out on the remaining
portions of the polysilicon layer 15 and a fourth etching step
carried out on just the first thin dielectric layer 12' will
complete the formation of the spacers 50, thereby exposing the base
region 3 again, as shown in FIG. 9e.
[0097] The HBT transistor formed according to the teachings of this
invention can then be completed with conventional processes to form
an emitter region 4 within the base region 2.
[0098] Finally, the emitter region 4 will be overlaid with a
corresponding top emitter contact 9, optimized to enhance the
injection efficiency of the HBT transistor.
[0099] FIG. 9f is a comprehensive view showing the HBT transistor
with a Ge.sub.xSi.sub.1-x heterojunction and the emitter contact 9
comprising a first polysilicon layer 7, heavily doped with
impurities of the N type and capped by a metal layer 8.
[0100] A second alternative embodiment of the inventive process for
fabricating HBT transistors will now be described and comprises
processing steps which are identical with those described above up
to the moment of forming the first thin dielectric layer 12' of
silicon dioxide.
[0101] In this second alternative embodiment, the first thin
dielectric layer of silicon dioxide is replaced by a thick
dielectric layer of silicon dioxide (SiO.sub.2) also deposited by
chemical vapor deposition (CVD).
[0102] In this embodiment, the thick dielectric layer of silicon
dioxide could also be deposited by an APCVD process, followed by an
optional thermal process.
[0103] The steps of the second alternative embodiment of the
fabrication process include: depositing a layer 15 of polysilicon;
etching inside the window region; and forming an emitter region
overlaid by an electric contact, similar to the first embodiment
described.
[0104] Also within the principle of this invention, a third
alternative embodiment of the HBT transistor fabrication process
will now be disclosed which includes the same process steps as
those previously described up to the moment of forming the first
thin dielectric layer 12'.
[0105] In this third alternative embodiment, the first thin
dielectric layer 12' is formed by depositing a sacrificial silicon
(Si) layer and then subjecting it to thermal oxidation. This
sacrificial layer is deposited inside the window region 10 in
direct contact with the Ge.sub.xSi.sub.1-x heterostructure included
in the substrate 1.
[0106] Advantageously, the process steps described for forming the
first thin dielectric layer 12' by a sacrificial layer will yield
the same results, in terms of quality of the
SiO.sub.2/Ge.sub.xSi.sub.1-x interface, as were obtained previously
by forming the layer 12' with a chemical vapor deposition (CVD)
process.
[0107] It has been found that the sacrificial layer deposited
inhibits the formation of the occluded germanium layer between the
heterostructure and the first thin dielectric layer 12' because it
prevents the oxidation process from reaching the Ge.sub.xSi.sub.1-x
heterostructure.
[0108] In order to further minimize the surface re-combination
phenomena that occur at the SiO.sub.2/Ge.sub.xSi.sub.1-x interface,
the third alternative embodiment of the process may also have the
step of forming the thin dielectric layer 12' followed by a
suitable thermal treatment.
[0109] The steps of the third alternative embodiment of the HBT
transistor fabrication process will then include: depositing a
second dielectric layer 14; depositing a layer 15 of polysilicon;
etching inside the window region; and forming an emitter region
overlaid by an electric contact, similar to the first embodiment
described.
[0110] To improve the adhesion of the second dielectric layer 14 on
the first thin dielectric layer 12', the second dielectric layer
may comprise silicon nitride (Si.sub.3N.sub.4).
[0111] Again within the principle of this invention, a fourth
alternative embodiment of the HBT transistor fabrication process is
provided which includes processing steps identical with those
previously described in relation to the third alternative
embodiment up to the moment when the first thin dielectric layer
12' is formed.
[0112] In this embodiment, the first dielectric layer of silicon
dioxide is further grown thermally to provide a dielectric layer of
increased thickness embedding, or replacing, the second dielectric
layer 14.
[0113] In order to minimize the surface re-combination phenomena
that occur at the SiO.sub.2/Ge.sub.xSi.sub.1-x interface, the
fourth alternative embodiment of the HBT transistor fabrication
process may also have the oxidation step followed by a suitable
thermal treatment.
[0114] The next steps of the fourth alternative embodiment of the
fabrication process will include: depositing a layer 15 of
polysilicon; etching inside the window region; and forming an
emitter region overlaid by an electric contact, similar to the
second embodiment described.
[0115] Advantageously, by adopting the fabrication processes of
this invention, the technical problem of the base current deviating
from the ideal in HBT transistors can be solved.
[0116] The truth of this statement is brought out by the graph in
FIG. 11 which illustrates the behavior of the collector (Ic) and
base (IB) currents versus bias voltage (Vbe), as applied between
the base and the emitter, for two HBT transistors having the same
emitter surface area but formed with different fabrication methods.
In fact, two patterns can be distinguished on this graph: the one
(broken line) associated with the HBT transistor which has the
dielectric layer 12 grown by thermal oxidation, and the other (full
line) associated with the HBT transistor formed by the process of
this invention with the dielectric layer 12' deposited by CVD.
These two patterns nearly match each other, and this match reveals
a marked reduction in the deviation of the base current from the
ideal.
[0117] FIG. 12 shows, for the same types of HBT transistors as
above, the behavior of their respective collector currents (Ic)
versus the bias voltage (Vce) across the collector and emitter.
[0118] It is evinced from this graph that, for HBT transistors
fabricated by the process of the invention (full line curve), a
significant increase occurs in the variation percent of the current
gain versus the collector current. It should be also emphasized
that these transistors have lower saturation voltage values,
thereby affording lower power consumption.
[0119] Another advantage of the fabrication process of this
invention or its first embodiment (CVD deposition of the layer 12')
is that it involves relatively low deposition temperatures. This
prevents back diffusion of the implanted acceptor impurities,
thereby avoiding an oxidation-enhanced diffusion of boron and
further raising the cut-off frequency of the HBT transistor
fabricated by the process of this invention.
[0120] A confirmation of the above statements can be found in the
graphs of FIG. 13 and FIG. 14 which show, for the two types of HBT
transistors described above, the concentration profile of the
acceptor impurities versus depth into the substrate and the
behavior of the cut-off frequency versus the collector bias
current.
[0121] Finally, notice that collector bias currents in the
milliampere range allow HBT transistors fabricated with the
invention process to attain cut-off frequencies in the 20 GHz
range, that is hitherto unattainable values.
[0122] In conclusion, the fabrication process of this invention
allows the frequency field of application of HBT transistors to be
further extended, while eliminating deviations of the base current
from the ideal.
[0123] From the foregoing it will be appreciated that, although
specific embodiments of the invention have been described herein
for purposes of illustration, various modifications may be made
without deviating from the spirit and scope of the invention.
Accordingly, the invention is not limited except as by the appended
claims.
[0124] All of the above U.S. patents, U.S. patent application
publications, U.S. patent applications, foreign patents, foreign
patent applications and non-patent publications referred to in this
specification and/or listed in the Application Data Sheetare
incorporated herein by reference, in their entirety.
* * * * *