U.S. patent application number 10/175839 was filed with the patent office on 2003-12-25 for structure of discrete nrom cell.
Invention is credited to Chang, Kent Kuohua, Lai, Erh-Kun.
Application Number | 20030234421 10/175839 |
Document ID | / |
Family ID | 29733989 |
Filed Date | 2003-12-25 |
United States Patent
Application |
20030234421 |
Kind Code |
A1 |
Chang, Kent Kuohua ; et
al. |
December 25, 2003 |
STRUCTURE OF DISCRETE NROM CELL
Abstract
A discrete NROM cell, at least comprising: a substrate; a first
ONO stacking gate and a second ONO stacking gate over the
substrate, wherein the ONO stacking gate is a structure having a
nitride layer between two oxide layers; an oxide layer formed over
the substrate covering the first and second ONO stacking gates; a
polysilicon layer formed over the oxide layer; and the source/drain
implanted in the substrate and next to the ONO stacking gates. The
structure of discrete NROM cell of the invention can solve the
problem of the electrons being trapped in the nitride layer of NROM
cell, and also control the source/drain implant and ONO structure
at precisely symmetrical positions.
Inventors: |
Chang, Kent Kuohua; (Taipei,
TW) ; Lai, Erh-Kun; (Taichung, TW) |
Correspondence
Address: |
RABIN & CHAMPAGNE, PC
1101 14TH STREET, NW
SUITE 500
WASHINGTON
DC
20005
US
|
Family ID: |
29733989 |
Appl. No.: |
10/175839 |
Filed: |
June 21, 2002 |
Current U.S.
Class: |
257/324 ;
257/E21.423; 257/E21.679; 257/E27.103; 257/E29.309 |
Current CPC
Class: |
H01L 29/792 20130101;
H01L 27/115 20130101; H01L 27/11568 20130101; H01L 29/66833
20130101 |
Class at
Publication: |
257/324 |
International
Class: |
H01L 029/788 |
Claims
What is claimed is:
1. A structure of discrete NROM cell, at least comprising: a
substrate; a plurality of ONO stacking gates over the substrate,
wherein the ONO stacking gate is a structure having a nitride layer
between two oxide layers; an oxide layer formed over the substrate
and covering the ONO stacking gates; a polysilicon layer formed
over the oxide layer; and a plurality of source/drain implanted in
the substrate and next to the ONO stacking gates.
2. The structure of discrete NROM cell according to claim 1,
wherein the ONO stacking gate includes a top oxide layer, a nitride
layer, and a bottom oxide layer.
3. The structure of discrete NROM cell according to claim 2,
wherein the thickness of the nitride layer ranges from about 20
.ANG. to 150 .ANG..
4. The structure of discrete NROM cell according to claim 2,
wherein the thickness of the bottom oxide layer ranges from 50
.ANG. to 150 .ANG..
5. The structure of discrete NROM cell according to claim 4,
wherein the bottom oxide layer is preferably about 70 .ANG..
6. The structure of discrete NROM cell according to claim 1,
wherein the polysilicon layer is doped by phosphorus or arsenic
ions.
7. The structure of discrete NROM cell according to claim 1,
wherein the source/drain of NROM cell is a concentration of P-type
dopant.
8. The structure of discrete NROM cell according to claim 7,
wherein the P-type dopant is Boron or BF.sub.2.sup.+.
9. The structure of discrete NROM cell according to claim 1,
wherein the source/drain of NROM cell is a concentration of N-type
dopant.
10. The structure of discrete NROM cell according to claim 9,
wherein the N-type dopant is phosphorous or arsenic ions.
11. A discrete NROM cell, at least comprising: a substrate; a first
ONO stacking gate and a second ONO stacking gate over the
substrate, wherein the ONO stacking gate is a structure having a
nitride layer between two oxide layers; an oxide layer formed over
the substrate and covering the first ONO stacking gate and the
second ONO stacking gate; a polysilicon layer formed over the oxide
layer; and a source/drain implanted in the substrate and next to
the first ONO stacking gate and the second ONO stacking gate.
12. The discrete NROM cell according to claim 11, wherein the ONO
stacking gate includes a top oxide layer, a nitride layer, and a
bottom oxide layer.
13. The discrete NROM cell according to claim 11, wherein the
polysilicon layer is doped by phosphorus or arsenic ions.
14. The discrete NROM cell according to claim 11, wherein a first
bit and a second bit are in the virtual position of the first ONO
stacking gate and the second ONO stacking gate, respectively.
15. The discrete NROM cell according to claim 12, wherein the
thickness of the nitride layer ranges from about 20 .ANG. to 150
.ANG..
16. The structure of discrete NROM cell according to claim 12,
wherein the thickness of the bottom oxide layer ranges from 50
.ANG. to 150 .ANG..
17. The structure of discrete NROM cell according to claim 11,
wherein the source/drain of NROM cell is a concentration of P-type
dopant.
18. The structure of discrete NROM cell according to claim 17,
wherein the P-type dopant is Boron or BF.sub.2.sup.+.
19. The structure of discrete NROM cell according to claim 11,
wherein the source/drain of NROM cell is a concentration of N-type
dopant.
20. The structure of discrete NROM cell according to claim 19,
wherein the N-type dopant is phosphorous or arsenic ions.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates in general to a structure of nitride
read-only memory (NROM) cells, and more particularly to the
structure of discrete NROM cell fabricated according to the
self-aligned process.
[0003] 2. Description of the Related Art
[0004] The memory devices for non-volatile storage of information,
such as read only memory (ROM), programmable read only memory
(PROM), erasable programmable read only memory (EPROM), and other
advanced memory devices, are currently used in the worldwide
industries. The other advanced memory devices that involve more
complex processing and testing procedures include electrically
erasable programmable read only memory (EEPROM), flash EEPROM, and
nitride read-only memory (NROM). These advanced memory devices can
accomplish the tasks that ROM can't do. For example, using EEPROM
devices in circuitry permits in-circuit erasing and reprogramming
of the device.
[0005] The main characteristic of NROM is dual bit cells having
multiple threshold voltage levels, where every two threshold
voltage levels together store a different bit. Others store one bit
on either side of the cell. The conventional structures and
fabricating methods of NROM cell are described in a lot of articles
and references.
[0006] FIG. 1 is a cross-sectional view of a conventional NROM
cell. The substrate 10 is implanted with a source 12 and a drain
14. The top of substrate 10 lies an ONO structure, having a nitride
layer 17 between a top oxide layer 16 and a bottom oxide layer
(tunneling oxide layer) 18. A numbers of BD (buried diffusion)
oxide 20 are formed to isolate the adjacent ONO structure and form
the channels 22. The conventional structure of NROM cell in which
contains dual bit in one cell is also depicted in FIG. 1. The
larger region (encircled with the dashed line) denotes a NROM cell
30, and the two smaller regions encircled with the dashed line
denote the first bit 32 and the second bit 34.
[0007] In the NROM cell, the nitride layer 17 provides the charge
retention mechanism for programming the memory cell. Under normal
condition, the electrons are introduced into the nitride layer 17
during programming of the cell, while the holes are introduced into
the nitride layer 17 to neutralize or combine the electrons during
erasing of the cell. However, nitride tends to trap electrons that
are introduced in the nitride layer 17 due to its property. If the
electrons trapped in the nitride layer 17, the cell is under
programming.
[0008] Additionally, according to the hot electron injection
phenomenon, some hot electrons will penetrate through the bottom
oxide layer 18, especially when it is thin, and then collected in
the nitride layer 17. Concentrated charge caused by the hot
electrons significantly raises the threshold voltage of the portion
of the channel 22 under charge to be higher than the threshold
voltage of the remaining portion of the channel 22. When the cell
is programmed, the concentrated charge is presented and the raised
threshold voltage does not permit the cell to the conductive state.
In a normal state, which the concentrated charge is not presented,
the reading voltage over the channel can overcome the threshold
voltage of the channel 22 and consequently the channel 22 is
conductive.
[0009] Moreover, the conventional NROM cell is generally fabricated
by photolithography, and has the drawback. For example, the implant
and the bits are not easily formed at the right position could be
shifted, so that the efficiency of the NROM cell is decreased.
SUMMARY OF THE INVENTION
[0010] It is therefore an object of the invention to provide a
structure of discrete NROM cell, so that the symmetrical positions
of the source/drain implant and ONO structure can be precisely
controlled.
[0011] The invention achieves the above-identified objects by
providing a discrete NROM cell, at least comprising: a substrate; a
first ONO stacking gate and a second ONO stacking gate over the
substrate, wherein the ONO stacking gate is a structure having a
nitride layer between two oxide layers; an oxide layer formed over
the substrate and covering the first and second ONO stacking gates;
a polysilicon layer formed over the oxide layer; and the
source/drain implanted in the substrate and next to the ONO
stacking gates.
[0012] Other objects, features, and advantages of the invention
will become apparent from the following detailed description of the
preferred but non-limiting embodiments. The following description
is made with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 (prior art) is a cross-sectional view of a
conventional NROM cell;
[0014] FIG. 2A-FIG. 2F illustrate the method of fabricating the
discrete NROM cell by self-aligned process according to the first
embodiment of the invention;
[0015] FIG. 2G is a cross-sectional view of the discrete NROM cell
fabricated according to the first embodiment of the invention;
[0016] FIG. 3A-FIG. 3F illustrate the method of fabricating the
discrete NROM cell by self-aligned process according to the second
embodiment of the invention; and
[0017] FIG. 3G is a cross-sectional view of the discrete NROM cell
fabricated according to the second embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0018] The discrete NROM cell of the invention is fabricated by the
self-aligned process. Two slightly different procedures are taken
for illustrated in the disclosed embodiments. Also, to avoid
obscuring the invention, well-known elements not directly relevant
to the invention are not shown or described. Accordingly, the
specification and the drawing are to be regard as an illustrative
sense rather than a restrictive sense.
[0019] Method 1 for Fabricating NROM Cell
[0020] FIG. 2A-FIG. 2F illustrate the method of fabricating the
discrete NROM cell by self-aligned process according to the first
embodiment of the invention. In FIG. 2A, a substrate 210 is
provided and an ONO layer is formed thereon. The ONO layer includes
a bottom oxide layer (tunneling oxide layer) 218 grown on the
substrate 210, a nitride layer 217 deposited over the bottom oxide
layer 218, and a top oxide layer 216 produced on the nitride layer
217. Then, a patterned photo-resist (PR) 219 is formed over the top
oxide layer 216.
[0021] The thickness of the bottom oxide layer 218 typically ranges
from 50 .ANG. to 150 .ANG., and preferably about 70 .ANG.. The
thickness of the nitride layer 217 typically ranges from 20 .ANG.
to 150 .ANG.. The thickness of the top oxide layer 216 is not
limited since it will be removed in the following procedures.
However, it will be appreciated that the thickness of ONO layer are
generally independent of each other, and variable depending on the
field of NROM cell application.
[0022] Next, the top oxide layer 216 is etched according to the
patterned PR 219. The top oxide under the patterned PR 219 remains
on while the others not be covered are etched away. Then, the
patterned PR 219 is removed as shown in FIG. 2B.
[0023] As illustrated by FIG. 2C, a film is then formed over the
top oxide layer 216 and portion of the nitride layer 217 by
conformal deposition. Subsequently, the film is etched by
anisotropic etching process, and the spacers 221 are formed on the
sides of the discrete top oxide layer 216. The film could be any
material that can be differentiated from Nitride, such as oxide or
polysilicon. Also, it is noted that the bottom width of the spacer
221 is controlled at a predetermined value (d).
[0024] Then, the source/drain 222 are implanted by self-aligned
process. The source/drain 222 is a concentration of N-type dopant
such as phosphorous or arsenic ions, or P-type dopant such as boron
or boron fluoride ions(BF.sub.2.sup.+).
[0025] In FIG. 2D, the top oxide layer 216 and the nitride layer
217 are removed sequentially. The nitride sheltered by the spacers
221 remains on the bottom oxide while the other portions not
covered by are etched away. Then, the spacers 221 are removed,
after that, the bottom oxide 218 is removed according to remaining
nitride 217, as shown in FIG. 2E.
[0026] As far as the process describe, the nitride layer 217 and
the bottom oxide layer 218 have been etched and formed as a
plurality of stacking gates. In FIG. 2F, an oxide layer 226 is
formed over the substrate 210, thereby the spaces between the
discrete stacking gates are filled with the oxide, also the ONO
stacking gates are fully covered.
[0027] Following oxide deposition, a polysilicon layer 228 is
formed over the oxide layer 226 as a wordline. The polysilicon
layer 228 can be amorphous silicon, or doped polysilicon that is
doped by phosphorous or arsenic ions. Also, in the particular
process, the Tungsten Silicide (WSi.sub.x) is subsequently
deposited over the polysilicon layer 228 (not shown in FIG. 2F).
The discrete NROM cell is then finished.
[0028] Structure of NROM Cell in the First Embodiment
[0029] FIG. 2G is a cross-sectional view of the discrete NROM cell
fabricated according to the first embodiment of the invention. The
substrate 210 is implanted with the source/drain 222. The narrow
stacking gate forming on the top of substrate 210 is an ONO layer
having the nitride layer 217 between the oxide layer 216 and the
bottom oxide layer 218. Also, the ONO stacking gates are separated
by the oxide layer 226; consequently, the discrete structure of
NROM cell is created. The oxide layer 226 is further capped by the
polysilicon layer 228. The larger encircled region denotes a NROM
cell 230, and the two smaller encircled regions denote the first
bit 232 and the second bit 233. Two bits are controlled at a
predetermined width (d). Also, the source/drain 222 is implanted by
self-aligned process and the following steps are also performed by
self-aligned process. Therefore, the symmetrical position of the
source/drain 222 and the ONO layer can be easily and precisely
controlled.
[0030] Method 2 for Fabricating NROM Cell
[0031] FIG. 3A-FIG. 3F illustrate the method of fabricating the
discrete NROM cell by self-aligned process according to the second
embodiment of the invention. The fabricating method of the second
embodiment is mostly the same as that of the first embodiment, but
some of steps are slightly modified or changed in different
orders.
[0032] The drawing of FIG. 3A is identical with FIG. 2A. In FIG.
3A, a substrate 310 is first provided and a ONO structure including
a top oxide layer 316, a nitride layer 317, and a bottom oxide
layer (tunneling oxide layer) 318 is formed thereon. Then, a
patterned photo-resist (PR) 319 is formed over the top oxide layer
316. Similarly, the thickness of three layers of ONO structure are
generally independent of each other, and variable depending on the
field of NROM cell application.
[0033] The top oxide layer 316 is etched according to the patterned
PR 319. After that, the source/drain 322 are implanted by
self-aligned process. The source/drain 322 is typically boron (B)
or BF.sub.2.sup.+. Then, the patterned PR 319 is de-scummed for
exposing the portion of the top oxide layer 316 at the
predetermined width of d, as illustrated in FIG. 3B.
[0034] The top oxide layer 316 is then etched according to the PR
descum, and followed by removing PR 319, as shown in FIG. 3C.
[0035] As illustration of FIG. 3D, a film is then formed over the
top oxide layer 316 and the portion of the nitride layer 317 by
conformal deposition. Subsequently, the film is etched by
anisotropic etching process, and the spacers 321 are formed on the
sides of the discrete top oxide layer 316. The film could be any
material that can be differentiated from Nitride, such as oxide or
polysilicon. Also, it is noted that the bottom width of the spacer
321 is controlled at the predetermined value of d.
[0036] Next, the discrete top oxide layer 316 is removed. The
nitride layer 317 is then etched according to the spacer 321. The
nitride sheltered by the spacers 321 remains on the bottom oxide
layer 318 while the other portion not covered by is etched away.
The spacers 321 are then removed, as shown in FIG. 3E.
Subsequently, the bottom oxide layer 318 is etched according to the
remained nitride layer 317, and a plurality of ONO stacking gates
are formed.
[0037] Then, an oxide layer 326 is formed over the substrate 310
and covers the ONO stacking gates.
[0038] Then, the oxide layer 326 is capped with a polysilicon layer
328, as shown in FIG. 3F. The discrete NROM cell is then
finished.
[0039] Structure of NROM Cell in the Second Embodiment
[0040] FIG. 3G is a cross-sectional view of the discrete NROM cell
fabricated according to the second embodiment of the invention. The
substrate 310 is implanted with the source/drain 322. Numerous
narrow stacking gates forming on the top of substrate 310 are ONO
structures having the nitride layer 317 between the oxide layer 316
and the bottom oxide layer 318. Also, the ONO stacking gates are
separated by the oxide layer 326; consequently, the discrete
structure of NROM cell is created. The oxide layer 326 is further
capped by the polysilicon layer 328. The larger encircled region
denotes a NROM cell 330, and the two smaller encircled regions
denote the first bit 332 and the second bit 333. Two bits are
controlled at the predetermined width of d. Also, the source/drain
322 is implanted by self-aligned process and the following steps
are also performed by self-aligned process. Therefore, the
symmetrical position of the source/drain 322 and the ONO stacking
gate can be easily and precisely controlled.
[0041] While the invention has been described by way of examples
and in terms of the preferred embodiments, it is to be understood
that the invention is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *