U.S. patent application number 10/140718 was filed with the patent office on 2003-11-13 for self timed pre-charged address compare logic circuit.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Pelella, Antonio R..
Application Number | 20030210134 10/140718 |
Document ID | / |
Family ID | 29399489 |
Filed Date | 2003-11-13 |
United States Patent
Application |
20030210134 |
Kind Code |
A1 |
Pelella, Antonio R. |
November 13, 2003 |
SELF TIMED PRE-CHARGED ADDRESS COMPARE LOGIC CIRCUIT
Abstract
An Address Compare Circuit (1) allows for a large compare
function at high speed due to its unique self-timed evaluation
clock and bit compare circuits. The address compare circuit can
reliably self-time off of the input data which insures proper
compare timing with respect to the arrival of two address busses
being compared. The HIT evaluation clock is generated by a circuit
that has additional control inputs to increase the arrival times of
input data, resulting in a greater operating window. This circuit
provides a way to generate a very accurate internal HIT evaluation
clock; therefore, the compare circuit reduces the extra setup time
needed to guarantee all address data bits are valid. Furthermore,
the HIT evaluation clock can be delayed to increase the arrival
times of input data, resulting in a greater operating window.
Inventors: |
Pelella, Antonio R.;
(Highland Falls, NY) |
Correspondence
Address: |
Lynn L. Augspurger
IBM Corporation
2455 South Road, P386
Poughkeepsie
NY
12601
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
29399489 |
Appl. No.: |
10/140718 |
Filed: |
May 8, 2002 |
Current U.S.
Class: |
340/146.2 |
Current CPC
Class: |
G05B 1/00 20130101 |
Class at
Publication: |
340/146.2 |
International
Class: |
G05B 001/00 |
Claims
What is claimed is:
1. An address compare circuit for comparing plural bit addresses,
comprising: a self timed address compare circuit including an
address input HIT clock circuit for providing a self-timed clock
signal off of input data having a bit from each address input to
the input HIT clock circuit, and a bit compare circuit activated
upon arrival of incoming addresses to be compared and comparing
bits of said addresses, and a compare evaluation circuit for timing
of a HIT evaluation clock signal, and a receiver for receiving the
output of said compare evaluation circuit, whereby data clocking is
reliably self-timed off of the input data insuring proper compare
timing with respect to the arrival of the addresses being compared
to generate an accurate internal HIT evaluation clock signal.
2. The address compare circuit according to claim 1 wherein said
HIT evaluation clock signal can be delayed to increase the arrival
times of input data and resulting in a greater operating
window.
3. The address compare circuit according to claim 2 wherein the
input data normally is return-to-zero dynamic data at the end of
each cycle; and if the inputs originate as static inputs to the
compare circuit, then these static inputs are first preconditioned
at the input so when they arrive at the bit compare circuitry, they
have a "return-to-zero" characteristic at the end of each
cycle.
4. The address compare circuit according to claim 3 wherein a hit
evaluation clock signal which is generated in said Hit clock
circuit using the rising edges of the input data, said hit
evaluation clock signal being used to trigger an evaluation of the
compare circuit, said Hit Clock circuit tracking any compare
circuit delay by mimicking an actual compare circuit with similar
transistor topologies.
5. The address compare circuit according to claim 4 wherein said
bit compare circuit has a open drain output connection and equates
a plurality of addresses at a time.
6. The address compare circuit according to claim 4 wherein the
self-timed hit evaluation clock signal which is generated by the
rising edges of the input data by said evaluation clock circuit
which also tracks the compare circuit delay even when simulation
models have wide tolerance's.
Description
FIELD OF THE INVENTION
[0001] The present invention generally relates to an address
compare circuit to test the equivalence of two addresses each made
up of the same number of bits. Furthermore, the speed at which this
compare is performed is of the highest priority.
[0002] Trademarks: IBM is a registered trademark of International
Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may
be registered trademarks or product names of International Business
Machines Corporation or other companies.
BACKGROUND
[0003] In computer design, it is common to compare two addresses in
order to determine the validity of a preceding or subsequent
operation. For example, the address (of a portion of data needed to
execute an instruction) is compared to an address stored in a
directory register to determine if a local Cache SRAM is holding a
copy of the data.
[0004] In general, there are two primary ways to implement the
compare logic:
[0005] 1. Bit-by-bit compare, then "AND" each Bit-by-bit compare
together: Before a compare operation begins, the output of the
compare circuit indicates a mismatch or "MISS" state. Once the
operation begins, the two addresses are compared "bit by bit".
Next, each bit compare is "ANDed" together forming a "AND" tree
usually taking 2 or more stages. If the address is the same, the
compare circuit indicates a match (or "HIT"). Otherwise an inactive
state or "MISS" is indicated by the compare circuit.
[0006] 2. Bit-by-bit miscompare, then "OR" each Bit-by-bit
miscompare together: Before a compare operation begins, the output
of the compare circuit indicates a match or "HIT" state. Once the
operation begins, the two addresses are compared "bit by bit".
Next, each bit miscompare is "ORed" together forming a "OR" tree
usually taking 2 or more stages. If the address is the same, the
compare circuit output will maintain the a match (or "HIT").
Otherwise an MISS" is indicated by the compare circuit.
[0007] The disadvantage of first method is the "AND" logic uses
series transistors which tend to be slow to operate. Although, this
method can use traditional static CMOS logic gates which are
relatively easy to implement, the speed disadvantage is hard to
over come.
[0008] The disadvantage of the second method is the compare circuit
indicates a "HIT" prior to the actual compare operation. For,
example, if downstream logic is dynamic in nature, dynamic logic
may not tolerate a HIT at its inputs during its pre-charge. This
overlap of signals or "collision" can cause false HIT related
operations to occur. Nevertheless, the "OR" logic is preferred,
since it uses parallel transistors and tend to operate quickly.
[0009] To take advantage of the second method's speed while
avoiding the collision problems, a HIT evaluation clock (HIT clock)
is introduced. The HIT clock is used to trigger the last stage of
the "OR" tree. As a result, the compare circuit output will start
in the MISS state and will only switch to the HIT state when both
addresses match and the HIT clock is active. However, the timing of
the HIT clock is not easily accomplished.
[0010] Generally, in there patented art, U.S. Pat. No. 6,353,558,
it is noted that specifically describes a method for reading and
writing a memory array during the same clock cycle with the same
decoded address. The present invention, which is concerned mainly
with the self timed nature of a high-speed compare function differs
and the "to compare" function is not addressed in this art, and
furthermore, the preferred embodiment provides new self timed
features which allow for higher speed operation.
[0011] Another patent, specifically U.S. Pat. No. 6,055,611,
generally relates to the enabling of memory cells and more
particularly relates to effectively replacing defective portion of
memory array with despair portion, again does not address the
preferred embodiment features, no how the self timed compare
function is achieved, nor how the self timed features allows for
higher speed operation. This is also true of U.S. Pat. No. 5765194
which generally relates to a compare circuit and to timing between
an address "MISS" and with a "forced" MISS.
SUMMARY OF THE INVENTION
[0012] The preferred embodiment of the invention provides an
improvement in an address compare circuits and provides a compare
circuit that can reliably self-timed off of the input data insuring
proper compare timing with respect to the arrival of the two
addresses being compared. This circuit provides a way to generate a
very accurate internal HIT evaluation clock; therefore, the compare
circuit reduces the extra setup time needed to guarantee all
address data bits are valid. Furthermore, the HIT evaluation clock
can be delayed to increase the arrival times of input data,
resulting in a greater operating window.
[0013] Also, the improved address compare circuit of the preferred
embodiment allows for large "OR" structures which reduce circuit
stages resulting in faster overall circuit performance.
Furthermore, when the number of bits being compared is increased,
the overall delay increase is marginal due to the "OR"
structures.
[0014] The present invention primarily uses dynamic input data
(i.e. the inputs "return-to-zero" at the end of each cycle);
however, if the inputs originate as "static" inputs to the compare
circuit, then these static inputs are first preconditioned at the
input receiver (i.e. a input repowering circuit), so when they
arrive at the compare circuitry, they now have the necessary
characteristic of a "return-to-zero" at the end of each cycle.
[0015] This preferred embodiment lends itself to very large compare
compare operations (60 inputs and grater) with only marginal delay
increase when the number of bits being compared is increased. There
is use of dynamic input data, (i.e. "return-to-zero" at the end of
each cycle); however, if the inputs originate as "static" inputs to
the Compare circuit, then these static inputs are first
preconditioned at the input receiver (i.e. re-buffering circuit),
so when they arrive at the Compare circuit, they now have the
necessary characteristic of a "return-to-zero" at the end of each
cycle. The self-timed hit evaluation clock, which is generated by
the rising edges of the input data, triggers an evaluation of the
compare circuit. This evaluation clock circuit is designed is such
a way so that it tracks the compare circuit delay even when
simulation models have wide tolerances. This is accomplished by
mimicking the actual compare circuit with similar transistor
topologies.
[0016] These and other improvements are set forth in the following
detailed description. For a better understanding of the invention
with advantages and features, refer to the description and to the
drawings.
DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 illustrates the overall address compare circuit used
in the present invention.
[0018] FIG. 2 illustrates the overall compare circuit with
individual functions isolated for clarity
[0019] FIG. 3 illustrates the "bit compare" circuit used in the
present invention.
[0020] FIG. 4 illustrates the "compare evaluation circuit" circuit
used in the present invention.
[0021] FIG. 5 illustrates the "HIT clock" circuit used in the
present invention.
[0022] FIG. 6 illustrates the "receiver" circuit used in the
present invention.
[0023] The detailed description explains the preferred embodiments,
together with advantages and features, by way of example with
reference to the drawings.
DETAILED DESCRIPTION OF THE INVENTION
[0024] With reference to FIG. 1, an address compare circuit is
shown, and for this discussion, two "32 bit wide" addresses, each
having a true and complement component (i.e. A_t<0:31>,
A_c<0:31>, and B_t<0:31>, B_c<0:31>) are being
compared. If both addresses match, a "HIT" signal is indicated at
the output of the compare circuit (HIT_OUT).
[0025] compare operation occurs, as will be illustrated in FIG. 2
with with the major components highlighted for clarity, as
follows:
[0026] At the beginning of an evaluation cycle the nodes labeled
HIT1 and HIT2 are pre-charged to the "match" or "HIT" state by the
reset clock "CK_RS.sub.--2" 5. If the nodes HIT1 and HIT2 remain
high ("1") when the HIT clock ("HIT_CLOCK.sub.--2") switches to a
"1", the result is an address match or "HIT". On the other hand, if
HIT1 or HIT2 have been pulled "low" due to an address miscompare,
the output "HIT_OUT" 7 will stay low (indicating a MISS).
[0027] The arrival of the incoming addresses is detected by the
low-to-high transitions of the address data bits (i.e. either the
true or complement of each bit will make a low-to-high transition
every cycle). This will start the "bit compare" function 3 and the
generation of the HIT clock "HIT_CLOCK.sub.--2". Only one bit from
each address A & B, are used as the inputs to the HIT clock
circuitry 2.
[0028] Each "bit compare" circuit has a "open drain" output
connection to the HIT.sub.--1 & HIT.sub.--2 lines 4; therefore,
a 32 bit compare has eight "open drain" NFETS 4 connected to HIT1
and eight NFETS connected to HIT2. The "bit compare" schematic,
shown in detail in FIG. 3, compares two address bits at a time for
the purpose of illustration in the embodiment. However, it could
easily be extended to a 4 or 8 way compare. Consequently,
(referring to FIG. 3) if a miscompare is detected, the open drain
output transistor, will pull the output voltage "HIT1" down to the
"0" or ground state.
[0029] It should be noted that the open drain feature of the bit
compare circuit for the self-timed address circuit that allows for
large "OR" structures which reduce circuit stages resulting in
faster overall circuit performance. Furthermore, this bit compare
circuit experiences only marginal delay increases when the number
of bits being compared are increased.
[0030] Referring to FIG. 2, if bit 0 or bit 1 . . . or bit 31 (from
Address A) matches with its corresponding bits from "Address B",
the assumed HIT is correct. This results in a HIT signal at the
output 7 "HIT_OUT". The exact timing of the HIT signal is
controlled by the arrival of the HIT clock signal
(HIT_CLOCK.sub.--2) at the compare evaluation circuit 8. Likewise,
if addresses A & B do not match, a MISS signal is maintained at
the output "HIT_OUT" (the initial pre-charged state of the
output).
[0031] The compare evaluation circuit is comprised of a "AND"
function 7, and its three inputs: HIT.sub.--1, HIT.sub.--2, &
HIT_CLOCK.sub.--2. Notice HIT.sub.--1 & HIT.sub.--2 are
connected to a parallel latch 5 to hold the results of individual
miscompare operations, whereas, HIT_CLOCK.sub.--2 uses a series
latch 6. The compare evaluation circuit is shown in detail in FIG.
4. The input latches 5 & 6 serve to hold the current state of
HIT.sub.--1, HIT.sub.--2, & HIT_CLOCK.sub.--2 until the next
evaluation cycle. At that time, a reset clock "CK_RS.sub.--1" will
arrive to reset HIT.sub.--1, HIT.sub.--2, & HIT_CLOCK.sub.--2
to their stand-by state ("1" or high state) and the "HIT_OUT" to
the "0" or MISS state.
[0032] Referring to FIG. 2, the HIT evaluation clock
"HIT_CLOCK.sub.--1", is generated by the rising edges of the input
address. The HIT evaluation clock circuitry 2 uses one input from
each address A and B. This guarantees that the HIT evaluation clock
"HIT_CLOCK.sub.--1" will wait until both addresses have arrived.
The speed of the HIT clock circuitry is important because it must
track with the bit compare circuits 3 under a wide range of
environmental and manufacturing tolerance's. This is accomplished
by mimicking the actual bit compare circuits with similar
transistor topologies and equivalent FET loading on the
HIT_CLOCK.sub.--1 and HIT.sub.--1 & HIT.sub.--2 nodes. The
detail implementation of the HIT clock circuitry is shown in FIG.
5. Again referring to FIG. 2, the circuit delay from the arrival of
address data to the active signal edge of HIT_CLOCK.sub.--1
(high-to-low transition) is nearly equal to the high-to-low
transition of HIT.sub.--1 & HIT.sub.--2 during a miscompare.
Ideally, this coincident timing relationship could be enough to
perform a successful address compare function. However, due to
tolerance and mis-tracking of device characteristics during normal
manufacturing processes, such ideal situations seldom occur. To
allow more timing margin between HIT_CLOCK.sub.--1 and HIT.sub.--1
& HIT.sub.--2, a series latch 6 is added to HIT_CLOCK.sub.--1.
The extra inverter delay through the latch creates the signal
HIT_CLOCK.sub.--2, which is then used to evaluate HIT.sub.--1 &
HIT.sub.--2. Furthermore, If tracking is still a problem, four
programmable delay inputs (HIT_DELAY.sub.--0, 1, 2, & 3) are
included to slow down the HIT_clock. These delay inputs can be
adjusted externally during testing or system operation.
[0033] To create a reliable self-timed evaluation clock triggered
off of the input data, only input signals that "return to zero"
(i.e. return to the "non-asserted" state at the end of every
cycle), are allowed to enter the bit compare circuits. If the
inputs originate as "static" signals, they are first preconditioned
at the input receiver, so when they arrive at the compare circuit,
they have the necessary characteristic of a "return-to-zero" at the
end of each cycle. This guarantees that no collisions will occur
during pre-charge at the beginning of the next new cycle. FIG. 6,
shows the input receiver circuit used to convert static signals to
"return-to-zero" signals. The static input "STATIC_DATA" is "ANDed"
together with the pulsed system clock "CK_SYSTEM". The result, are
outputs DATA_T, & DATA_C that have the desired
characteristic.
[0034] While the preferred embodiment to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvements and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
* * * * *