Pelella; Antonio R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pelella; Antonio R..The latest application filed is for "global bit select circuit with write around capability".

Company Profile

0.18.17

Pelella; Antonio R. - Highland Falls NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Global bit select circuit with write around capability Grant 8,638,595 - Pelella January 28, 2	2014-01-28
Global Bit Select Circuit With Write Around Capability App 20130272057 - Pelella; Antonio R.	2013-10-17
Single clock dynamic compare circuit Grant 8,233,331 - Chan , et al. July 31, 2	2012-07-31
Robust local bit select circuitry to overcome timing mismatch Grant 8,184,475 - Joshi , et al. May 22, 2	2012-05-22
Single Clock Dynamic Compare Circuit App 20110298500 - Chan; Yuen H. ; et al.	2011-12-08
Testing Memory Arrays And Logic With Abist Circuitry App 20110296259 - Balakrishnan; Bargav ; et al.	2011-12-01
Robust Local Bit Select Circuitry To Overcome Timing Mismatch App 20110199817 - Joshi; Rajiv V. ; et al.	2011-08-18
High performance pseudo dynamic pulse controllable multiplexer Grant 7,592,851 - Chan , et al. September 22, 2	2009-09-22
High Performance Pseudo Dynamic Pulse Controllable Multiplexer App 20090189675 - Chan; Yuen H. ; et al.	2009-07-30
Global bit select circuit interface with dual read and write bit line pairs Grant 7,463,537 - Chan , et al. December 9, 2	2008-12-09
Global Bit Select Circuit Interface with Dual Read and Write Bit Line Pairs App 20080056052 - Chan; Yuen H. ; et al.	2008-03-06
Global bit select circuit with dual read and write bit line pairs Grant 7,336,546 - Chan , et al. February 26, 2	2008-02-26
Split L2 latch with glitch free programmable delay Grant 7,293,209 - Chan , et al. November 6, 2	2007-11-06
Global bit line restore timing scheme and circuit Grant 7,272,030 - Chan , et al. September 18, 2	2007-09-18
Global Bit Line Restore Timing Scheme and Circuit App 20070058421 - Chan; Yuen H. ; et al.	2007-03-15
Global bit line restore timing scheme and circuit Grant 7,170,774 - Chan , et al. January 30, 2	2007-01-30
Local bit select with suppression of fast read before write Grant 7,113,433 - Chan , et al. September 26, 2	2006-09-26
Local bit select circuit with slow read recovery scheme Grant 7,102,946 - Pelella September 5, 2	2006-09-05
Split L2 latch with glitch free programmable delay App 20060179375 - Chan; Yuen H. ; et al.	2006-08-10
Global bit select circuit with dual read and write bit line pairs App 20060176753 - Chan; Yuen H. ; et al.	2006-08-10
Local bit select with suppression of fast read before write App 20060176729 - Chan; Yuen H. ; et al.	2006-08-10
Global bit line restore timing scheme and circuit App 20060176730 - Chan; Yuen H. ; et al.	2006-08-10
Local Bit Select Circuit With Slow Read Recovery Scheme App 20060176728 - Pelella; Antonio R.	2006-08-10
Output driver with pulse to static converter Grant 7,084,673 - Chan , et al. August 1, 2	2006-08-01
Cache late select circuit Grant 7,054,184 - Chan , et al. May 30, 2	2006-05-30
Output driver with pulse to static converter App 20050253639 - Chan, Yuen H. ; et al.	2005-11-17
Cache late select circuit App 20050254285 - Chan, Yuen H. ; et al.	2005-11-17
Coupled body contacts for SOI differential circuits Grant 6,868,000 - Chan , et al. March 15, 2	2005-03-15
Coupled body contacts for SOI differential circuits App 20040228160 - Chan, Yuen H. ; et al.	2004-11-18
High performance dual-stage sense amplifier circuit Grant 6,788,112 - Chan , et al. September 7, 2	2004-09-07
Self Timed Pre-charged Address Compare Logic Circuit App 20030210134 - Pelella, Antonio R.	2003-11-13
Self timed pre-charged address compare logic circuit Grant 6,646,544 - Pelella November 11, 2	2003-11-11
Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch Grant 5,576,644 - Pelella November 19, 1	1996-11-19

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