U.S. patent application number 10/341906 was filed with the patent office on 2003-10-23 for power conditioning substrate stiffener.
Invention is credited to Pommer, Richard.
Application Number | 20030197256 10/341906 |
Document ID | / |
Family ID | 24041370 |
Filed Date | 2003-10-23 |
United States Patent
Application |
20030197256 |
Kind Code |
A1 |
Pommer, Richard |
October 23, 2003 |
Power conditioning substrate stiffener
Abstract
Utilization of the "dead space" previously occupied by a metal
stiffener in an integrated circuit package as a location for power
conditioning and converting mechanisms such as decoupling
capacitors and planar transformers.
Inventors: |
Pommer, Richard; (Carlsbad,
CA) |
Correspondence
Address: |
Sandra P. Thompson
RIORDAN & MCKINZIE
18th Floor
600 Anton Blvd.
Costa Mesa
CA
92626
US
|
Family ID: |
24041370 |
Appl. No.: |
10/341906 |
Filed: |
January 13, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10341906 |
Jan 13, 2003 |
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09512969 |
Feb 24, 2000 |
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6570250 |
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Current U.S.
Class: |
257/678 ;
257/E25.012; 257/E25.016 |
Current CPC
Class: |
H01L 2224/05568
20130101; H01L 2224/05599 20130101; H01L 2924/00014 20130101; H01L
2224/16225 20130101; H01L 2924/15311 20130101; H01L 2224/48091
20130101; H01L 25/072 20130101; H01L 2924/00014 20130101; H01L
2924/1532 20130101; H01L 2924/15153 20130101; H01L 25/0655
20130101; H01L 2224/05573 20130101; H01L 2924/19041 20130101; H01L
2224/32225 20130101; H01L 2224/48091 20130101; H01L 2224/48227
20130101; H01L 2924/1517 20130101; H01L 2924/00014 20130101; H01L
2924/30107 20130101 |
Class at
Publication: |
257/678 |
International
Class: |
H01L 023/02 |
Claims
What is claimed is:
1. A combination comprising: an integrated circuit (IC) comprising
a power input pad; a power conditioning frame (PCF); an
interconnect having an IC mounting surface comprising an IC power
output pad, a first conditioning pad and a second conditioning pad,
the first conditioning pad electrically coupled to the IC power
output pad, the second conditioning pad electrically coupled to an
interconnect power input pad, the first and second conditioning
pads being electrically connected through the power conditioning
frame.
2. The combination of claim 1 wherein the PCF comprises an
electrical component which is part of a power path from the first
conditioning pad to the second conditioning pad through the PCF,
the power path electrically connecting the first and second
conditioning pads.
3. The combination of claim 2 wherein the component is an active
device.
4. The combination of claim 2 wherein the component is one of a
capacitor, a resistor, a conductor, or a network of capacitors,
resistors, or conductors.
5. The combination of claim 2 wherein the component is a planar
transformer.
6. The combination of claim 1 wherein the PCF comprises an inner
hollow and the IC is positioned with the hollow.
7. A method for assembling an IC package combination comprising:
providing a known good IC; providing a known good interconnect;
providing a known good PCF; coupling the IC to the interconnect;
coupling the PCF to the interconnect.
8. A method of assembling a combination: providing an integrated
circuit (IC) comprising a power input pad; providing a power
conditioning frame (PCF); providing an interconnect having an IC
mounting surface comprising a first conditioning pad electrically
coupled to an IC power output pad, an interconnect power input pad
electrically coupled to a second conditioning pad, the first
conditioning pad and second conditioning pad being electrically
unconnected; electrically coupling the PCF to the first
conditioning pad and the second conditioning pad so as to
electrically connect the first conditioning pad to the second
conditioning pad through the power conditioning frame; electrically
coupling the IC power input pad to the interconnect power output
pad.
Description
FIELD OF THE INVENTION
[0001] The field of the invention is integrated circuit
packaging.
BACKGROUND OF THE INVENTION
[0002] As the amount of power required by ICs increases, there is
increasing difficulty in passing sufficient power through
interconnects to the ICs. To make the issue worse, as the IC power
has risen, the voltages have dropped from 5V to 3.3V, then to 1.2V,
and now approach 1V. This increase in power and decrease in voltage
has caused the current required to increase rapidly. At the same
time the number of I/O's and the switching rates are increasing
while the I/O pitch on the chip is decreasing. All of this causes
high dI/dt power noise which make clean power distribution
difficult. Although the use of decoupling capacitors can help
reduce such noise, building capacitors into a substrate filled with
high density vias tends to be difficult and costly.
SUMMARY OF THE INVENTION
[0003] The present invention is directed to utilizing the "dead
space" previously occupied by a metal stiffener in an integrated
circuit package as a location for power conditioning and converting
mechanisms such as de-coupling capacitors and planar
transformers.
[0004] Various objects, features, aspects and advantages of the
present invention will become more apparent from the following
detailed description of preferred embodiments of the invention,
along with the accompanying drawings in which like numerals
represent like components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is a top perspective view of a first combination
embodying the invention.
[0006] FIG. 2 is an exploded cross-sectional view of the
combination of FIG. 1.
[0007] FIG. 3 is a detailed view of second combination embodying
the invention.
[0008] FIG. 4 is side cutaway view of a first FLIP-CHIP MLBGA
combination embodying the invention.
[0009] FIG. 5 is side cutaway view of a WIRE BONDED TBGA
combination embodying the invention.
[0010] FIG. 6 is side cutaway view of a second FLIP-CHIP MLBGA
combination embodying the invention.
[0011] FIG. 7 is an exploded perspective view of a sixth
combination embodying the invention.
[0012] FIG. 8 is a top view of the printed circuit card and IC of
FIG. 7.
[0013] FIG. 9 is a top view of the PCF of FIG. 7.
[0014] FIG. 10 is an exploded perspective view of a seventh
combination embodying the invention.
[0015] FIG. 11 is a top view of the printed circuit board and IC of
FIG. 10.
[0016] FIG. 12 is a top view of the PCF of FIG. 10.
DETAILED DESCRIPTION
[0017] An IC package typically comprises an interconnect to which
an IC is connected, and a copper stiffening frame which either
surrounds the IC or covers one side of the package. In place of the
typical solid frame, a power conditioning frame (PCF) comprising
power conditioning and possibly converting mechanisms can be used.
Power provided to the interconnect would pass through the PCF, back
into the interconnect, and then into the IC.
[0018] The standard frames take up a relatively large amount of
space so power conditioning frames sized similarly can contain
sizable decoupling capacitors. Moreover, by moving de-coupling
capacitors and similar devices off of the interconnect, the
interconnect can be more fully tested without damaging such
devices. After separate testing, the power conditioning frame and
the interconnect can be coupled together. It is also contemplated
to bring power into the interconnect at a higher voltage and use a
PCF to step it down to power the I/O and logic portions of the IC.
The ability to step down the voltage in the PCF greatly simplifies
power distribution as it reduces the number of vias needed to
transfer power through the interconnect. Moreover, moving any power
conditioning off of the interconnect and into the PCF will likely
shorten signal paths with a resulting decrease in inductance.
[0019] The use of a PCF to take advantage of dead space can also be
accomplished where an IC is mounted directly to a printed circuit
board (PCB) or card (PCC). In such embodiments, the interconnect
comprises the PCB or PCC with the PCF having the same relationship
to the IC and PCB/PCC as it does to an IC and interconnect
combination. For the sake of simplicity, the term interconnect as
used herein also includes PCBs and PCCs.
[0020] Referring first to FIGS. 1 and 2, an IC package combination
comprises an interconnect 10, an IC/die 20, and a PCF 30. When
viewed from the top, as shown in FIGS. 8 and 11, the outer
perimeters of interconnect 10 and IC 20 form substantially
rectangular footprints with the footprint of IC 20 being smaller
than and falling within the footprint of interconnect 10. PCF 30 is
sized and dimensioned to fit within the dead space which falls
outside the footprint of IC 20, but inside the footprint of
interconnect 10. When viewed from the side it can be seen that both
IC 20 and PCF 30 are preferably coupled to the same surface of
interconnect 10.
[0021] Referring to FIG. 5, the IC package combination may be in a
wire bonded TBGA form or, referring to FIGS. 4 and 6, in a
flip-chip MLBGA form, or any other form which has sufficient dead
space within which the PCF can be included. As shown in FIGS. 4-6 a
power/ground decoupling layer 40 may also be part of the
interconnect (FIGS. 5 and 6) or as part of the PCF (FIG. 4).
Referring to FIGS. 7 and 10, the combination may also include a
thermal transfer layer/copper plate 51 and/or a heat sink 52.
[0022] Interconnect 10 can comprise any combination of materials
but will typically comprise a first conductive pattern 11 and a
second conductive pattern 12. The patterns 11 and 12 are typically
electrically connected so as to allow the pattern 21 of IC 20 to be
electrically connected to a printed wiring board (PWB) through
interconnect 10. Referring to FIG. 3, interconnect 10 may comprise
a powerinput pad 13,avia 14, pads 15a and 15b,vias 16 and 18,
component 17,andpad 19. Pad 13, via 14, and pad ISA provide a path
for power to pass through interconnect 10 to pad 32 of PCF 30. The
power path then continues through PCF 30, back into interconnect 10
via pad 15B and through interconnect 10 by way of pad 15B, via 16,
component 17, via 18, and pad 19 into power input pad 22 of IC 20.
It can thus be seen that, in at least some embodiments,
interconnect 10 will comprise a broken conductive path between a
power input pad of the interconnect and a power input pad of the IC
which is closed/bridged by PCF 30. Although other embodiments of
interconnect 10 may comprise structures which vary widely from that
shown in FIG. 3, it is contemplated that all preferred embodiments
will comprise at least one power path which must be closed/bridged
by PCF 30 before power provided to interconnect 10 can flow into IC
20. As previously discussed, interconnect 10 may, among others, be
a PCB (FIG. 10) or PCC (FIG. 7) and/or may be used as the PCB of a
multi-chip module (MCM).
[0023] As used herein, a power pad is a pad used to transfer power
into or out of the IC, interconnect, or PCF. A conditioning pad is
simply a pad which is part of the interconnect but is used to
electrically connect the PCF to the intercoimect. An interconnect
power input pas is simply a pad used to transfer power into the
interconnect so that it subsequently can be transferred through the
PCF and then into the IC. A PCF is essentially a power or signal
conditioning circuit sized and dimensioned to fit within the open
space which results from the differences in sizes between the IC
and the interconnect, and which can be assembled and tested
separately from both the interconnect and the IC.
[0024] IC 20 can comprise any combination of materials but
typically will comprise a conductive pattern 21 sized and
dimensioned so as to make the use of interconnect 10
advantageous.
[0025] PCF 30 is preferred to comprise a conductive pattern 31 and
at least one bridging component 34. Conductive pattern 31 is
preferred to comprise at least one power input pad 32 and at least
one power output pad 36 with vias 33 and 35 and component 34
providing a conductive path between pad 32 and pad 36.
[0026] Component 34 may be any type of component and thus might be,
among others, a simply conductor, a resistor, a capacitor, an
inductor, or a planar transformers. Instead of a single device,
component 34 may comprise a network of homogeneous or diverse
devices.
[0027] PCF 30 is preferred to be sized and dimensioned to fit
within the dead space which results from the difference in sizes
between an IC and its interconnect (see FIGS. 7-12). Although some
embodiments may be frame shaped and comprise an inner hollow in
which the IC fits so as to take advantage of all of the available
dead space, other embodiments may utilize only a portion of the
space and thus comprise a "within" frame or to simply have a
rectangular or other non-frame shape. In less preferred embodiments
the PCF may be taller than the IC and/or may extend beyond the
footprint of the interconnect.
[0028] It is contemplated that PCF 30 might also incorporate a
thermal electric cooler or fan, may have other uses than power
conditioning, and/or may be a passive, semi-active, or active
device.
[0029] In some embodiments it may be advantageous to utilize ICs
having power provided on the outside pads nearest there perimeters
and logic inputs on the inside pads. Thus reversing the typical
arrangement which utilizes inside pads as power inputs and outside
pads as logic/signal inputs.
[0030] A combination utilizing a PCF as described may be assembled
by, providing a known good IC; providing a known good interconnect;
providing a known good PCF; coupling the IC to the interconnect;
and coupling the PCF to the interconnect.
[0031] PCF 30 may condition one or more signals of provided by
interconnect 10 in any number of ways including, but not
necessarily limited to stepping voltages up or down, and filtering
to provide spike protection and/or eliminate noise.
[0032] Thus, specific embodiments and applications of combinations
utilizing power conditioning frames have been disclosed. It should
be apparent, however, to those skilled in the art that many more
modifications besides those already described are possible without
departing from the inventive concepts herein. As an example, some
embodiments may couple the PCF directly to the IC so that power or
other signals provided to the interconnect pass through the PCF and
then to the IC without reentering the interconnect. As an
alternative example, the devices and methods disclosed herein might
be applied to MCMs and PCBs as well as IC packages. Yet another
alternative may condition non-power signals such that the PCF acts
as a signal conditioning frame rather than a power conditioning
frame. The inventive subject matter, therefore, is not to be
restricted except in the spirit of the appended claims. Moreover,
in interpreting both the specification and the claims, all terms
should be interpreted in the broadest possible manner consistent
with the context. In particular, the terms "comprises" and
"comprising" should be interpreted as referring to elements,
components, or steps in a non-exclusive manner, indicating that the
referenced elements, components, or steps may be present, or
utilized, or combined with other elements, components, or steps
that are not expressly referenced.
* * * * *