U.S. patent application number 10/093177 was filed with the patent office on 2003-09-11 for in-situ monitor seed for copper plating.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Chou, Shih-Wei, Tsai, Minghsing.
Application Number | 20030168345 10/093177 |
Document ID | / |
Family ID | 27787932 |
Filed Date | 2003-09-11 |
United States Patent
Application |
20030168345 |
Kind Code |
A1 |
Tsai, Minghsing ; et
al. |
September 11, 2003 |
In-situ monitor seed for copper plating
Abstract
A method and apparatus for monitoring copper seed layer growth
during copper plating of a semiconductor wafer. A ring contact for
use in copper plating of the semiconductor wafer is generally
divided into a plurality of switches thereof. The ring contact is
biased to prior to copper plating of the semiconductor wafer to
determine a copper seed layer conductivity. Each switch among the
plurality of switches can be connected together and thereafter the
switches may be biased to an anode during copper plating, thereby
permitting in-situ monitoring of copper seed resistance prior to
the copper plating and a detection of copper seed damage and copper
seed corrosion associated with the copper plating.
Inventors: |
Tsai, Minghsing; (Hsin-Chu,
TW) ; Chou, Shih-Wei; (Taipei, TW) |
Correspondence
Address: |
TUNG & ASSOCIATES
Suite 120
838 W. Long Lake Road
Bloomfield Hills
MI
48302
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
|
Family ID: |
27787932 |
Appl. No.: |
10/093177 |
Filed: |
March 7, 2002 |
Current U.S.
Class: |
205/157 ;
257/E21.175 |
Current CPC
Class: |
H01L 21/2885 20130101;
C25D 21/12 20130101; C25D 7/123 20130101; H01L 21/76873 20130101;
C25D 17/001 20130101; H01L 21/76843 20130101 |
Class at
Publication: |
205/157 |
International
Class: |
C25D 007/12 |
Claims
1. A method for monitoring seed layer growth during plating of a
semiconductor wafer, said method comprising the steps of: dividing
a ring contact for use in plating of said semiconductor wafer,
wherein said ring contact is divided to include a plurality of
switches thereof; and biasing said ring contact prior to plating of
said semiconductor wafer to determine a seed layer conductivity,
thereby permitting in-situ monitoring of seed resistance prior to
plating of said semiconductor wafer.
2. The method of claim 1 further comprising the step of: connecting
each switch among said plurality of switches together.
3. The method of claim 1 further comprising the step of: biasing
said plurality of switches to an anode during plating.
4. The method of claim 1 further comprising the steps of:
connecting each switch among said plurality of switches together;
and biasing said plurality of switches to an anode during
plating.
5. The method of claim 1 further comprising the step of: detecting
seed damage associated with said plating of said semiconductor
wafer.
6. The method of claim 1 further comprising the step of: detecting
seed corrosion associated with said plating of said semiconductor
wafer.
7. The method of claim 1 further comprising the step of: plating
said semiconductor wafer.
8. The method of claim 7 wherein the step of plating said
semiconductor wafer further comprises the step of: plating said
semiconductor wafer with copper.
9. The method of claim 8 wherein said seed layer comprises a copper
seed layer.
10. A method for monitoring copper seed layer growth during copper
plating of a semiconductor wafer, said method comprising the steps
of: dividing a ring contact for use in copper plating of said
semiconductor wafer, wherein said ring contact is divided to
include a plurality of switches thereof; and biasing said ring
contact prior to copper plating of said semiconductor wafer to
determine a copper seed layer conductivity; connecting each switch
among said plurality of switches together; and thereafter biasing
said plurality of switches to an anode during copper plating,
thereby permitting in-situ monitoring of copper seed resistance
prior to said copper plating and a detection of copper seed damage
and copper seed corrosion associated with said copper plating.
11. An apparatus for monitoring seed layer growth during plating of
a semiconductor wafer, said apparatus comprising: a ring contact
for use in plating of said semiconductor wafer, wherein said ring
contact is divided to include a plurality of switches thereof; and
biasing mechanism for biasing said ring contact prior to plating of
said semiconductor wafer to determine a seed layer conductivity,
thereby permitting in-situ monitoring of seed resistance prior to
plating of said semiconductor wafer.
12. The apparatus of claim 11 wherein each switch among said
plurality of switches are connected together.
13. The apparatus of claim 11 wherein said biasing mechanism
further comprises: biasing mechanism for biasing said plurality of
switches to an anode during plating.
14. The apparatus of claim 11 further comprising: connecting each
switch among said plurality of switches together; and wherein said
biasing mechanism biases said plurality of switches to an anode
during plating.
15. The apparatus of claim 11 further comprising: detecting
mechanism for detecting seed damage associated with said plating of
said semiconductor wafer.
16. The apparatus of claim 11 further comprising: detecting
mechanism for detecting seed corrosion associated with said plating
of said semiconductor wafer.
17. The apparatus of claim 11 further comprising: plating mechanism
for plating said semiconductor wafer.
18. The apparatus of claim 17 wherein said plating mechanism
further comprises: plating mechanism for plating copper.
19. The apparatus of claim 18 wherein said seed layer comprises a
copper seed layer.
20. An apparatus for monitoring copper seed layer growth during
copper plating of a semiconductor wafer, said apparatus comprising:
a ring contact for use in copper plating of said semiconductor
wafer, wherein said ring contact is divided to include a plurality
of switches thereof; biasing mechanism for biasing said ring
contact prior to copper plating of said semiconductor wafer to
determine a copper seed layer conductivity; wherein each switch
among said plurality of switches are connecting together; and
wherein said plurality of switches are biased to an anode during
copper plating, thereby permitting in-situ monitoring of copper
seed resistance prior to said copper plating and a detection of
copper seed damage and copper seed corrosion associated with said
copper plating.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to semiconductor
fabrication techniques and devices. The present invention also
relates to copper plating devices and techniques utilized in the
fabrication of integrated circuits on semiconductor wafers. The
present invention also relates to contact rings utilized in copper
plating processes and devices.
BACKGROUND OF THE INVENTION
[0002] The production of semiconductor integrated circuits and
other microelectronic devices from workpieces such as semiconductor
wafers typically requires formation of one or more metal layers on
the wafer. These metal layers are used, for example, to
electrically interconnect the various devices of the integrated
circuit. Further, the structures formed from the metal layers may
constitute microelectronic devices such as read/write heads,
etc.
[0003] The microelectronic manufacturing industry has applied a
wide range of metals to form such structures. These metals include,
for example, nickel, tungsten, solder, platinum, and copper.
Further, a wide range of processing techniques have been used to
deposit such metals. These techniques include, for example,
chemical vapor deposition (CVD), physical vapor deposition (PVD),
electroplating, and electroless plating. Of these techniques,
electroplating and electroless plating tend to be the most
economical and, as such, the most desirable. Electroplating and
electroless plating can be used in the deposition of blanket metal
layers as well as patterned metal layers.
[0004] One of the most popular process sequences used by the
microelectronic manufacturing industry to deposit a metal onto
semiconductor wafers is referred to as "damascene" processing. In
such processing holes, commonly called "vias", trenches and/or
other recesses are formed onto a workpiece and filled with a metal,
such as copper. In the damascene process, the wafer is first
provided with a metallic seed layer which is used to conduct
electrical current during a subsequent metal electroplating
step.
[0005] If a metal such as copper is utilized, the seed layer can be
disposed over a barrier layer material, such as Ti, TiN, etc. The
seed layer is generally a very thin layer of metal which can be
applied using one or more of several processes. For example, the
seed layer of metal can be laid down using physical vapor
deposition or chemical vapor deposition processes to produce a
layer on the order of 1,000 angstroms thick. The seed layer can
advantageously be formed of copper, gold, nickel, palladium, or
other metals. The seed layer is formed over a surface which is
convoluted by the presence of the vias, trenches, or other recessed
device features.
[0006] A metal layer is then electroplated onto the seed layer in
the form of a blanket layer. The blanket layer is plated to form an
overlying layer, with the goal of providing a metal layer that
fills the trenches and vias and extends a certain amount above
these features. Such a blanket layer will typically have a
thickness on the order of 10,000 to 15,000 angstroms (1-1.5
microns).
[0007] After the blanket layer has been electroplated onto the
semiconductor wafer, excess metal material present outside of the
vias, trenches, or other recesses is removed. The metal is removed
to provide a resulting pattern of metal layer in the semiconductor
integrated circuit being formed. The excess plated material can be
removed, for example, using chemical mechanical planarization.
Chemical mechanical planarization is a processing step which uses
the combined action of a chemical removal agent and an abrasive
which grinds and polishes the exposed metal surface to remove
undesired parts of the metal layer applied in the electroplating
step.
[0008] The electroplating of the semiconductor wafers takes place
in a reactor assembly. In such an assembly an anode electrode is
disposed in a plating bath, and the wafer with the seed layer
thereon is used as a cathode. Only a lower face of the wafer
contacts the surface of the plating bath. The wafer is held by a
support system that also conducts the requisite electroplating
power (e.g., cathode current) to the wafer. The support system may
comprise conductive fingers that secure the wafer in place and also
contact the wafer seed layer in order to conduct electrical current
for the plating operation.
[0009] Thus, the modern semiconductor industry has begun relying on
a manufacturing process called "damascene" for forming interconnect
lines and vias for multi-layer metal structures that provide the
"wiring" of an integrated circuit. As explained above, the
damascene technique involves etching a trench in a planar
dielectric (insulator) layer and filling the trench with a metal
such as aluminum, copper, or tungsten. A technique called
"dual-damascene" adds etched vias for providing contact to the
lower level as the damascene structure is filled.
[0010] There are several different ways to manufacture the
damascene structure in the dielectric layer as practiced in the art
For example, when copper is used as the filling, a layer of another
material can be initially deposited to line the trenches and vias
to prevent the migration of the copper into the dielectric layer.
This migration barrier can be deposited by chemical vapor
deposition (CVD), physical vapor deposition (PVD), or electroless
deposition. In addition to the migration barrier, sometimes a seed
layer of the plating metal and/or other metals are applied to serve
as a good site for electroless or electrolytic plating.
[0011] The filling process can be accomplished by plasma
deposition, sputtering, or electroless or electrolytic deposition
onto a seed layer. To achieve good fill of the typical micron to
sub-micron wide trenches and vias, extra metal is deposited in the
process, such metal covering areas of the wafer above and outside
the trenches and vias. After filling, the extra metal must be
removed down to the dielectric surface while leaving the trenches
and vias filled in a process called "planarization". Standard
chemical mechanical planarization (CMP) can be used to provide a
planarized surface and metal removal.
[0012] As an alternative to CMP, electrochemical etching (ECE),
electrochemical polishing (ECP), electropolishing or
electrochemical planarization (ECP) has been used. For the purpose
of this application, the terms "electrochemical polishing",
"electropolishing", "planarizing" and "electrochemical
planarization" will be used interchangeably as they are in
literature, the end goal is to have a very flat and smooth surface,
the small differences between the terms is that the polishing
desires to have a very smooth surface, while planarization desires
to flatten-out topology and produce a flat smooth surface.
"Electrochemical etch" however has a different purpose, that is to
remove material, generally uniformly, without regard to surface
flatness.
[0013] In conventional copper plating devices, a barrier/seed is
required for current conduction and copper growth. For the
production of semiconductor wafers, however, patterns are located
on the top of the wafer and cannot be monitored in-situ
effectively. In addition, some wafers may be mis-processed and seed
layer processes skipped prior to ECP. Wafers that do not have a
copper seed layer or a poorly plated seed layer, which then are
sent to ECP operations can cause a great amount of copper to
accumulate on the associated ring contact utilized in copper
plating and semiconductor fabrication operations thereof. This
results in particle accumulation issues and wafer peeling concerns.
Conventional approaches to minimize this problem typically involves
setting a high voltage value. Such an approach, however, will only
reduce the particle risk while completely eliminating the risk
altogether. Based on the foregoing, the present inventors have
concluded that a need exists for an improved apparatus and method
for in-situ monitoring of metal seed layer formation.
BRIEF SUMMARY OF THE INVENTION
[0014] The following summary of the invention is provided to
facilitate an understanding of some of the innovative features
unique to the present invention, and is not intended to be a full
description. A full appreciation of the various aspects of the
invention can be gained by taking the entire specification, claims,
drawings, and abstract as a whole.
[0015] It is therefore one aspect of the present invention to
provide an improved semiconductor fabrication apparatus and
method.
[0016] It is another aspect of the present invention to provide
improved copper plating devices and techniques utilized in the
fabrication of integrated circuits on semiconductor wafers.
[0017] It is yet another aspect of the present invention to provide
an improved contact ring for utilization in copper plating
processes and devices thereof.
[0018] It is still another aspect of the present invention to
provide a method and apparatus for monitoring copper seed layer
growth during copper plating of a semiconductor wafer.
[0019] The above and other aspects of the present invention can
thus be achieved as is now described. A method and apparatus for
monitoring copper seed layer growth during copper plating of a
semiconductor wafer is disclosed herein. A ring contact for use in
copper plating of the semiconductor wafer is generally divided into
a plurality of switches thereof. The ring contact is biased to
prior to copper plating of the semiconductor wafer to determine a
copper seed layer conductivity. Each switch among the plurality of
switches can be connected together and thereafter the switches may
be biased to an anode during copper plating, thereby permitting
in-situ monitoring of copper seed resistance prior to the copper
plating and a detection of copper seed damage and copper seed
corrosion associated with the copper plating. The ring contact can
preferably be divided into 2 to 32 switches. The ring contact can
be biased to check the seed layer conductivity before plating. All
ring contacts can be connected together and biased to an anode
during plating. In-situ monitoring of the seed resistance before
plating thus can take place according to the method and apparatus
disclosed herein. Seed damage or seed corrosion can thus be
detected, thereby preventing particle and copper peeling on damaged
seed or non-seed layers thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying figures, in which like reference numerals
refer to identical or functionally-similar elements throughout the
separate views and which are incorporated in and form part of the
specification, further illustrate the present invention and,
together with the detailed description of the invention, serve to
explain the principles of the present invention.
[0021] FIG. 1 illustrates a side view of a copper plating
apparatus, in accordance with a preferred embodiment of the present
invention.
[0022] FIG. 2 depicts a top side view of a copper plating
apparatus, in accordance with a preferred embodiment of the present
invention;
[0023] FIG. 3 illustrates a schematic diagram of a copper plating
apparatus, in accordance with a preferred embodiment of the present
invention;
[0024] FIG. 4 depicts a top view of the copper plating apparatus
indicated in FIG. 1, in accordance with a preferred embodiment of
the present invention;
[0025] FIG. 5 illustrates a top view of the copper plating
apparatus indicated in FIG. 2, in accordance with a preferred
embodiment of the present invention;
[0026] FIG. 6 depicts a schematic diagram of a contact ring that
can be utilized in accordance with a preferred embodiment of the
present invention; and
[0027] FIG. 7 illustrates a block diagram of a semiconductor wafer
and a copper plating apparatus, in accordance with a preferred
embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0028] The particular values and configurations discussed in these
non-limiting examples can be varied and are cited merely to
illustrate embodiments of the present invention and are not
intended to limit the scope of the invention.
[0029] Because a barrier/seed is required for current conduction
and copper growth in traditional copper plating devices and related
methods thereof, particle accumulation, along with copper peeling
and copper seed corrosion must be resolved. In the production of
semiconductor wafers, patterns are generally located on the top of
the wafer and cannot be monitored in-situ effectively.
[0030] Some semiconductor wafers may be mis-processed and seed
layer processes skipped prior to ECP. Wafers that do not have a
copper seed layer or a poorly plated seed layer, which then are
sent to ECP operations can cause a great amount of copper to
accumulate on the associated ring contact utilized in copper
plating and semiconductor fabrication operations thereof. This
results in particle accumulation issues and wafer peeling
concerns.
[0031] Conventional approaches to minimize this problem typically
involves setting a high voltage value. Such an approach, however,
reduces the particle risk while not entirely completing
elimination. The present invention disclosed and described herein
thus solves these problems and associated issues.
[0032] FIG. 1 illustrates a side view 10 of a copper plating
apparatus 21, in accordance with a preferred embodiment of the
present invention. Copper plating apparatus 21 generally includes a
copper anode 16 having a positive node 17. The electrolyte flow is
indicated by arrow 18. Note that in FIGS. 1 to 5 illustrated
herein, like parts are generally indicated by identical reference
numerals.
[0033] FIG. 2 depicts a top side view 12 of a copper plating
apparatus 23, in accordance with a preferred embodiment of the
present invention. Copper plating apparatus 23 of FIG. 2 is
analogous to copper plating apparatus of 21 of FIG. 1. Copper
plating apparatus 23 includes a ring 22 (i.e., a contact ring).
FIG. 3 illustrates a schematic diagram 15 of a copper plating
apparatus, in accordance with a preferred embodiment of the present
invention. Note the inclusion of ground 19 and positive node
17.
[0034] Because contact rings are well-known in the semiconductor
arts, it is not necessary to describe such contact rings in detail.
It is important, however, to keep in mind that the present
invention generally comprises an improvement to prior art contact
rings and the manner in which such contact rings are utilized, in
order to effect a novel method and apparatus for in-situ monitoring
of seed layer development and ensuring proper contact and no wafer
warpage. In general, a contact ring can be utilized to provide a
substantially continuous electrically-conductive contact with a
peripheral region of an associated semiconductor wafer or other
workpiece. The improved contact ring disclosed herein, however,
permits the periphery of a semiconductor wafer to be checked and/or
monitored for copper seed layer formation only, not the center of
the semiconductor wafer.
[0035] FIG. 4 depicts a top view 23 of the copper plating apparatus
21 indicated in FIG. 1, in accordance with a preferred embodiment
of the present invention. Copper plating apparatus 21 can be
configured as a ring contact which is divided into a plurality of 2
to 32 switches 24. The number of switches chosen depends on a
desired implementation of the present invention. Thus, the number
of switches may vary. An initial switch T.sub.i is represented in
FIG. 4 by arrow 26. A second switch is indicated by arrow 28.
[0036] FIG. 5 illustrates a top view 25 of the copper plating
apparatus 22 indicated in FIG. 2, in accordance with a preferred
embodiment of the present invention. Block 32 illustrated in FIG. 5
represents a computer controller. Also illustrated in FIG. 5 are a
positive node 17 and a negative node 19. A central portion 30 of
copper plating apparatus 22 may be linked to computer controller
32. Again, in FIGS. 4 and 5, like parts are illustrated by
identical reference numerals.
[0037] FIG. 6 depicts a schematic diagram 44 of a contact ring 42
that can be utilized in accordance with a preferred embodiment of
the present invention. Contact ring 42 generally comprises a
contact ring which can be divided into separate contacts, such as,
for example, contact 46 to detect seed quality and contact. In
addition, contact ring 48 is divided in such a manner to detect the
seed resistance by making switches on the contact ring. Thus,
contact ring 42 can be divided into a plurality of switches or
contacts in order to effectively introduce in-situ monitoring of
seed uniforming prior to plating, such as, for example, copper
plating. Contact ring 42 can also be configured from a rigid and
non-corrosive materials, such as for example, Ti.
[0038] Such a configuration is also desired to assure that
semiconductor wafers are properly moved into a plating cell and
that no copper slum is deposited on the contact ring 42. FIG. 7
illustrates a block diagram 53 of a semiconductor wafer 50 and a
copper plating apparatus, in accordance with a preferred embodiment
of the present invention. In addition, a quartz portion 58 is
illustrated in FIG. 7. Semiconductor wafer 50 may be utilized in
association with contact ring 42 depicted in FIG. 6. By configuring
a copper plating apparatus in the manner illustrated in FIGS. 6 and
7, proper contact may be assured with a minimized downward force,
which is indicated by arrow 56 in FIG. 7, thereby reducing low k
peeling. All contacts are thus joined with an inside metal
ring.
[0039] Based on the foregoing, it can be appreciated that the
present invention generally discloses a method and apparatus for
monitoring copper seed layer growth during copper plating of a
semiconductor wafer is disclosed herein. A ring contact for use in
copper plating of the semiconductor wafer is generally divided into
a plurality of switches thereof. The ring contact is biased to
prior to copper plating of the semiconductor wafer to determine a
copper seed layer conductivity.
[0040] Each switch among the plurality of switches can be connected
together and thereafter the switches may be biased to an anode
during copper plating, thereby permitting in-situ monitoring of
copper seed resistance prior to the copper plating and a detection
of copper seed damage and copper seed corrosion associated with the
copper plating.
[0041] The ring contact can preferably be divided into 2 to 32
switches. The ring contact can be biased to check the seed layer
conductivity before plating. All ring contacts can be connected
together and biased to an anode during plating. In-situ monitoring
of the seed resistance before plating thus can take place according
to the method and apparatus disclosed herein. Seed damage or seed
corrosion can thus be detected, thereby preventing particle and
copper peeling on damaged seed or non-seed layers thereof.
[0042] The embodiments and examples set forth herein are presented
to best explain the present invention and its practical application
and to thereby enable those skilled in the art to make and utilize
the invention. Those skilled in the art, however, will recognize
that the foregoing description and examples have been presented for
the purpose of illustration and example only. Other variations and
modifications of the present invention will be apparent to those of
skill in the art, and it is the intent of the appended claims that
such variations and modifications be covered. For example, although
the present invention is discussed in terms of "copper plating," it
is anticipated that the present invention applies equally to other
types of metallic plating, not merely copper.
[0043] The description as set forth is thus not intended to be
exhaustive or to limit the scope of the invention. Many
modifications and variations are possible in light of the above
teaching without departing from scope of the following claims. It
is contemplated that the use of the present invention can involve
components having different characteristics. It is intended that
the scope of the present invention be defined by the claims
appended hereto, giving full cognizance to equivalents in all
respects.
* * * * *