U.S. patent application number 10/043430 was filed with the patent office on 2003-07-10 for methods of forming flash field effect transistor gates and non-flash field effect transistor gates.
Invention is credited to Beaman, Kevin L..
Application Number | 20030129801 10/043430 |
Document ID | / |
Family ID | 21927122 |
Filed Date | 2003-07-10 |
United States Patent
Application |
20030129801 |
Kind Code |
A1 |
Beaman, Kevin L. |
July 10, 2003 |
METHODS OF FORMING FLASH FIELD EFFECT TRANSISTOR GATES AND
NON-FLASH FIELD EFFECT TRANSISTOR GATES
Abstract
Methods of forming FLASH field effect transistor gates and a
non-FLASH field effect transistor gates are described. In one
implementation, a substrate comprising first and second
semiconductive material portions is provided. A FLASH transistor
gate is partially formed to include at least a first gate
dielectric material received over the first semiconductive material
portion, a floating gate material overlying the first gate
dielectric material, and a second gate dielectric material received
over the floating gate material. The second gate dielectric
material comprises silicon nitride. In a common oxidizing step, the
silicon nitride of the second gate dielectric material and the
second semiconductive material portion are oxidized effective to
form both a) a gate oxide layer of a non-FLASH transistor gate
overlying the second semiconductive material portion, and b)
silicon dioxide as part of the second gate dielectric material of
the FLASH transistor gate. Additional implementations are
contemplated.
Inventors: |
Beaman, Kevin L.; (Boise,
ID) |
Correspondence
Address: |
WELLS ST. JOHN ROBERTS GREGORY & MATKIN P.S.
601 W. FIRST AVENUE
SUITE 1300
SPOKANE
WA
99201-3828
US
|
Family ID: |
21927122 |
Appl. No.: |
10/043430 |
Filed: |
January 9, 2002 |
Current U.S.
Class: |
438/261 ;
257/E21.686; 257/E27.103 |
Current CPC
Class: |
H01L 27/115 20130101;
H01L 27/11539 20130101; H01L 27/11526 20130101 |
Class at
Publication: |
438/261 |
International
Class: |
H01L 021/336 |
Claims
1. A method of forming a FLASH field effect transistor gate and a
non-FLASH field effect transistor gate, comprising: providing a
substrate comprising first and second semiconductive material
portions; partially forming a FLASH transistor gate to include at
least a first gate dielectric material received over the first
semiconductive material portion, a floating gate material overlying
the first gate dielectric material, and a second gate dielectric
material received over the floating gate material; the second gate
dielectric material comprising silicon nitride; and in a common
oxidizing step, oxidizing the silicon nitride of the second gate
dielectric material and the second semiconductive material portion
effective to form both a) a gate oxide layer of a non-FLASH
transistor gate overlying the second semiconductive material
portion, and b) silicon dioxide as part of the second gate
dielectric material of the FLASH transistor gate.
2. The method of claim 1, wherein after the common oxidizing step,
forming a first gate material over the second gate dielectric
material and forming a second gate material over the gate oxide
layer of the non-FLASH transistor gate.
3. The method of claim 1, wherein the common oxidizing step
comprises a temperature of about 850 degrees C. to about 1100
degrees C.
4. The method of claim 1, wherein the common oxidizing step
comprises rapid thermal processing.
5. The method of claim 1, wherein the common oxidizing step
comprises: providing the substrate with the partially formed FLASH
transistor gate within a processing chamber; and injecting hydrogen
and oxygen gas into the processing chamber to generate atomic
oxygen and steam proximate the substrate.
6. The method of claim 1, wherein the second semiconductive
material portion is oxidized at a first rate, and wherein the
silicon nitride of the second gate dielectric material is oxidized
at a second rate which is about 10% to about 70% of the first
rate.
7. The method of claim 1, wherein the common oxidizing step
comprises: providing the substrate with the partially formed FLASH
transistor gate within a processing chamber; after providing the
substrate within the processing chamber, heating the substrate to a
temperature of about 850 degrees C. to about 1100 degrees C.; and
after heating the substrate to a temperature of about 850 degrees
C. to about 1100 degrees C., injecting hydrogen and oxygen gas into
the processing chamber to generate atomic oxygen and steam
proximate the substrate.
8. The method of claim 7, wherein the hydrogen and oxygen gas
injected into the processing chamber form a mixture of gases, and
wherein the mixture of gases comprise about 0.5% to about 33%
hydrogen gas by volume.
9. The method of claim 8, wherein the hydrogen gas has a partial
pressure within the processing chamber, and wherein the partial
pressure of the hydrogen gas can be varied to control a rate at
which the silicon nitride is oxidized, and wherein increasing the
partial pressure of the hydrogen gas increases the rate at which
the silicon nitride is oxidized.
10. A method of forming a FLASH field effect transistor gate and a
non-FLASH field effect transistor gate, comprising: providing a
substrate comprising first and second semiconductive material
portions; partially forming a FLASH transistor gate to include at
least a first gate dielectric material received over the first
semiconductive material portion, a floating gate material overlying
the first gate dielectric material, and a second gate dielectric
material received over the floating gate material; the second gate
dielectric material comprising silicon nitride; and in a common
oxidizing step, exposing the silicon nitride of the second gate
dielectric material and the second semiconductive material portion
to atomic oxygen under conditions effective to form both a) a gate
oxide layer of a non-FLASH transistor gate overlying the second
semiconductive material portion, and b) silicon dioxide as part of
the second gate dielectric material of the FLASH transistor
gate.
11. The method of claim 10, wherein after the common oxidizing
step, forming a first gate material over the second gate dielectric
material and forming a second gate material over the gate oxide
layer of the non-FLASH transistor gate.
12. The method of claim 10, wherein the atomic oxygen is supplied
by an ozone source.
13. The method of claim 10, wherein the atomic oxygen is supplied
by a microwave source.
14. The method of claim 10, wherein the atomic oxygen is supplied
by photo-excitation.
15. The method of claim 10, wherein the atomic oxygen is supplied
by in situ steam generation.
16. The method of claim 10, wherein the common oxidizing step
comprises: providing the substrate with the partially formed FLASH
transistor gate within a processing chamber; after providing the
substrate within the processing chamber, heating the substrate to a
temperature of about 850 degrees C. to about 1100 degrees C.; and
after heating the substrate to a temperature of about 850 degrees
C. to about 1100 degrees C., injecting hydrogen and oxygen gas into
the processing chamber to generate the atomic oxygen proximate the
substrate.
17. The method of claim 10, wherein the gate oxide layer of the
non-FLASH transistor gate overlying the second semiconductive
material portion is formed to a first thickness, and wherein the
silicon dioxide formed as part of the second gate dielectric
material of the FLASH transistor gate is formed to a second
thickness, and wherein the second thickness is about 10% to about
70% of the first thickness.
18. A method of forming a FLASH field effect transistor gate and a
non-FLASH field effect transistor gate, comprising: providing a
substrate comprising first and second semiconductive material
portions; partially forming a FLASH transistor gate to include at
least a first gate dielectric material received over the first
semiconductive material portion, a floating gate material overlying
the first gate dielectric material, and a second gate dielectric
material received over the floating gate material; the second gate
dielectric material comprising a first silicon dioxide comprising
layer and a silicon nitride comprising layer over the first silicon
dioxide comprising layer; and in a common oxidizing step, exposing
the silicon nitride of the second gate dielectric material and the
second semiconductive material portion to atomic oxygen under
conditions effective to form both a) a gate oxide layer of a
non-FLASH transistor gate overlying the second semiconductive
material portion, and b) a second silicon dioxide comprising layer
over the silicon nitride comprising layer as part of the second
gate dielectric material of the FLASH transistor gate.
19. The method of claim 18, wherein after the common oxidizing
step, forming a first gate material over the second gate dielectric
material and forming a second gate material over the gate oxide
layer of the non-FLASH transistor gate.
20. The method of claim 18, wherein the common oxidizing step
comprises: providing the substrate with the partially formed FLASH
transistor gate within a processing chamber; and injecting hydrogen
and oxygen gas into the processing chamber to generate the atomic
oxygen proximate the substrate.
21. The method of claim 18, wherein the second semiconductive
material portion is oxidized at a first rate, and wherein the
silicon nitride of the second gate dielectric material is oxidized
at a second rate which is about 10% to about 70% of the first
rate.
22. The method of claim 18, wherein the common oxidizing step
comprises: providing the substrate with the partially formed FLASH
transistor gate within a processing chamber; after providing the
substrate within the processing chamber, heating the substrate to a
temperature of about 850 degrees C. to about 1100 degrees C.; and
after heating the substrate to a temperature of about 850 degrees
C. to about 1100 degrees C., injecting hydrogen and oxygen gas into
the processing chamber to generate the atomic oxygen proximate the
substrate.
23. A method of forming a FLASH field effect transistor gate and a
non-FLASH field effect transistor gate, comprising: providing a
substrate comprising first and second semiconductive material
portions; partially forming a FLASH transistor gate to include a
silicon nitride comprising layer received over the first
semiconductive material portion; providing the substrate with the
partially formed FLASH transistor gate within a processing chamber;
and injecting hydrogen and oxygen gas into the processing chamber
under conditions effective to generate atomic oxygen proximate the
substrate and to form both a) a gate oxide layer of a non-FLASH
transistor gate overlying the second semiconductive material
portion, and b) silicon dioxide over the silicon nitride layer as
part of the FLASH transistor gate.
24. The method of claim 23, wherein after forming both a) the gate
oxide layer of the non-FLASH transistor gate overlying the second
semiconductive material portion, and b) the silicon dioxide over
the silicon nitride comprising layer as part of the FLASH
transistor gate, the method further comprises forming a first gate
material over the second gate dielectric material and forming a
second gate material over the gate oxide layer of the non-FLASH
transistor gate.
25. The method of claim 23, wherein the silicon dioxide formed over
the silicon nitride comprising layer of the FLASH transistor gate
and the gate oxide layer of the non-FLASH transistor gate are grown
at a temperature of about 850 degrees C. to about 1100 degrees
C.
26. The method of claim 23, wherein the injecting hydrogen and
oxygen gas into the processing chamber under conditions effective
to generate atomic oxygen proximate the substrate is also effective
to generate steam proximate the substrate.
27. The method of claim 26, wherein the atomic oxygen and the steam
oxidize the second semiconductive material portion at a first rate,
and wherein the atomic oxygen and the steam oxidize the silicon
nitride comprising layer received over the first semiconductive
material portion at a second rate which is about 10% to about 70%
of the first rate.
28. The method of claim 23, wherein the gate oxide layer of the
non-FLASH transistor gate overlying the second semiconductive
material portion is formed to a first thickness, and wherein the
silicon dioxide formed over the silicon nitride comprising layer as
part of the FLASH transistor gate is formed to a second thickness,
and wherein the second thickness is about 10% to about 70% of the
first thickness.
29. The method of claim 23, wherein the substrate within the
processing chamber is heated to a temperature of about 850 degrees
C. to about 1100 degrees C. before injecting the hydrogen and
oxygen gas into the processing chamber.
30. The method of claim 29, wherein the hydrogen and oxygen gas
injected into the processing chamber form a mixture of gases, and
wherein the mixture of gases comprise about 0.5% to about 33%
hydrogen gas by volume.
31. The method of claim 30, wherein the hydrogen gas has a partial
pressure within the processing chamber, and wherein the partial
pressure of the hydrogen gas can be varied to control a rate at
which the silicon nitride comprising layer is oxidized, and wherein
increasing the partial pressure of the hydrogen gas increases the
rate at which the silicon nitride comprising layer is oxidized.
Description
TECHNICAL FIELD
[0001] This invention relates to methods of forming FLASH field
effect transistor gates and non-FLASH field effect transistor
gates.
BACKGROUND OF THE INVENTION
[0002] In semiconductor wafer fabrication, certain integrated
circuit designs form both FLASH field effect transistors and
non-FLASH field effect transistors on the same semiconductor
substrate. One particular aspect of doing so, and problems
associated therewith, is described with reference to FIGS. 1-2.
[0003] FIG. 1 depicts a semiconductor wafer fragment 10 at one
processing step. Wafer fragment 10 is comprised of a bulk
monocrystalline silicon substrate 11 having first and second
semiconductive material portions 12 and 13. In the context of this
document, the term "semiconductive substrate" or "semiconductor
substrate" is defined to mean any construction comprising
semiconductive material, including, but not limited to, bulk
semiconductive materials such as a semiconductive wafer (either
alone or in assemblies comprising other materials thereon), and
semiconductive material layers (either alone or in assemblies
comprising other material). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above. Further, in the context
of this document, the term "layer" refers to both the singular and
plural unless otherwise indicated.
[0004] A FLASH field effect transistor gate is shown as being
partially formed over the first semiconductive material portion 12
of substrate 11. Such includes a first gate dielectric material 21
(i.e. silicon dioxide), a floating gate material 22 (i.e.
conductively doped polysilicon) received over first gate dielectric
material 21, and a partially formed second gate dielectric material
30 received over floating gate material 22. Partially formed second
gate dielectric material 30 includes a first silicon dioxide layer
31 and a silicon nitride layer 32 thereover.
[0005] Referring to FIG. 2, a second silicon dioxide layer 33 is
shown to have been formed over silicon nitride layer 32. Formation
of second silicon dioxide layer 33 typically completes the second
gate dielectric material 30, which now comprises a three layer
structure which includes a first silicon dioxide layer 31, a middle
silicon nitride layer 32, and a outer or second silicon dioxide
layer 33. This second gate dielectric material layer 30 is commonly
referred to as an "oxide-nitride-oxide layer", or an "ONO
layer".
[0006] Although it is possible for the second silicon dioxide layer
33 to be deposited, under typical prior art methods it is generally
formed by oxidation of silicon nitride layer 32. The prior art
processing illustrated in FIG. 2 typically forms second silicon
dioxide layer 33 by a thermal oxidation method which includes a
long, hot, wet oxidation step. The goal of this thermal oxidation
was typically to form a 15-30 .ANG. thick silicon dioxide layer 33
on silicon nitride layer 32. By way of illustration only, example
conditions to form this 15-30 .ANG. thick silicon dioxide layer 33
included exposing semiconductor wafer fragment 10 to a temperature
of about 850.degree. C. to about 1000.degree. C., and ambient
pressure in the presence of steam for about 90 to 240 minutes.
[0007] Unfortunately, this thermal oxidation would also generally
oxidize any exposed silicon and result in the formation of a
2000-3000 .ANG. thick silicon dioxide layer over any such exposed
silicon. For example, a 15-30 .ANG. thick silicon dioxide layer 33
is shown to have formed on silicon nitride layer 32, while a
considerably thicker silicon dioxide layer 34 is shown to have
formed over the exposed silicon of second semiconductive material
portion 13.
[0008] This consumption of silicon and thick oxide deposition is
generally undesirable, especially when one wishes to subsequently
form another integrated circuit component over silicon substrate
11, such as forming a non-FLASH field effect transistor over the
second semiconductive material portion 13. Therefore, under prior
art processing methods, other areas of silicon substrate 11, such
as second semiconductive material portion 13, might be masked to
avoid such consumption of silicon and thick oxide deposition
thereover. After the thermal oxidation has been completed, the mask
would be removed and a dedicated oxidation conducted to form any
desired peripheral gate oxide layers over silicon substrate 11.
[0009] The invention was principally motivated by a desire to
address the above-identified issue. However, the invention is in no
way so limited, and is only limited by the accompanying claims as
literally worded and appropriately interpreted in accordance with
the Doctrine of Equivalents.
SUMMARY OF THE INVENTION
[0010] Methods of forming FLASH field effect transistor gates and a
non-FLASH field effect transistor gates are described. In one
implementation, a substrate comprising first and second
semiconductive material portions is provided. A FLASH transistor
gate is partially formed to include at least a first gate
dielectric material received over the first semiconductive material
portion, a floating gate material overlying the first gate
dielectric material, and a second gate dielectric material received
over the floating gate material. The second gate dielectric
material comprises silicon nitride. In a common oxidizing step, the
silicon nitride of the second gate dielectric material and the
second semiconductive material portion are oxidized effective to
form both a) a gate oxide layer of a non-FLASH transistor gate
overlying the second semiconductive material portion, and b)
silicon dioxide as part of the second gate dielectric material of
the FLASH transistor gate. In one implementation, in a common
oxidizing step, the silicon nitride of the second gate dielectric
material and the second semiconductive material portion are exposed
to atomic oxygen under conditions effective to form both a) a gate
oxide layer of a non-FLASH transistor gate overlying the second
semiconductive material portion, and b) silicon dioxide as part of
the second gate dielectric material of the FLASH transistor gate.
Additional implementations are contemplated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0012] FIG. 1 is a diagrammatic sectional view of a prior art
semiconductor wafer fragment at one prior art processing step.
[0013] FIG. 2 is a view of the FIG. 1 prior art wafer fragment at a
processing step subsequent to that shown by FIG. 1.
[0014] FIG. 3 is a diagrammatic sectional view of a semiconductor
wafer fragment at one processing step in accordance with one aspect
of the invention.
[0015] FIG. 4 is a view of the FIG. 3 wafer fragment within a
processing chamber.
[0016] FIG. 5 is a view of the FIG. 4 wafer fragment at a
processing step subsequent to that shown by FIG. 4.
[0017] FIG. 6 is a view of the FIG. 5 wafer fragment at a
processing step subsequent to that shown by FIG. 5.
[0018] FIG. 7 is a view of the FIG. 6 wafer fragment at a
processing step subsequent to that shown by FIG. 6.
[0019] FIG. 8 is a view of the FIG. 7 wafer fragment at a
processing step subsequent to that shown by FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0021] Preferred embodiments of methods of forming a FLASH field
effect transistor gate and non-FLASH field effect transistor gate
are described with reference to FIGS. 3-8. FIG. 3 depicts a
semiconductor wafer fragment 40, for example comprising a bulk
monocrystalline silicon substrate region 42. Substrate 42 can be
considered as comprising first and second semiconductive material
portions 44 and 46, respectively. In the depicted described
example, a FLASH field effect transistor gate is being formed
relative to portion 44, and a non-FLASH field effect transistor
gate is being formed relative to portion 46. Portion 44 has been
processed to include a first gate dielectric material 48 received
thereover. A floating gate material 50 is formed to overly first
gate dielectric material 48. A second gate dielectric material
overlies floating gate material 50. In the depicted embodiment,
such includes a first silicon dioxide comprising layer 52 and a
silicon nitride comprising layer 54 thereover. Collectively, layers
52 and 54 can be considered as a second gate dielectric material
56, which at least comprises silicon nitride. First silicon dioxide
comprising layer 52 is typically formed to a thickness of about
30-60 .ANG., while silicon nitride comprising layer 54 is formed to
a thickness of about 40-70 .ANG.. Such shows but one exemplary
embodiment of partially forming a FLASH transistor gate which
includes at least a first gate dielectric material which is
received over a first semiconductive material portion, a floating
gate material which overlies the first gate dielectric material,
and a second gate dielectric material which is received over the
floating gate material, with the second gate dielectric material
comprising silicon nitride.
[0022] Referring to FIGS. 4 and 5, substrate 40 of FIG. 3 in one
preferred embodiment has been positioned within a processing
chamber 59. Silicon nitride of second gate dielectric material 56
and second semiconductive material portion 46 are oxidized in a
common oxidizing step. Such oxidizing is effective to form both a
gate oxide layer 58 of what will be a non-FLASH transistor gate
overlying second semiconductive material portion 46, and silicon
dioxide 60 as part of second gate dielectric material 56 of what
will be a FLASH transistor gate. Any suitable oxidizing conditions
are contemplated. Preferred oxidizing conditions include a
temperature of about 850 degrees C. to about 1100 degrees C.
Further, chamber 59 might constitute a conventional furnace, a
rapid thermal processor, or any other existing or yet-to-be
developed chamber suitable for oxidizing the substrate.
[0023] One preferred method includes exposing the silicon nitride
of second gate dielectric material 56 and the second semiconductive
material portion 46 to atomic oxygen. Example techniques for doing
so are disclosed in our co-pending U.S. patent application Ser. No.
09/653,281, filed on Aug. 31, 2000, having inventors Kevin L.
Beaman et. al., entitled Use of Atomic Oxidation for Fabrication of
Oxide-Nitride-Oxide Stack for Flash Memory Devices, which is hereby
incorporated by reference. The atomic oxygen might be supplied by
an ozone source, a microwave source, by photo-excitation, by in
situ steam generation, or other method. A more specific example
includes injecting hydrogen and oxygen gas into the processing
chamber effective to generate atomic oxygen proximate the
substrate. One example process would include heating the substrate
to a temperature of about 850 degrees C. to about 1100 degrees C.
prior to injecting the hydrogen and oxygen. A preferred pressure
range within the reactor during processing, by way of example only,
is from 5 to 10 Torr. Such processing is also preferably effective
to generate steam along with the atomic oxygen proximate the
substrate. A more specific example includes injecting hydrogen and
oxygen gas into the processing chamber effective to form a mixture
of gasses comprising about 0.5% to about 33% hydrogen gas by
volume. Regardless, the hydrogen gas within the chamber will have
partial pressure which can be varied to control a rate at which the
silicon nitride will be oxidized, with increasing of the partial
pressure of the hydrogen gas tending to increase the rate at which
the silicon nitride is oxidized. In one preferred embodiment,
second semiconductive material portion 46 will be oxidized at one
rate, and silicon nitride of second gate dielectric material 56
will be oxidized at another rate which is from about 10% to about
70% of the first rate, whereby the respective thicknesses of the
oxide comprising layer 60 and oxide comprising layer 58 can be
selectively different.
[0024] Referring to FIG. 6, a first gate material 64 is formed over
second gate dielectric material 56 and a second gate material 66 is
formed over gate oxide layer 58 over second semiconductive material
portion 46 in the fabrication of a non-FLASH transistor gate. Such
materials might be the same or different materials, might be of the
same or different thicknesses, and might be formed in the same or
different processing steps. Preferably, such are formed in the same
step, with conductively doped polysilicon being an example
material.
[0025] Referring to FIG. 7, an insulative capping layer 70 has been
formed over the respective first and second gate materials.
Exemplary preferred materials include silicon dioxide and silicon
nitride.
[0026] Referring to FIG. 8, the illustrated layers have been
fabricated to form a FLASH field effect transistor gate 72 and a
non-FLASH field effect transistor gate 74. Source and drain regions
76 are also shown as having been provided within semiconductive
material portions 44 and 46.
[0027] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *