U.S. patent application number 10/337978 was filed with the patent office on 2003-07-10 for semiconductor device and method for manufacturing the same.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Miyano, Kiyotaka, Ozawa, Yoshio, Saida, Shigehiko, Tanaka, Masayuki.
Application Number | 20030127695 10/337978 |
Document ID | / |
Family ID | 19190850 |
Filed Date | 2003-07-10 |
United States Patent
Application |
20030127695 |
Kind Code |
A1 |
Ozawa, Yoshio ; et
al. |
July 10, 2003 |
Semiconductor device and method for manufacturing the same
Abstract
A semiconductor device includes a semiconductor device
comprising a semiconductor substrate, source/drain regions formed
in the semiconductor substrate, a gate insulation film formed on
the semiconductor substrate, a gate electrode formed on the gate
insulation film between the source/drain regions, and a gate
sidewall spacer formed on side surfaces of the gate electrode,
wherein the gate sidewall spacer is composed of silicon oxide
containing 0.1-30 atomic % of chlorine.
Inventors: |
Ozawa, Yoshio;
(Yokohama-shi, JP) ; Tanaka, Masayuki;
(Yokohama-shi, JP) ; Miyano, Kiyotaka;
(Fujisawa-shi, JP) ; Saida, Shigehiko;
(Yokkaichi-shi, JP) |
Correspondence
Address: |
Finnegan, Henderson, Farabow,
Garrett & Dunner, L.L.P.
1300 I Street, N.W.
Washington
DC
20005-3315
US
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
|
Family ID: |
19190850 |
Appl. No.: |
10/337978 |
Filed: |
January 8, 2003 |
Current U.S.
Class: |
257/382 ;
257/E29.152 |
Current CPC
Class: |
H01L 29/4983 20130101;
H01L 29/6656 20130101; H01L 29/41783 20130101 |
Class at
Publication: |
257/382 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 10, 2002 |
JP |
2002-003192 |
Claims
What is claimed is:
1. A semiconductor device comprising: a semiconductor substrate;
source/drain regions formed in the semiconductor substrate; a gate
insulation film formed on the semiconductor substrate; a gate
electrode formed on the gate insulation film between the
source/drain regions; and a gate sidewall spacer formed on side
surfaces of the gate electrode, wherein the gate sidewall spacer is
composed of silicon oxide containing 0.1-30 atomic % of
chlorine.
2. The semiconductor device according to claim 1, wherein the gate
electrode has a gate length of 0.2 .mu.m or less.
3. The semiconductor device according to claim 1, wherein each of
the source/drain regions has an elevated source/drain
structure.
4. The semiconductor device according to claim 1, wherein a metal
silicide layer is formed on an upper surface of the gate electrode
and each of the source/drain regions.
5. A semiconductor device comprising: a semiconductor substrate;
source/drain regions formed in the semiconductor substrate; a gate
insulation film formed on the semiconductor substrate; a gate
electrode formed on the gate insulation film between the
source/drain regions and covered with a gate protecting insulation
film; and a gate sidewall spacer formed on side surfaces of the
gate electrode, wherein the gate sidewall spacer is composed of
silicon oxide containing 0.1-30 atomic % of chlorine.
6. The semiconductor device according to claim 5, wherein the gate
protecting insulation film is composed of silicon oxide containing
0.1-30 atomic % of chlorine.
7. The semiconductor device according to claim 5, wherein the gate
electrode has a gate length of 0.2 .mu.m or less.
8. The semiconductor device according to claim 5, wherein each of
the source/drain regions has an elevated source/drain
structure.
9. The semiconductor device according to claim 5, wherein a metal
silicide layer is formed on an upper surface of the gate electrode
and each of the source/drain regions.
10. A method for manufacturing a semiconductor device, comprising:
forming source/drain regions in a semiconductor substrate; forming
a gate insulation film on the semiconductor substrate; forming a
gate electrode on the gate insulation film between the source/drain
regions; forming an insulation film composed of a silicon nitride
film containing chlorine on side surfaces of the gate electrode;
and converting the silicon nitride film by oxidation reaction
processing into silicon oxide film containing 0.1-30 atomic % of
chlorine to provide a gate sidewall spacer.
11. The method according to claim 10, wherein the conversion into
the silicon oxide is accomplished by oxidizing reaction using water
vapor as a main oxidation agent.
12. The method according to claim 10, wherein the conversion into
the silicon oxide is accomplished by oxidizing reaction under a
pressure in excess of the atmospheric pressure.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2002-003192, filed Jan. 10, 2002; the entire contents of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a MOS transistor having an
improved sidewall of a gate electrode and a method for
manufacturing the same.
[0004] 2. Description of the Related Art
[0005] As a structure of a semiconductor device is patterned finer,
parasitic capacitance which is inevitably present in an element
structure gives rise to a larger problem. For example, the
parasitic capacitance, which occurs between a gate electrode and a
source/drain region which provides a MOS transistor, reduces an
operating speed of the transistor and has a larger effect as the
elements are patterned finer.
[0006] FIG. 7A shows part of a gate electrode structure of a
conventional MOS transistor. Provided on a semiconductor substrate
111 such as silicon is a gate insulation film 112 such as a silicon
oxide film, on which a gate electrode 113 is formed. A source/drain
region 116 is formed in the semiconductor substrate 111. Side and
upper surfaces of the gate electrode 113 are covered with a gate
protecting insulation film (Sidewall Oxide Layer) 114, and the side
surface of the protecting insulation film 114 is covered with a
gate sidewall insulation film (Sidewall Spacer) 115 such as a
silicon nitride film.
[0007] In the MOS transistor having such a configuration, the gate
protection film 114 and the gate sidewall insulation film 115 are
interposed as a dielectric between the gate electrode 113 and the
source/drain diffusion region 116 (including a wiring layer
thereof), so that there occurs unwanted parasitic capacitance.
[0008] Parasitic capacitance reduces the operating speed of the
transistor. Especially in a fine-patterned transistor having a gate
length of 0.2 .mu.m or less, the parasitic capacitance reduces the
operating speed greatly.
[0009] Furthermore, a MOS transistor having an elevated
source/drain configuration shown in FIG. 7B has an elevated
source/drain layer 117 which overlies the source/drain region 116
and is in contact with the gate sidewall spacer 115. This MOS
transistor similarly suffers from drastic reduction in operating
speed owing to large parasitic capacitance between the gate
electrode 113 and the elevated source/drain layer 117 (including
the wiring layer thereof) where the gate protection film 114 and
the gate sidewall spacer 115 are interposed therebetween.
[0010] Although silicon oxide has been used as a material of the
gate sidewall spacer conventionally, silicon nitride with high
dielectric constant is used recently for a later-described reason.
This has made the problem of parasitic capacitance further
serious.
[0011] FIGS. 8A-8D and FIGS. 9A-9C show a method for manufacturing
a MOS transistor in a case where a conventional gate sidewall
spacer is made of silicon oxide.
[0012] As shown in FIG. 8A, after a gate oxide film 122 is formed
on a silicon semiconductor substrate 121, a polysilicon film is
deposited by Chemical Vapor Deposition (CVD) and processed by
Reactive Ion Etching (RIE) to form a gate electrode 123
thereof.
[0013] As shown in FIG. 8B, an exposed surface of the gate
electrode 123 is oxidized to form a gate protecting insulation film
124. Then, a part 125 of a source/drain diffusion region is formed
in the semiconductor substrate 121 by ion implantation.
[0014] As shown in FIG. 8C, a silicon oxide film is deposited by
CVD over the substrate surface and then removed by RIE to form a
gate sidewall spacer 126 thereof. In this case, the exposed surface
of the semiconductor substrate 121 is damaged by ions, so that a
roughened exposed surface is formed on the one part 125 of the
source/drain region.
[0015] As shown in FIG. 8D, a source/drain diffusion region 127 is
formed in the semiconductor substrate 121 by ion implantation. In
this case, since the surface of the semiconductor substrate 121 is
roughened, variation in the shape of the diffusion regions occurs
among the elements, which results in increased fluctuations in
operating characteristics thereof.
[0016] As shown in FIG. 9A, the oxide film is removed from the
upper surface of the gate electrode 123 using dilute hydrofluoric
acid. In this case, the gate protection film 124 and the gate
sidewall insulation film 126 are also removed partially. There are
some cases where the insulation film 126 of the sidewall spacer is
left little by a type of the MOS transistor formed on the
semiconductor substrate 121. Next, as shown in FIG. 9B, a cobalt
layer 128 is deposited over the substrate surface by
sputtering.
[0017] As shown in FIG. 9C, a cobalt silicide layer 129 is provided
on the gate electrode 123 and the source/drain region 127 by lamp
heating. Thereafter, a non-reacted the cobalt layer is removed. In
this case, in the MOS transistor in which the insulation film of
the gate sidewall spacer is not almost left, the gate electrode 123
and the source/drain region 127 are electrically connected through
the cobalt silicide layer 129, thereby reducing the yield.
[0018] To eliminate such a problem in this case of using the
silicon oxide as the gate sidewall spacer, a silicon nitride film
has been used as the gate sidewall spacer as shown in FIGS. 10A-10D
and FIGS. 11A-11C.
[0019] After a gate oxide film 132 is formed on a semiconductor
substrate 131 such as silicon, a gate electrode 133 such as a
polysilicon film is formed thereon (FIG. 10A). Next, an exposed
surface of the gate electrode 133 is oxidized to form a gate
protection insulation film 134. Then, a part 135 of a source/drain
diffusion region is formed in the semiconductor substrate 131 by
ion implantation (FIG. 10B). A silicon nitride film is deposited
over the substrate surface by CVD and then selectively removed by
RIE to provide a gate sidewall insulation spacer 136 on a side
surface of the gate protection film 134.
[0020] According to the method, as shown in FIG. 10C, since the
exposed face of the semiconductor substrate 131 can be prevented
from being roughened, the shape of the source/drain diffusion
region 137 does not vary among elements as shown in FIG. 10D.
Therefore, it is possible to reduce fluctuations in operating
characteristics of the elements.
[0021] Furthermore, as shown in FIG. 11A, the gate sidewall spacer
is not removed during processing by use of dilute hydrofluoric
acid, so that as shown in FIG. 11C the gate electrode 133 and the
source/drain region 137 are not electrically connected, thereby
preventing the yield from being deteriorated.
[0022] According to this method, however, since the dielectric
constant of the gate sidewall spacer is about twice as large as
that of the conventional silicon oxide film, the parasitic
capacitance is roughly doubled, thus greatly reducing the operating
speed of the element.
[0023] In this MOS transistor, a cobalt layer 138 is deposited over
the surface of the semiconductor substrate 131 by sputtering (FIG.
11B). Then, using the lamp heating, a cobalt silicide layer 139 is
formed on the gate electrode 133 and the source/drain region 137
(FIG. 11C). A non-reacted cobalt layer is removed.
[0024] The above-mentioned problem occurs also in a case of forming
a MOS transistor having an elevated source/drain structure shown in
FIGS. 12A-12D.
[0025] That is, FIGS. 12A-12D show a method for manufacturing a MOS
transistor in a case of forming the gate sidewall spacer using the
silicon oxide.
[0026] As shown in FIG. 12A, after a gate oxide film 142 is formed
on a semiconductor substrate 141 such as silicon, a polysilicon
film and a silicon nitride film are deposited consecutively by CVD
and processed by RIE to form a gate electrode 143 and a silicon
nitride film 144 sequentially.
[0027] As shown in FIG. 12B, after an exposed surface of the gate
electrode 143 is oxidized to form a gate protection film 145, a
part 146 of a source/drain diffusion region is formed in the
silicon substrate by ion implantation.
[0028] As shown in FIG. 12C, a silicon oxide film is deposited over
the surface of the semiconductor substrate 141 by CVD and then
removed by RIE to form a gate sidewall spacer 147. In this case,
the silicon semiconductor substrate is exposed partially and
subjected to impact by ions, thereby providing a roughened surface
thereon.
[0029] As shown in FIG. 12D, an elevated source/drain layer 148 is
formed by epitaxial growth of silicon. In this case, a gap 150
called a facet is formed between the gate sidewall spacer 147 and
the elevated layer 148.
[0030] A source/drain diffusion region 149 is formed in the
semiconductor substrate 141 by ion implantation. In this case, a
diffusion region under the facet is formed deep, so that it is
difficult to control a threshold value of the transistor owing to
the short-channel effect.
[0031] Therefore, a manufacturing method using a silicon nitride
film is used as shown in FIGS. 13A-13D.
[0032] That is, as shown in FIG. 13A, after a gate oxide film 152
is formed on a semiconductor substrate 151 such as silicon, a
polysilicon film and a silicon nitride film are deposited
consecutively by CVD and processed by RIE to provide a gate
electrode 153 and a silicon nitride film 154 sequentially.
[0033] As shown in FIG. 13B, after an exposed surface of the gate
electrode 153 is oxidized to form a gate protection film 155, a
part 156 of a source/drain diffusion region is formed in the
silicon substrate 151 by ion implantation.
[0034] As shown in FIG. 13C, a silicon nitride film is deposited
over the surface of the semiconductor substrate 151 by CVD and then
removed from the flat portion by RIE to form a gate sidewall spacer
157.
[0035] According to the method, the surface of the semiconductor
substrate in which the diffusion layer is formed is not roughened
and, in addition, a gap called a facet is not formed between the
gate sidewall spacer 157 and the elevated layer 158 as shown in
FIG. 13D. Therefore, the source/drain diffusion region is formed
just as designed, so that the threshold value of the transistors
can be controlled easily.
[0036] According to this method, however, the dielectric constant
of the gate sidewall spacer is about twice as large as that of a
conventional silicon oxide film, so that the parasitic capacitance
is also doubled approximately, thus greatly reducing the operating
speed of the elements.
[0037] As described above, to suppress variations in shape of the
source/drain diffusion region thereby to prevent an undesired
failure of short-circuiting at the time of salicide formation, a
silicon nitride film is used as at least part of the gate sidewall
spacer of the fine-patterned transistor. Furthermore, in the
transistor having the elevated source/drain structure, the sidewall
spacer of silicon nitride is used because of the facet formed at
the time of the elevated layer formation. In addition, to prevent
the semiconductor substrate from being dug at the time of forming
the conductor plug connected to the source/drain region, the
transistor is covered with a so-called liner film of a silicon
nitride film.
[0038] Such silicon nitride present around these transistors has
higher dielectric constant than silicon oxide and so increases the
parasitic capacitance, thus greatly reducing the operating speed of
the transistors. Furthermore, trapped charge, distortions,
hydrogen, etc. present in the silicon nitride film cause
fluctuations in characteristics of the transistors, thus reducing
device reliabilities.
BRIEF SUMMARY OF THE INVENTION
[0039] According to a first aspect of the present invention, a
semiconductor device comprises: a semiconductor substrate;
source/drain regions formed in the semiconductor substrate; a gate
insulation film formed on the semiconductor substrate; a gate
electrode formed on the gate insulation film between the
source/drain regions; and a gate sidewall spacer formed on side
surfaces of the gate electrode, wherein the gate sidewall spacer is
composed of silicon oxide containing 0.1-30 atomic % of
chlorine.
[0040] According to a second aspect of the present invention, a
semiconductor device comprises: a semiconductor substrate;
source/drain regions formed in the semiconductor substrate; a gate
insulation film formed on the semiconductor substrate; a gate
electrode formed on the gate insulation film between the
source/drain regions and covered with a gate protecting insulation
film; and a gate sidewall spacer formed on side surfaces of the
gate electrode, wherein the gate sidewall spacer is composed of
silicon oxide containing 0.1-30 atomic % of chlorine.
[0041] According to a third aspect of the present invention, a
method for manufacturing a semiconductor device comprises forming
source/drain regions in a semiconductor substrate; forming a gate
insulation film on the semiconductor substrate; forming a gate
electrode on the gate insulation film between the source/drain
regions; forming an insulation film composed of a silicon nitride
film containing chlorine on side surfaces of the gate electrode;
and converting the silicon nitride film by oxidation reaction
processing into silicon oxide film containing 0.1-30 atomic % of
chlorine to provide a gate sidewall spacer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0042] FIG. 1 is a plan view of a transistor according to a first
embodiment;
[0043] FIGS. 2A and 2B are cross-sectional views of the transistor
according to the first embodiment and FIG. 2A is a cross-sectional
view taken along line II-II of FIG. 1;
[0044] FIG. 3 is a graph for explaining a relationship between a
concentration of chlorine in a silicon oxide film and a rate of
change in dielectric constant of the silicon oxide film;
[0045] FIGS. 4A to 4D are cross-sectional views for explaining a
transistor manufacturing method according to a second
embodiment;
[0046] FIGS. 5A to 5D are cross-sectional views for explaining the
transistor manufacturing method according to the second
embodiment;
[0047] FIGS. 6A to 6D are cross-sectional views for explaining a
transistor manufacturing method according to a third
embodiment;
[0048] FIGS. 7A to 7B are cross-sectional views for explaining a
conventional transistor manufacturing method;
[0049] FIGS. 8A to 8D are cross-sectional views for explaining the
conventional transistor manufacturing method;
[0050] FIGS. 9A to 9C are cross-sectional views for explaining the
conventional transistor manufacturing method;
[0051] FIGS. 10A to 10D are cross-sectional views for explaining
the conventional transistor manufacturing method;
[0052] FIGS. 11A to 11C are cross-sectional views for explaining
the conventional transistor manufacturing method;
[0053] FIGS. 12A to 12D are cross-sectional views for explaining
the conventional transistor manufacturing method; and
[0054] FIGS. 13A to 13D are cross-sectional views for explaining
the conventional transistor manufacturing method.
DETAILED DESCRIPTION OF THE INVENTION
[0055] The following will describe embodiments with reference to
drawings.
[0056] First, a first embodiment is described with reference to
FIGS. 1-3.
[0057] As shown in FIG. 1 and FIGS. 2A-2B, on a semiconductor
substrate 11 such as silicon is formed a gate insulation film 12 of
a silicon oxide film, on which a gate electrode 13 of polysilicon
is provided. Source/drain regions 16 are provided in the
semiconductor substrate 11. Side and upper surfaces of the gate
electrode 13 are covered with a gate protection insulation film
(sidewall oxide layer) 14 of a silicon oxide film, in addition to
which, the side surfaces covered with the protection film 14 are
further covered with a gate sidewall insulation film (sidewall
spacer) 15. A gate length L is, for example, 0.2 .mu.m or less. In
a MOS transistor having such a structure, the parasitic capacitance
occurs between the gate electrode 13 and a source/drain diffusion
region 16 (including a wiring layer).
[0058] Furthermore, in a semiconductor device having an elevated
source/drain construction shown in FIG. 2B, provided on a
semiconductor substrate is an elevated source/drain layer 17 made
of, for example, monocrystal silicon which is on the source/drain
region 16 and in contact with the gate sidewall spacer 15. The
parasitic capacitance occurs between the gate electrode 13 and the
elevated source/drain layer 17 (including the wiring layer) where
the gate protection film 14 and the gate sidewall spacer 15 are
interposed therebetween.
[0059] It is to be noted that the gate sidewall spacer 15 used in
the semiconductor device shown in FIGS. 2A-2B is composed of
silicon oxide containing chlorine. For example, a silicon oxide
film containing chlorine can be formed by plasma CVD using a
silicon source gas containing chlorine such as a dichlorosilane
(SiH.sub.2Cl.sub.2) gas or a tetrachlorosilane (SiCl.sub.4) gas and
an oxygen source gas such as a dinitrogen monoxide (N.sub.2O) gas
or SiO.sub.2 CVD with a chlorine (Cl.sub.2) gas or a hydrogen
chloride (HCl) gas as an additional source gas.
[0060] FIG. 3 is a graph for explaining dependency of a rate of
change in dielectric constant of a silicon oxide film containing
chlorine on a chlorine concentration. A vertical axis represents
the rate of change in the dielectric constant and a horizontal
axis, a concentration of chlorine (atomic %) in the silicon oxide
film.
[0061] FIG. 3 shows a relationship between the rate of change in
the dielectric constant of the silicon oxide film containing
chlorine and the chlorine concentration shown in Table 1. If the
chlorine concentration of the silicon oxide film containing
chlorine is set to 0.1 atomic % or higher, the dielectric constant
of this silicon oxide film decreases essentially, thus enabling
essentially reducing parasitic capacitance between the gate
electrode 13 and the source/drain diffusion region 16 including the
wiring layer (not shown) and that between the gate electrode 13 and
the elevated source/drain layer 17 (including the wiring layer). It
is to be noted that if the chlorine concentration is set to 1
atomic % or more, the parasitic capacitance can be reduced by 5% or
more, so that a remarkable advantage will be obtained especially in
a fine-patterned transistor having a gate length of 0.2 .mu.m or
less.
[0062] In such a semiconductor device, the parasitic capacitance
can be reduced, so that the thickness of the gate sidewall spacer
can be decreased, thus further promoting fine patterning of the
elements. Furthermore, by containing chlorine in the silicon oxide
film providing the gate protection film which covers an exposed
portion of the gate electrode, the parasitic capacitance can be
reduced between the gate electrode and the source/drain region or
the elevated source/drain layer.
[0063] There is no upper limit in principle on the concentration of
chlorine contained in the silicon oxide film. If the chlorine
concentration increases, however, a hygroscopic property of silicon
oxide becomes remarkable, thus rather increasing the dielectric
constant in some cases depending on a method of forming elements.
It is, therefore, preferable to set the concentration of chlorine
in the silicon oxide film to 30 atomic % or less essentially.
[0064] Furthermore, to reduce the dielectric constant, fluorine can
be introduced into the silicon oxide. Fluorine, however, has an
adverse effect such as promotion of diffusion of boron on a
fine-patterned transistor, so that it cannot suitably be used in
place of chlorine and preferably be used appropriately together
with chlorine as occasion demands.
1 TABLE 1 Concentration of Rate of change in chlorine in silicon
dielectric constant oxide film containing of silicon oxide film
chlorine (atom %) containing chlorine 0.01 1 0.1 0.99 1 0.95 5 0.87
13 0.76 16 0.71 30 0.59
[0065] The following will describe a second embodiment with
reference to FIGS. 4A-4D and FIGS. 5A-5D.
[0066] As shown in FIG. 4A, on a surface of a semiconductor
substrate 21 such as silicon is formed a gate oxide film 22 by
oxidation processing. Then, a polysilicon layer is deposited by CVD
and processed by RIE to form a gate electrode 23. Thereafter, as
shown in FIG. 4B, an exposed surface of the gate electrode 23 is
oxidized to form a gate protection film 24. Then, a part 25 of a
source/drain diffusion region is formed in the semiconductor
substrate 21 by ion implantation. As shown in FIG. 4C, a silicon
nitride film is deposited over the substrate surface by
low-pressure CVD using a hexachlorodisilane (Si.sub.2Cl.sub.6) gas
and an ammonia (NH.sub.3) gas. The film forming condition is, for
example, a temperature of 400.degree. C., a hexachlorodisilane gas
flow rate of 1000 sccm, an ammonia gas flow rate of 10 sccm, and a
pressure of 180 Pa. It has been confirmed by secondary-ion mass
spectroscopy that this silicon nitride film contains about 10
atomic % of chlorine and hydrogen.
[0067] Thereafter, the silicon nitride film is selectively removed
by RIE to provide a gate sidewall nitride film 26. In this case, by
setting the RIE rate of the gate oxide film 22 lower than that of
the gate sidewall nitride film 26, the surface of the semiconductor
substrate can be prevented from being roughened.
[0068] As shown in FIG. 4D, a source/drain diffusion region 27 is
formed in the semiconductor substrate 21 by ion implantation. In
this case, since the surface of the semiconductor substrate is
prevented from being roughened, it is possible to suppress the
shape of the diffusion region from being varied from one another.
This results in elimination of fluctuations in operating
characteristics of the elements.
[0069] Next, as shown in FIG. 5A, the gate oxide film is removed
from both the upper surface of the gate electrode 23 and the
surface of the source/drain region 27 using dilute hydrofluoric
acid. In this case, since the silicon nitride film is not almost
etched, the gate sidewall spacer 26 remains in a desired shape on
all of the elements.
[0070] As shown in FIG. 5B, a cobalt layer 28 is deposited over the
substrate surface by sputtering. Then, as shown in FIG. 5C, a
cobalt silicide layer 29 is formed by the lamp heating on the upper
surface of the gate electrode 23 and the surface of the
source/drain region 27.
[0071] Thereafter, a non-reacted portion of the cobalt layer is
removed. In this case, since the gate sidewall spacer 26 is formed
already, the gate electrode 23 and the source/drain diffusion
region 27 do not electrically connected to each other, thereby
essentially avoiding a problem of a decrease in yield.
[0072] As shown in FIG. 5D, the gate sidewall spacer 26 of the
nitride film can be annealed in a water vapor atmosphere to be
converted into a silicon oxide film containing chlorine, which is
provided as the gate sidewall insulation film 26'. The annealing
condition is given by, for example, a temperature of 150.degree. C.
and a pressure of 2 atmospheres. It has been confirmed by
secondary-ion mass spectroscopy that this silicon oxide film
contains of the order of 1 atomic % of chlorine and hydrogen.
[0073] Thereafter, an interlevel insulation film, a wiring layer,
etc. are formed on the semiconductor substrate by a known method,
thus completing the MOS transistor. In this case, since the nitride
film of the gate sidewall spacer is converted into the silicon
oxide film already, the parasitic capacitance is reduced between
the gate electrode 23 and the source/drain diffusion region 27
including the wiring layer, thus avoiding a decrease in operating
speed of the elements.
[0074] In the above-described processing, the silicon nitride film
is converted into the silicon oxide film with annealing in the
water vapor atmosphere. However, an oxidizing atmosphere of oxygen,
ozone, etc., or an atmosphere of a mixture may be also used. A
water vapor atmosphere, however, is suitable because the silicon
nitride film is converted into the silicon oxide film even at a low
temperature. Furthermore, annealing may be conducted at a pressure
of 1 atmosphere or less but preferably be conducted at a pressure
higher than 1 atmosphere.
[0075] The following will describe a third embodiment with
reference to FIGS. 6A-6D.
[0076] In description of the present embodiment, steps are
explained for manufacturing a transistor having an elevated
source/drain structure.
[0077] First, as shown in FIG. 6A, on a semiconductor substrate 31
such as silicon is formed a gate insulation film 32 such as a
silicon oxide film. Then, a polysilicon layer and a silicon nitride
film 34 which serves as a mask for RIE processing are deposited by
CVD consecutively, and the polysilicon is processed by RIE to form
a gate electrode 33. Subsequently, an exposed surface of the gate
electrode 33 is oxidized to form a gate protecting insulation film
35. Then, a part 36 of a source/drain diffusion region is formed in
the semiconductor substrate 31 by ion implantation.
[0078] As shown in FIG. 6B, a silicon nitride film is deposited
over the substrate surface by low-pressure CVD using a
hexachlorodisilane (Si.sub.2Cl.sub.6) gas and an ammonia (NH.sub.3)
gas. A film forming condition is given by, for example, a
temperature of 400.degree. C., a hexachlorodisilane gas flow rate
of 1000 sccm, an ammonia gas flow rate of 10 sccm, and a pressure
of 180 Pa. Then, the silicon nitride film is removed by RIE to
provide a gate sidewall nitride film 37. In this case, by setting
the RIE rate of the gate oxide film 32 lower than that of the gate
sidewall nitride film 37, the surface of the semiconductor
substrate 31 is prevented from being roughened.
[0079] As shown in FIG. 6C, an elevated source/drain layer 38 is
formed by epitaxial growth of silicon. The forming condition is
given by, for example, a temperature of 600.degree. C., a
dichlorosilane (SiH.sub.2Cl.sub.2) gas flow rate of 300 sccm, a
germane (GeH.sub.4) gas flow rate of 10 sccm, an hydrogen chloride
gas flow rate of 100 sccm, a hydrogen gas flow rate of 1500 sccm,
and a pressure of 2 kPa. In this case, since the sidewall spacer 37
is adjoined, a gap called the facet is not formed. The reason for
use of the germane gas is to lower the forming temperature when the
elevated layer 38 is produced. If the elevated layer is formed at a
high temperature, the silicon nitride film is densified and cannot
be easily converted into the silicon oxide film later. A
source/drain diffusion region 39 is formed in the silicon substrate
by ion implantation. In this case, the unwanted facet is prevented
from being formed, so that it is possible to suppress the variation
in the shape of the diffusion regions. Therefore, the threshold
values of the transistors can be controlled easily.
[0080] As shown in FIG. 6D, by annealing the sidewall nitride film
37 in a water vapor atmosphere, it is converted into the silicon
oxide film containing chlorine, thereby providing the gate sidewall
spacer 37'. The annealing condition is given by, for example, a
temperature of 400.degree. C. and a pressure of 1 atmosphere. It
has been confirmed by secondary-ion mass spectroscopy that this
silicon oxide film contains about 0.1 atom % of chlorine and
hydrogen.
[0081] Thereafter, an interlevel insulation film, a wiring layer,
etc. are provided on the semiconductor substrate by a known method,
thus completing the MOS transistor.
[0082] In this case, since the gate sidewall insulation film is
converted into the silicon oxide film already, parasitic
capacitance is reduced between the gate electrode 33 and the
source/drain diffusion region 38 including the wiring layer, thus
avoiding a decrease in operating speed of the elements.
[0083] Besides the above-mentioned embodiments, it is possible to
convert a silicon nitride film, which is present around a
transistor, into a silicon oxide film after the element is
completed. Once it is converted into an oxide, it is possible to
prevent a decrease in operating speed of the transistor,
reliability of the device, etc. owing to the silicon nitride film
having a high dielectric constant.
[0084] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general invention concept as defined by the
appended claims and their equivalents.
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