U.S. patent application number 10/329219 was filed with the patent office on 2003-06-26 for copper interconnection and the method for fabricating the same.
This patent application is currently assigned to NEC Electronics Corporation. Invention is credited to Fujii, Akiko.
Application Number | 20030118798 10/329219 |
Document ID | / |
Family ID | 19188626 |
Filed Date | 2003-06-26 |
United States Patent
Application |
20030118798 |
Kind Code |
A1 |
Fujii, Akiko |
June 26, 2003 |
Copper interconnection and the method for fabricating the same
Abstract
A copper interconnection where holes in the vicinity of an
interface are reduced to lower contribution of interface diffusion
to Cu the EM, increase a lifetime, and simultaneously increase
adhesiveness and resistance to stress migration is constituted in a
manner that impurities 15 form a solid solution in the vicinity of
an interface between a Cu layer 16 and a barrier metal layer 12,
the impurities are precipitated, and an amorphous Cu layer 14 is
fabricated, or a compound with Cu is fabricated. The copper
interconnection is also constituted in a manner that impurities 15
form a solid solution in the vicinity of an interface between the
Cu layer 16 and a cap layer 19, the impurities 15 are precipitated,
and an amorphous Cu layer 14 is fabricated, or a compound with Cu
is fabricated.
Inventors: |
Fujii, Akiko; (Kanagawa,
JP) |
Correspondence
Address: |
SCULLY SCOTT MURPHY & PRESSER, PC
400 GARDEN CITY PLAZA
GARDEN CITY
NY
11530
|
Assignee: |
NEC Electronics Corporation
Kanagawa
JP
|
Family ID: |
19188626 |
Appl. No.: |
10/329219 |
Filed: |
December 24, 2002 |
Current U.S.
Class: |
428/209 ;
204/192.17; 257/751 |
Current CPC
Class: |
H01L 21/76859 20130101;
H01L 21/76849 20130101; H01L 21/76843 20130101; H01L 21/76805
20130101; H01L 21/76873 20130101; H01L 23/53295 20130101; H01L
21/76883 20130101; H01L 23/53238 20130101; H01L 21/76867 20130101;
B32B 15/01 20130101; H01L 21/76855 20130101; H01L 2924/0002
20130101; Y10T 428/24917 20150115; H01L 2924/0002 20130101; H01L
2924/00 20130101 |
Class at
Publication: |
428/209 ;
204/192.17; 257/751 |
International
Class: |
B32B 015/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 25, 2001 |
JP |
392399/2001 |
Claims
What is claimed is:
1. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; and hole
reduction impurities added to said Cu precipitated in a first
interface in order to reduce holes fabricated in said first
interface between said Cu or Cu alloy layer and said barrier metal
layer.
2. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; and hole
reduction impurities added to said Cu to fabricate a solid solution
with said Cu in a first interface in order to reduce holes
fabricated in said first interface between said Cu or Cu alloy
layer and said barrier metal layer.
3. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; and a
hole reduction amorphous layer present in a first interface, in
which said Cu is made amorphous, in order to reduce holes
fabricated in said first interface between said Cu or Cu alloy
layer and said barrier metal layer.
4. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; and a
hole reduction compound layer present in a first interface, in
which a compound with said Cu is fabricated, in order to reduce
holes fabricated in said first interface between said Cu or Cu
alloy layer and said barrier metal layer.
5. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer; and hole reduction
impurities added to said Cu precipitated in a second interface in
order to reduce holes fabricated in said second interface between
said Cu or Cu alloy layer and said insulating cap layer.
6. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer; and hole reduction
impurities added to said Cu to fabricate a solid solution with said
Cu in a second interface in order to reduce holes fabricated in
said second interface between said Cu or Cu alloy layer and said
insulating cap layer.
7. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer; and a hole
reduction amorphous layer present in a second interface, in which
said Cu is made amorphous, in order to reduce holes fabricated in
said second interface between said Cu or Cu alloy layer and said
insulating cap layer.
8. A copper interconnection comprising: a barrier metal layer
fabricated on an interconnection groove; a Cu or Cu alloy layer for
an interconnection fabricated on said barrier metal layer; an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer; and a hole
reduction compound layer present in a second interface, in which a
compound with said Cu is fabricated, in order to reduce holes
fabricated in said second interface between said Cu or Cu alloy
layer and said insulating cap layer.
9. The copper interconnection according to claim 1, wherein said
hole reduction impurities added to said Cu is one selected from Nb,
Ta, Si, Ru, and V.
10. The copper interconnection according to claim 5, wherein said
hole reduction impurities added to said Cu is one selected from Nb,
Ta, Si, Ru, and V.
11. A method for manufacturing a copper interconnection,
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a hole reduction impurity
fabricating step(A) of ion-implanting hole reduction impurities in
said barrier metal in order to reduce holes fabricated in a first
interface between a Cu or Cu alloy layer for an interconnection and
said barrier metal layer after said barrier metal sputtering step,
and executing heat treatment; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said hole reduction
impurity fabricating step(A); a Cu depositing step of depositing Cu
which makes an interconnection on said seed Cu after said seed Cu
sputtering step; and, thereby making said hole reduction impurities
precipitate in said vicinity of said first interface.
12. The method for manufacturing a copper interconnection,
according to claim 11, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a solid solution of said hole reduction
impurities with said Cu in said vicinity of said first
interface.
13. The method for manufacturing a copper interconnection,
according to claim 11, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, making said hole reduction impurities a Cu amorphous in
said vicinity of said first interface.
14. The method for manufacturing a copper interconnection,
according to claim 11, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a Cu compound with said Cu in said vicinity
of said first interface.
15. A method for manufacturing a copper interconnection,
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a hole reduction impurity
fabricating step(B) of depositing hole reduction impurities by a
solid phase in order to reduce holes fabricated in a first
interface between a Cu or Cu alloy layer for an interconnection and
said barrier metal layer after said sputtering step, and diffusing
said impurities by heat; a seed Cu sputtering step of sputtering
seed Cu which becomes a seed after said hole reduction impurity
fabricating step(B); a Cu depositing step of depositing Cu which
makes an interconnection on said seed Cu after said seed Cu
sputtering step; and, thereby making said hole reduction impurities
precipitate in said vicinity of said first interface.
16. The method for manufacturing a copper interconnection,
according to claim 15, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a solid solution of said hole reduction
impurities with said Cu in said vicinity of said first
interface.
17. The method for manufacturing a copper interconnection,
according to claim 15, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a Cu compound with said Cu in said vicinity
of said first interface.
18. A method for manufacturing a copper interconnection,
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a hole reduction impurity fabricating step(A) of
ion-implanting hole reduction impurities in said barrier metal in
order to reduce holes fabricated in a first interface between a Cu
or Cu alloy layer for an interconnection and said barrier metal
layer after said seed Cu sputtering step, and executing heat
treatment; a Cu depositing step of depositing Cu which makes an
interconnection on said seed Cu after said hole reduction impurity
fabricating step(A); and, thereby making said hole reduction
impurities precipitate in said vicinity of said first
interface.
19. The method for manufacturing a copper interconnection,
according to claim 18, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a solid solution of said hole reduction
impurities with said Cu in said vicinity of said first
interface.
20. The method for manufacturing a copper interconnection,
according to claim 18, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, making said hole reduction impurities a Cu amorphous in
said vicinity of said first interface.
21. The method for manufacturing a copper interconnection,
according to claim 18, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said first
interface, fabricating a Cu compound with said Cu in said vicinity
of said first interface.
22. A method for manufacturing a copper interconnection,
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a Cu interconnection fabricating step of embedding
a Cu or Cu alloy layer in said interconnection groove after said
seed Cu sputtering step, and fabricating an interconnection by
using CMP method; a hole reduction impurity fabricating step(C) of
ion-implanting hole reduction impurities in order to reduce holes
fabricated in a second interface between said Cu or Cu alloy layer
and an insulating cap layer fabricated on said Cu or Cu alloy layer
to insulate and protect said Cu or Cu alloy layer after said Cu
interconnection fabricating step, and executing heat treatment; a
natural oxide layer removing step of removing a natural oxide layer
of said Cu by executing treatment such as cleaning and/or plasma
irradiation on a surface of said interconnection after said second
hole reduction impurity fabricating step; an insulating cap layer
sputtering deposition step of depositing said insulating cap layer
by sputtering after said natural oxide layer removing step; and,
thereby making said hole reduction impurities precipitate in said
vicinity of said second interface.
23. The method for manufacturing a copper interconnection,
according to claim 22, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said second
interface, fabricating a solid solution of said hole reduction
impurities with said Cu in said vicinity of said second
interface.
24. The method for manufacturing a copper interconnection,
according to claim 22, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said second
interface, making said hole reduction impurities a Cu amorphous in
said vicinity of said second interface.
25. The method for manufacturing a copper interconnection,
according to claim 22, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said second
interface, fabricating a Cu compound with said Cu in said vicinity
of said second interface.
26. A method for manufacturing a copper interconnection,
comprising: a barrier metal sputtering step of sputtering barrier
metal ion an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a Cu interconnection fabricating step of embedding
a Cu or Cu alloy layer in said interconnection groove after said
seed Cu sputtering step, and fabricating an interconnection by
using CMP method; a hole reduction impurity fabricating step(D) of
depositing hole reduction impurities by a solid phase in order to
reduce holes fabricated in a second interface between said Cu or Cu
alloy layer and an insulating cap layer fabricated on said Cu or Cu
alloy layer to insulate and protect said Cu or Cu alloy layer after
said Cu interconnection fabricating step, and executing heat
treatment; a natural oxide layer removing step of removing a
natural oxide layer of said Cu by executing treatment such as
cleaning and/or plasma irradiation on a surface of said
interconnection after said second hole reduction impurity
fabricating step; an insulating cap layer sputtering deposition
step of depositing said insulating cap layer by sputtering after
said natural oxide layer removing step; and thereby making said
hole reduction impurities precipitate in said vicinity of said
second interface.
27. The method for manufacturing a copper interconnection,
according to claim 26, wherein in place of making said hole
reduction impurities precipitate in said vicinity of said second
interface, fabricating a Cu compound with said Cu in said vicinity
of said second interface.
28. The method for manufacturing a copper interconnection,
according to claim 26, wherein in place of said hole reduction
impurity depositing step, a Cu compound fabricating step of
fabricating a compound with said Cu in said vicinity of said second
interface is executed.
29. The method for manufacturing a copper interconnection,
according to claim 22, wherein said natural oxide layer removing
step is executed after said Cu interconnection fabricating step,
and then said hole reduction impurity fabricating step(C) is
executed.
30. The method for manufacturing a copper interconnection,
according to claim 26, wherein said natural oxide layer removing
step is executed after said Cu interconnection fabricating step,
and then said hole reduction impurity fabricating step(D) is
executed.
31. The method for manufacturing a copper interconnection,
according to claim 11, wherein said hole reduction impurities are
one selected from Nb, Ta, Si, Ru, and V.
32. The method for manufacturing a copper interconnection,
according to claim 15, wherein said hole reduction impurities are
one selected from Nb, Ta, Si, Ru, and V.
33. The method for manufacturing a copper interconnection,
according to claim 18, wherein said hole reduction impurities are
one selected from Nb, Ta, Si, Ru, and V.
34. The method for manufacturing a copper interconnection,
according to claim 22, wherein said hole reduction impurities are
one selected from Nb, Ta, Si, Ru, and V.
35. The method for manufacturing a copper interconnection,
according to claim 26, wherein said hole reduction impurities are
one selected from Nb, Ta, Si, Ru, and V.
36. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in a group of interconnections of said
lower interconnection layer, said upper interconnection layer or
said via hole, wherein said copper interconnection is provided with
a barrier metal layer fabricated on an interconnection groove, a Cu
or Cu alloy layer for an interconnection fabricated on said barrier
metal layer, and hole reduction impurities added to said Cu
precipitated in a first interface in order to reduce holes
fabricated in said first interface between said Cu or Cu alloy
layer and said barrier metal layer.
37. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in a group of interconnections of said
lower interconnection layer, said upper interconnection layer or
said via hole, wherein said copper interconnection is provided with
a barrier metal layer fabricated on an interconnection groove, a Cu
or Cu alloy layer for an interconnection fabricated on said barrier
metal layer, and hole reduction impurities added to said Cu to
fabricate a solid solution in a first interface in order to reduce
holes fabricated in said first interface between said Cu or Cu
alloy layer and said barrier metal layer.
38. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in a group of interconnections of said
lower interconnection layer, said upper interconnection layer or
said via hole, wherein said copper interconnection is provided with
a barrier metal layer fabricated on an interconnection groove, a Cu
or Cu alloy layer for an interconnection fabricated on said barrier
metal layer, and a Cu hole reduction amorphous layer present in a
first interface in order to reduce holes fabricated in said first
interface between said Cu or Cu alloy layer and said barrier metal
layer.
39. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in a group of interconnections of said
lower interconnection layer, said upper interconnection layer or
said via hole, wherein said copper interconnection is provided with
a barrier metal layer fabricated on an interconnection groove, a Cu
or Cu alloy layer for an interconnection fabricated on said barrier
metal layer, and a hole reduction compound layer present in a first
interface, in which a compound with said Cu is fabricated, in order
to reduce holes fabricated in said first interface between said Cu
or Cu alloy layer and said barrier metal layer.
40. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in said lower interconnection layer, said
upper interconnection layer or said via hole, wherein said copper
interconnection is provided with a barrier metal layer fabricated
on an interconnection groove, a Cu or Cu alloy layer for an
interconnection fabricated on said barrier metal layer, an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer, and hole reduction
impurities added to said Cu precipitated in a second interface in
order to reduce holes fabricated in said second interface between
said Cu or Cu alloy layer and said insulating cap layer.
41. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in said lower interconnection layer, said
upper interconnection layer or said via hole, wherein said copper
interconnection is provided with a barrier metal layer fabricated
on an interconnection groove, a Cu or Cu alloy layer for an
interconnection fabricated on said barrier metal layer, an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer, and hole reduction
impurities added to said Cu to fabricate a solid solution in a
second interface in order to reduce holes fabricated in said second
interface between said Cu or Cu alloy layer and said insulating cap
layer.
42. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in said lower interconnection layer, said
upper interconnection layer or said via hole, wherein said copper
interconnection is provided with a barrier metal layer fabricated
on an interconnection groove, a Cu or Cu alloy layer for an
interconnection fabricated on said barrier metal layer, an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer, and a hole
reduction amorphous layer present in a second interface, in which
said Cu is made amorphous, in order to reduce holes fabricated in
said second interface between said Cu or Cu alloy layer and said
insulating cap layer.
43. A copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, comprising: at least one or more copper
interconnections included in said lower interconnection layer, said
upper interconnection layer or said via hole, wherein said copper
interconnection is provided with a barrier metal layer fabricated
on an interconnection groove, a Cu or Cu alloy layer for an
interconnection fabricated on said barrier metal layer, an
insulating cap layer fabricated on said Cu or Cu alloy layer to
protect and insulate said Cu or Cu alloy layer, and a hole
reduction compound layer present in a second interface, in which a
compound with said Cu is fabricated, in order to reduce holes
fabricated in said second interface between said Cu or Cu alloy
layer and said insulating cap layer.
44. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 36, wherein said hole
reduction impurities are one selected from Nb, Ta, Si, Ru, and
V.
45. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 36, wherein said multi-layer
interconnection structure is a single damascene.
46. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 37, wherein said multi-layer
interconnection structure is a single damascene.
47. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 38, wherein said multi-layer
interconnection structure is a single damascene.
48. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 39, wherein said multi-layer
interconnection structure is a single damascene.
49. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 40, wherein said multi-layer
interconnection structure is a single damascene.
50. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 41, wherein said multi-layer
interconnection structure is a single damascene.
51. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 42, wherein said multi-layer
interconnection structure is a single damascene.
52. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 43, wherein said multi-layer
interconnection structure is a single damascene.
53. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 36, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
54. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 37, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
55. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 38, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
56. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 39, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
57. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 40, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
58. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 41, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
59. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 42, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
60. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 43, wherein said multi-layer
interconnection structure is a dual damascene, and said dual
damascene is fabricated in a via first process for fabricating an
interconnection groove after opening of a via.
61. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 36, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
62. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 37, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
63. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 38, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
64. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 39, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
65. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 40, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
66. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 41, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
67. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 42, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
68. The copper interconnection with multi-layers having a lower
interconnection layer of one layer, an upper interconnection layer
positioned on said lower interconnection layer to be different from
said one layer, and a via hole for interconnecting said lower and
upper wring layers, according to claim 43, wherein said dual
damascene is fabricated in a trench first process for opening a via
after fabrication of an interconnection groove.
69. A method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in a
manufacturing process of said copper interconnection, said process
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a hole reduction impurity
fabricating step(A) of ion-implanting hole reduction impurities in
said barrier metal in order to reduce holes fabricated in a first
interface between a Cu or , Cu alloy layer for an interconnection
and said barrier metal layer after said barrier metal sputtering
step, and executing heat treatment; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said hole reduction
impurity fabricating step(A); a Cu depositing step of depositing Cu
which makes an interconnection on said seed Cu after said seed Cu
sputtering step; and, thereby making said hole reduction impurities
precipitate in said vicinity of said first interface.
70. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 69, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
solid solution of said hole reduction impurities with said Cu in
said vicinity of said first interface.
71. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 69, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, making said
hole reduction impurities a Cu amorphous in said vicinity of said
first interface.
72. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper wire, according to claim 69,
wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
Cu compound with said Cu in said vicinity of said first
interface.
73. A method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in a
manufacturing process of said copper interconnection, said process
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a hole reduction impurity
fabricating step(B) of depositing hole reduction impurities by a
solid phase in order to reduce holes fabricated in a first
interface between a Cu or Cu alloy layer for an interconnection and
said barrier metal layer after said sputtering step, and diffusing
said impurities by heat; a hole reduction impurity fabricating step
of implanting ions in said barrier metal to execute heat treatment;
a seed Cu sputtering step of sputtering seed Cu which becomes a
seed after said hole reduction impurity fabricating step(B); a Cu
depositing step of depositing Cu which makes an interconnection on
said seed Cu after said seed Cu sputtering step; and thereby making
said hole reduction impurities precipitate in said vicinity of said
first interface.
74. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 73, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
solid solution of said hole reduction impurities with said Cu in
said vicinity of said first interface.
75. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 73, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
Cu compound with said Cu in said vicinity of said first
interface.
76. A method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on the lower interconnection
layer to be different from said one layer, and a via hole for
interconnecting said lower and upper wring layers, at least one or
more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in a
manufacturing process of said copper interconnection, said process
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a hole reduction impurity fabricating step(A) of
ion-implanting hole reduction impurities in said barrier metal in
order to reduce holes fabricated in a first interface between a Cu
or Cu alloy layer for an interconnection and said barrier metal
layer after said seed Cu sputtering step, and executing heat
treatment; a Cu depositing step of depositing Cu which makes an
interconnection on said seed Cu after said hole reduction impurity
fabricating step(A); and thereby making said hole reduction
impurities precipitate in said vicinity of said first
interface.
77. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 76, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
solid solution of said hole reduction impurities with said Cu in
said vicinity of said first interface.
78. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 76, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, making said
hole reduction impurities a Cu amorphous in said vicinity of said
first interface.
79. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 76, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said first interface, fabricating a
Cu compound with said Cu in said vicinity of said first
interface.
80. A method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on the lower interconnection
layer to be different from said one layer, and a via hole for
interconnecting said lower and upper wring layers, at least one or
more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in a
manufacturing process of said copper interconnection, said process
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a Cu interconnection fabricating step of embedding
a Cu or Cu alloy layer in said interconnection groove after said
seed Cu sputtering step, and fabricating an interconnection by
using CMP method; a hole reduction impurity fabricating step(C) of
ion-implanting hole reduction impurities in order to reduce holes
fabricated in a second interface between said Cu or Cu alloy layer
and an insulating cap layer fabricated on said Cu or Cu alloy layer
to insulate and protect said Cu or Cu alloy layer after said Cu
interconnection fabricating step, and executing heat treatment; a
natural oxide layer removing step of removing a natural oxide layer
of said Cu by executing treatment such as cleaning and/or plasma
irradiation on a surface of said interconnection after said second
hole reduction impurity fabricating step; an insulating cap layer
sputtering deposition step of depositing said insulating cap layer
by sputtering after said natural oxide layer removing step; and
thereby making said hole reduction impurities precipitate in said
vicinity of said first interface.
81. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 80, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said second interface, fabricating
a solid solution of said hole reduction impurities with said Cu in
said vicinity of said second interface.
82. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 80, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said second interface, making said
hole reduction impurities a Cu amorphous in said vicinity of said
second interface.
83. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 80, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said second interface, fabricating
a Cu compound with said Cu in said vicinity of said second
interface.
84. A method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on the lower interconnection
layer to be different from said one layer, and a via hole for
interconnecting said lower and upper wring layers, at least one or
more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in a
manufacturing process of said copper interconnection, said process
comprising: a barrier metal sputtering step of sputtering barrier
metal on an interconnection groove; a seed Cu sputtering step of
sputtering seed Cu which becomes a seed after said barrier metal
sputtering step; a Cu interconnection fabricating step of embedding
a Cu or Cu alloy layer in said interconnection groove after said
seed Cu sputtering step, and fabricating an interconnection by
using CMP method; a hole reduction impurity fabricating step(D) of
depositing hole reduction impurities by a solid phase in order to
reduce holes fabricated in a second interface between said Cu or Cu
alloy layer and an insulating cap layer fabricated on said Cu or Cu
alloy layer to insulate and protect said Cu or Cu alloy layer after
said Cu interconnection fabricating step, and executing heat
treatment; a natural oxide layer removing step of removing a
natural oxide layer of said Cu by executing treatment such as
cleaning and/or plasma irradiation on a surface of said
interconnection after said second hole reduction impurity
fabricating step; an insulating cap layer sputtering deposition
step of depositing said insulating cap layer by sputtering after
said natural oxide layer removing step; and, thereby making said
hole reduction impurities precipitate in said vicinity of said
second interface.
85. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 84, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said second interface, fabricating
a solid solution of said hole reduction impurities with said Cu in
said vicinity of said second interface.
86. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 84, wherein in place of making said hole reduction impurities
precipitate in said vicinity of said second interface, fabricating
a Cu compound with said Cu in said vicinity of said second
interface.
87. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 80, wherein said natural oxide layer removing step is
executed after said Cu interconnection fabricating step, and then
said second hole reduction impurity fabricating step is
executed.
88. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 84, wherein said natural oxide layer removing step is
executed after said Cu interconnection fabricating step, and then
said third hole reduction impurity fabricating step is
executed.
89. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers, at
least one or more of said lower interconnection layer, said upper
interconnection layer, and said via hole being fabricated in said
manufacturing process of said copper interconnection, according to
claim 69, wherein the hole reduction impurities are one selected
from Nb, Ta, Si, Ru, and V.
90. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 69, wherein said multi-layers interconnection
structure is a single damascene.
91. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 70, wherein said multi-layers interconnection
structure is a single damascene.
92. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 71, wherein said multi-layers interconnection
structure is a single damascene.
93. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 72, wherein said multi-layers interconnection
structure is a single damascene.
94. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 73, wherein said multi-layers interconnection
structure is a single damascene.
95. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 74, wherein said multi-layers interconnection
structure is a single damascene.
96. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 75, wherein said multi-layers interconnection
structure is a single damascene.
97. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 76, wherein said multi-layers interconnection
structure is a single damascene.
98. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 77, wherein said multi-layers interconnection
structure is a single damascene.
99. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 78, wherein said multi-layers interconnection
structure is a single damascene.
100. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 79, wherein said multi-layers interconnection
structure is a single damascene.
101. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 80, wherein said multi-layers interconnection
structure is a single damascene.
102. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 81, wherein said multi-layers interconnection
structure is a single damascene.
103. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 82, wherein said multi-layers interconnection
structure is a single damascene.
104. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 83, wherein said multi-layers interconnection
structure is a single damascene.
105. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 84, wherein said multi-layers interconnection
structure is a single damascene.
106. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 85, wherein said multi-layers interconnection
structure is a single damascene.
107. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 86, wherein said multi-layers interconnection
structure is a single damascene.
108. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 69, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
109. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 70, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
110. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 71, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
111. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 72, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
112. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 73, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
113. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 74, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
114. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 75, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
115. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 76, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
116. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 77, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
117. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 78, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
118. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 79, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
119. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 80, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
120. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 81, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
121. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 82, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
122. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 83, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
123. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 84, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
124. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 85, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
125. The method for manufacturing a copper interconnection with
multi-layers having a lower interconnection layer of one layer, an
upper interconnection layer positioned on said lower
interconnection layer to be different from said one layer, and a
via hole for interconnecting said lower and upper wring layers,
according to claim 86, wherein said multi-layer interconnection
structure is a dual damascene, and said dual damascene is
fabricated in at least one of a via first process for fabricating
said interconnection groove after opening of said via, a trench
first process for opening said via after fabrication of said
interconnection groove.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a copper interconnection
structure and its fabrication method and, more particularly, to a
copper interconnection structure of a increasing Cu interconnection
lifetime, and its fabrication method.
[0003] 2. Description of the Prior Art
[0004] It is well known that in recent years efforts have been made
to achieve high performance and functionality of a semiconductor
integrated circuit used for an information electronic equipment
such as a cell phone. Such a semiconductor integrated circuit has
many circuit elements, for example transistors. It is also a
well-known fact that such a semiconductor integrated circuit is
fabricated by using a high-precision semiconductor fabrication
process. Further, in the high-precision semiconductor fabrication
process, an interconnection structure of an increased
interconnection lifetime, especially a copper interconnection
structure attracts attention.
[0005] FIGS. 1A to 1D are sectional views of a copper
interconnection illustrating a conventional copper interconnection
fabrication process. Referring to FIGS. 1A to 1D, the conventional
copper interconnection structure is provided with a barrier metal
(Ta) layer 12 made of mainly high melting point metal such as Ta on
an insulating layer 11, a thin seed Cu layer 14 fabricated by
sputtering a Cu interconnection layer 16a fabricated using a method
such as electro plating to thickly deposit Cu, and an SiN layer 17
fabricated by using sputtering to deposit SiN or the like.
[0006] Next, a conventional copper interconnection fabrication
method will be described by referring to the sectional views of
FIGS. 1A to 1D again.
[0007] First, according to the conventional copper interconnection
fabrication process, as shown in FIG. 1A, a Cu interconnection
groove 10 is fabricated on the insulating layer 11, then the
barrier metal (Ta) layer 12 mainly made of high melting point metal
such as Ta is fabricated thin by sputtering and, further as shown
in FIG. 1B, seed Cu is thinly sputtered to fabricate the seed Cu
layer 14. Subsequently, Cu is thickly deposited by a method such as
electro-plating to fabricate the Cu layer 16. This is subjected to
heat treatment at about 400.degree. C. for 10 min. to several hours
according to an interconnection thickness and/or an interconnection
width to grow Cu grains, and uniformly fill the groove.
Subsequently, as shown in FIG. 1C, the layer is made flat by the
chemical mechanical polishing (CMP) method or the like to fabricate
an interconnection 16a. A surface of the interconnection 16a is
treated such as cleaning and/or plasma irradiation to remove a Cu
natural oxide layer and, then, as shown in FIG. 1D, an insulating
film, such as SiN or the like, is deposited by sputtering to
fabricate the SiN layer 17.
[0008] As an example of an electromigration (EM) suppression in an
Al interconnection, there is an example of adding a small amount of
impurities such as Cu to Al as described in Japanese Patent
Application Laid-Open No. Hei 08 (1996)-107110 (paragraphs 0015 to
0020, FIG. 1).
[0009] Such impurities are added because as described in "Al--Ti
and Al--Ti--Si thin alloy films", Albertus G. Dirks, Tien Tien, and
Janet M. Towner, pp. 2010, "Journal of Applied Physics", vol. 59-6
(1968), impurities are precipitated on a grain boundary to lower a
hole density, whereby contribution of grain boundary diffusion is
reduced. In the Cu interconnection, an EM main diffusion path is
considered to be an interface between Cu and other materials.
Accordingly, interface holes must be selectively removed.
[0010] However, in such a copper interconnection fabrication
method, there are problems that an EM resistance of the copper
interconnection is low, and particularly, in a case of the copper
interconnection width is narrow, the copper interconnection has
shorter lifetime than the Al interconnection. A reason is that in
the case of the Al interconnection, if an interconnection width is
smaller than an average Al grain size, and a gain boundary becomes
a bamboo structure, Al lattice diffusion becomes a main diffusion
mechanism. This lattice diffusion is much slower than either grain
boundary or interface diffusion. Thus, in the case of the narrow
interconnection where grain boundary diffusion is dominant which
achieves a bamboo grain boundary structure, an EM lifetime is
longer than a wide interconnection.
[0011] On the other hand, in the case of the Cu interconnection,
even if an interconnection width is smaller than an average Cu
grain size, and a grain boundary becomes a bamboo structure, not Cu
lattice diffusion but interface diffusion becomes a main diffusion
mechanism. Thus, an increase in the EM lifetime observed in the
case of the thin Al interconnection is not seen in the case of the
Cu interconnection. As a result, in the case of an interconnection
width is small, the Cu interconnection has shorter lifetime than
the Al interconnection.
SUMMARY OF THE INVENTION
[0012] Objects of the present invention are to provide a copper
interconnection structure which eliminates the foregoing drawbacks
of the conventional art, and solves the technical problems to
increase an interconnection lifetime, and its fabrication
method.
[0013] A constitution of a copper interconnection structure of the
present invention is characterized in that in the vicinity of an
interface between Cu and barrier metal or between Cu and a cap
layer, in order to selectively reduce holes existed in an interface
between Cu or a Cu alloy layer and a barrier metal layer, hole
reduction impurities added to Cu form a solid solution, the hole
reduction impurities are precipitated, amorphous Cu is provided or
a compound with Cu is formed, whereby holes in the vicinity of the
interface are reduced, contribution of interface diffusion to Cu EM
is reduced, a lifetime is increased, and simultaneously
adhesiveness and resistance to stress migration are increased.
[0014] A constitution of a copper interconnection fabrication
method of the present invention is characterized in that after
sputtering of barrier metal on an interconnection groove, in order
to reduce holes existed in an interface between Cu or a Cu alloy
layer and a barrier metal layer, hole reduction impurities added to
Cu are ion-implanted in the barrier metal, heat treatment is
executed, seed Cu is sputtered, and then Cu which makes an
interconnection is deposited thereon, the hole reduction impurities
form a solid solution in the vicinity of the interface between Cu
and the barrier metal, the hole reduction impurities are
precipitated, and amorphous Cu is provided or a compound with Cu is
formed.
[0015] Further, a constitution of another copper interconnection
fabrication method of the present invention is characterized in
that Cu or a Cu alloy is embedded in an interconnection groove
fabricated in an interconnection surface, an interconnection is
fabricated by using the CMP method or the like, then impurities are
ion-implanted in order to reduce holes existed in an interface
between Cu or a Cu alloy layer and a barrier metal layer, heat
treatment is executed, a surface of the interconnection is treated
such as cleaning and/or plasma irradiation to remove a Cu natural
oxide layer, and then a cap layer is fabricated by sputtering to
make Cu amorphous in the vicinity of an interface with the cap
layer.
[0016] Furthermore, according to the present invention, in place of
ion-implantation of the hole reduction impurities added to the Cu
executed to selectively reduce the holes existed in the interface
between the Cu or the Cu alloy layer and the barrier metal layer,
and the heat treatment, the impurities can be diffused from thin
layer by heat treatment in place of ion-implantation, and then
diffused by heat. The step of executing the treatment such as
cleaning and/or plasma irradiation on the surface of the
interconnection to remove the Cu natural oxide layer can be
executed after the fabrication of the interconnection, and then the
hole reduction impurities can be ion-implanted. Further, the step
of executing the treatment such as cleaning and/or plasma
irradiation on the surface of the interconnection to remove the Cu
natural oxide layer can be executed after the fabrication of the
interconnection, and then the hole reduction impurities can be
deposited by a very thin layer, and the hole reduction impurities
can be one of Nb, Ta, Si, Ru and V.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIGS. 1A to 1D are sectional views of a copper
interconnection illustrating a conventional copper interconnection
fabrication process.
[0018] FIGS. 2A to 2E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a first embodiment of the present
invention.
[0019] FIGS. 3A to 3E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a second embodiment of the present
invention.
[0020] FIGS. 4A to 4E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a third embodiment of the present
invention.
[0021] FIGS. 5A to 5F are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a fourth embodiment of the present
invention.
[0022] FIGS. 6A to 6F are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a fifth embodiment of the present
invention.
[0023] FIGS. 7A to 7E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a sixth embodiment of the present
invention.
[0024] FIGS. 8A to 8E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to a seventh embodiment of the present
invention.
[0025] FIGS. 9A to 9E are sectional views of a copper
interconnection illustrating a copper interconnection fabrication
process according to an eight embodiment of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] Next, detailed description will be made of a copper
interconnection structure and its fabrication method according to
several embodiments of the present invention with reference to the
accompanying drawings.
[0027] FIGS. 2A to 2E are sectional views showing a process of a
fabrication method according to a first embodiment of the present
invention. First, in the fabrication method of the first embodiment
of the invention, as shown in FIG. 2A, after a Cu interconnection
groove 10 is fabricated on an insulating layer 11, a barrier metal
(Ta) layer 12 mainly made of high melting point metal such as Ta is
fabricated thereon by sputtering. Subsequently, as shown in FIG.
2B, impurities 13a such as Nb are injected by injection energy of 2
keV to 5 keV, and a dose amount of 1.0E14 cm.sup.-2, and subjected
to annealing at about 900.degree. C. for several min. Accordingly,
the impurity Nb becomes a solid solution on the surface to
fabricate an impurity part (Nb) 15.
[0028] Then, as shown in FIG. 2C, seed Cu is thinly sputtered to
fabricate a seed Cu layer 14, and Cu is thickly deposited
subsequently by a method such as electro-plating to fabricate a Cu
layer 16. The Cu layer 16 is subjected to heat treatment at about
400.degree. C. for about 10 min. to several hours in accordance
with an interconnection thickness and/or an interconnection width
to grow Cu grains, and uniformly fill the groove. Subsequently, by
using CMP method or the like, the layer is made flat to fabricate
an interconnection 16a as shown in FIG. 2D. A surface of the
interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, as shown
in FIG. 2E, SiN or the like is sputtered to fabricate an insulating
layer 17.
[0029] Thus, an interconnection structure is obtained, where the
impurity Nb 13 becomes a solid solution in the vicinity of an
interface between the seed Cu layer 14 and the Ta barrier metal
layer 12 of the interconnection layer.
[0030] On the other hand, an interconnection structure can be
obtained, where an impurity Si in place of the impurity Nb 13 is
precipitated in the vicinity of the interface between the seed Cu
layer 14 and the Ta barrier metal layer 12 of the interconnection
layer. First, as in the case of the fabrication process of the
interconnection structure where the impurity Nb 13 becomes a solid
solution in the vicinity of the interface between the seed Cu layer
14 and the Ta barrier metal layer 12 of the interconnection layer,
a barrier metal (Ta) layer 12 is fabricated by sputtering as shown
in FIG. 2A.
[0031] Subsequently, as shown in FIG. 2B, impurities such as Si are
injected by injection energy of 5 keV to 10 keV, and a dose amount
of 2.0E14 cm.sup.-2 to 5.0E14 cm.sup.-2, and subjected to annealing
at about 850.degree. C. for several min. Accordingly, the impurity
Si is precipitated on a very surface of Ta to fabricate an impurity
(Si) part 15a.
[0032] The process thereafter is similar to the fabrication process
of the interconnection structure where the impurity Nb 13 becomes a
solid solution in the vicinity of the interface between the seed Cu
layer 14 and the Ta barrier metal layer 12 of the interconnection
layer, that is, the steps from FIGS. 2C to 2E are sequentially
executed.
[0033] The embodiment has been described by way of example where
the interconnection groove 10 is fabricated on the insulating layer
11. Apparently, however, the interconnection groove 10 can be
fabricated on a semiconductor layer, another interconnection layer
and/or a combination thereof.
[0034] FIGS. 3A to 3E are sectional views showing a process of a
fabrication method according to a second embodiment of the present
invention. First, in the fabrication method of the second
embodiment of the invention, as shown in FIG. 3A, after a Cu
interconnection groove 10 is fabricated on an insulating layer 11,
a barrier metal (Ta) layer 12 mainly made of high melting point
metal such as Ta, and a seed Cu layer 14 made of seed Cu are
fabricated thin by sputtering. Subsequently, as shown in FIG. 3B,
impurities 13a such as Ta are injected by injection energy of 5.0
keV, and a dose amount of 1.0E15 cm.sup.-2, and subjected to
annealing at about 900.degree. C. for several min. Accordingly, Cu
becomes amorphous in the vicinity of an interface between the seed
Cu and the barrier Ta to from an amorphous Cu layer 14a.
Subsequently, as shown in FIG. 3C, Cu is thickly deposited by a
method such as electro-plating to fabricate a Cu layer 16. The Cu
layer 16 is subjected to heat treatment at about 400.degree. C. for
about 10 min. to several hours in accordance with an
interconnection thickness and/or an interconnection width to grow
Cu grains, and uniformly fill the interconnection groove.
[0035] Subsequently, by using CMP method or the like, an
interconnection 16a is fabricated as shown in FIG. 3D. A surface of
the interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, as shown
in FIG. 3E, SiN or the like is sputtered to fabricate an insulating
layer 17. Thus, an interconnection structure is obtained, where
there is an amorphous Cu layer 14a in an interface between the seed
Cu layer 14 and the Ta layer 12.
[0036] FIGS. 4A to 4E are sectional views showing a process of a
fabrication method according to a third embodiment of the present
invention. First, in the fabrication method of the third embodiment
of the invention, as shown in FIG. 4A, after a Cu interconnection
groove 10 is fabricated on an insulating layer 11, a barrier metal
layer 12 mainly made of high melting point metal such as Ta, and a
seed Cu layer 14 made of seed Cu are fabricated thin by sputtering.
Subsequently, as shown in FIG. 4B, a solid phase Si layer 18
containing impurities such as Si is fabricated by several nm, and
subjected to annealing at about 900.degree. C. for several min., to
fabricate a Cu--Si compound layer 18a in an interface between the
seed Cu layer 14 and the Ta layer 12. As shown in FIG. 4C, Cu is
thickly deposited by a method such as electro-plating to fabricate
a Cu layer 16. The Cu layer 16 is subjected to heat treatment at
about 400.degree. C. for about 10 min. to several hours in
accordance with an interconnection thickness and/or an
interconnection width to grow Cu grains, and uniformly fill the
groove 10.
[0037] Subsequently, by using CMP method or the like, an
interconnection 18a is fabricated as shown in FIG. 4D. A surface of
the interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, as shown
in FIG. 4E, SiN or the like is deposited by sputtering to fabricate
an insulating layer 17. Thus, an interconnection structure is
obtained, where there is a Cu--Si compound layer. 18a in an
interface between the seed Cu layer 14 and the barrier metal Ta
layer 12.
[0038] FIGS. 5A to 5F are sectional views showing a process of a
fabrication method according to a fourth embodiment of the present
invention. First, in the fabrication method of the fourth
embodiment of the invention, as shown in FIG. 5A, after a Cu
interconnection groove 10 is fabricated on an insulating layer 11,
a barrier metal layer 12 mainly made of high melting point metal
such as Ta, and a seed Cu layer 14 made of seed Cu are fabricated
thin by sputtering. Subsequently, Cu is thickly deposited by a
method such as electro-plating to fabricate a Cu layer 16. This
layer is subjected to heat treatment at about 400.degree. C. for
about 10 min. to several hours in accordance with an
interconnection thickness and/or an interconnection width to grow
Cu grains, and uniformly fill the groove.
[0039] Subsequently, by using CMP method or the like, an
interconnection 16a is fabricated as shown in FIG. 5B. In the
drawing, a CuOx natural oxide film 20 is shown on the Cu layer 16.
Here, as shown in FIG. 5C, impurities 21 such as V are injected by
injection energy of 2 keV to 5 keV, and a dose amount of 1.0E14
cm.sup.-2, and subjected to annealing at about 900.degree. C. for
several min. The impurity V becomes a solid solution in the
vicinity of an interface CuOx 20 and the interconnection Cu of the
surface. As shown in FIG. 5E, a surface of the interconnection is
treated such as cleaning and/or plasma irradiation to remove the Cu
natural oxide layer 20 and, then, as shown in FIG. 5F, SiN or the
like is deposited by sputtering. Thus, an interconnection structure
is obtained, where an impurity V layer 21a becomes a solid solution
in an interface between a cap SiN 17 and the Cu layer 16.
[0040] FIGS. 6A to 6F are sectional views showing a process of a
fabrication method according to a fifth embodiment of the present
invention. First, in the fabrication method of the fifth embodiment
of the invention, as shown in FIG. 6A, after a Cu interconnection
groove 10 is fabricated on an insulating layer 11, a barrier metal
layer 12 mainly made of high melting point metal such as Ta, and a
seed Cu layer 14 are fabricated thin by sputtering. Subsequently,
Cu is thickly deposited by a method such as electro-plating to
fabricate a Cu layer 16. This layer is subjected to heat treatment
at about 400.degree. C. for about 10 min. to several hours in
accordance with an interconnection thickness and/or an
interconnection width to grow Cu grains, and uniformly fill the
groove. In the drawing, a CuOx natural oxide film 20 is shown on
the Cu layer 16.
[0041] Subsequently, as shown in FIG. 6B, CMP method or the like is
used to fabricate an interconnection, and a surface of the
interconnection is treated such as cleaning and/or plasma
irradiation to remove the Cu natural oxide layer 20 as shown in
FIG. 6C. As shown in FIG. 6D, impurities such as Si are injected by
injection energy of 5 keV to 10 keV, and a dose amount of 1.0E15
cm.sup.-2, and subjected to annealing at about 900.degree. C. for
several min. An amorphous Cu layer is fabricated in the vicinity of
the surface of the Cu layer. Subsequently, SiN or the like is
deposited by sputtering. Thus, an interconnection structure is
obtained, where there is an amorphous Cu layer 23 in an interface
between a cap SiN 17.and the Cu layer 16.
[0042] Next, description will be made of single and dual damascene
structures, and a fabrication method thereof when the present
invention is applied to the single damascene structure having a
multilayer interconnection including at least one of such
interconnections, for example the above-described interconnection
structure of each layer, or the dual damascene structure having the
above-described interconnection structure over two layers, for
example a via hole and its upper layer interconnection.
[0043] First, the case where the invention is applied to the single
damascene structure is described. FIGS. 7A to 7E are sectional
views showing a fabrication process of a copper interconnection
according to a sixth embodiment of the present invention.
[0044] According to the fabrication method of the multiplayer
interconnection of the sixth embodiment of the invention where the
copper interconnection fabrication method of the embodiment is
applied to the single damascene structure, as shown in FIG. 7A,
after a Cu interconnection groove 10 is fabricated, a barrier metal
layer 12 mainly made of high melting point metal such as Ta is
sputtered. Subsequently, impurities such as Nb 13 are injected by
injection energy of 2 keV to 5 keV, and a dose amount of 1.0E14
cm.sup.-2, and subjected to annealing at about 350.degree. C. for
several min.
[0045] As shown in FIG. 7B, the impurity Nb becomes a solid
solution on a very surface of the Ta layer 12. A seed Cu layer 14
is thinly sputtered, and then a Cu layer 16 is fabricated thick by
a method such as electro-plating. This layer is subjected to heat
treatment at about 250 to 350.degree. C. for 5 min. to several
hours in accordance with an interconnection thickness and/or an
interconnection width to grow Cu grains, and uniformly fill the
groove.
[0046] Subsequently, by using CMP method or the like, an
interconnection 16a is fabricated as shown in FIG. 7C. A surface of
the interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, an SiC
layer 17 or the like is fabricated by sputtering. Thus, an
interconnection structure is obtained, where an impurity Nb 15
becomes a solid solution in an interface between the seed Cu layer
14 and the Ta layer 12, and this interconnection is set as a lower
layer interconnection.
[0047] Then, a low dielectric constant film 11a as an interlayer
insulating film, and an SiCN layer 17a are fabricated thin. A via
hole 71 is fabricated by a normal etching method, and treated such
as ashing and/or cleaning. For this via hole 71, as in the case of
the interconnection groove, sputtering of a barrier metal layer 12a
of Ta or the like, injection of impurities 15a such as Nb and
annealing, and sputtering of a seed Cu layer 14b, and
electro-plating and annealing of a Cu layer 16a are executed.
[0048] Subsequently, CMP is executed to fabricate a via hole
constituted of the barrier metal layer 12a of Ta or the like, the
seed Cu layer 14b, the impurities 15a such as Nb, and the Cu layer
16. Then, as shown in FIG. 7D, an interlayer insulating film 11a is
fabricated, and an upper layer interconnection is fabricated by a
method similar to that of the lower layer interconnection and,
accordingly as shown in FIG. 7E, a multilayer interconnection of a
single damascene structure is fabricated.
[0049] The embodiment shows the structure where the impurity
becomes a solid solution in the interface between the seed Cu layer
and the Ta layer in all of the lower layer interconnection, the via
hole, and the upper layer interconnection. However, a structure can
also be fabricated, where the invention is applied to one of the
lower layer interconnection, the via hole and the upper layer
interconnection. Moreover, the number of interconnection layers is
not limited to two, and the invention can be applied to a case of
much more layers. The embodiment shows the case of the via hole
made of Cu. However, other materials such as W may be used.
[0050] Next, description is made of a case of applying the copper
interconnection fabrication method of the embodiment of the
invention to a via first structure in a dual damascene structure.
FIG. 8A to 8E are sectional views showing a copper interconnection
fabrication process according to a seventh embodiment of the
present invention.
[0051] According to the fabrication method of the multiplayer
interconnection of the seventh embodiment of the invention where
the copper interconnection fabrication method of the embodiment is
applied to a via first structure in a dual damascene structure, as
shown in FIG. 8A, after a Cu interconnection groove, is fabricated,
a barrier metal layer 12 mainly made of high melting point metal
such as Ta, and a seed Cu layer 14 are thinly sputtered.
Subsequently, impurities such as Ta are injected by injection
energy of 5 keV, and a dose amount of 1.0E15 cm.sup.-2, and
subjected to annealing at about 400.degree. C. for several min. As
shown in FIG. 8B, Cu in the vicinity of an interface between the
seed layer Cu 14 and the Ta barrier metal layer 12 become
amorphous.
[0052] Subsequently, a Cu layer 16a is fabricated thick by a method
such as electro-plating. This layer is subjected to heat treatment
at about 380.degree. C. for 10 min. to several hours in accordance
with an interconnection thickness and/or an interconnection width
to grow Cu grains, and uniformly fill the groove. Subsequently, by
using CMP method or the like, an interconnection is fabricated.
[0053] Further, as shown in FIG. 8C, a surface of the
interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, an SiC
layer 17 or the like is fabricated by sputtering. Thus, an
interconnection structure is obtained, where there is an amorphous
Cu layer 14a in the interface between the seed Cu layer and the Ta
layer, and this interconnection is set as a lower layer
interconnection.
[0054] Further, a low dielectric constant film 11a as an interlayer
insulating film of a via hole part 81, and an SiCN layer 17a or the
like are fabricated. Subsequently, a low dielectric constant film
as an interlayer insulating film of an upper layer interconnection,
and an SiO.sub.2 film 11b are fabricated. Then, an anti-reflection
compound (ARC) film, a photoresist and an etching mask are
fabricated and, by using gas containing fluorocarbon or the like,
the via hole 81 is opened by etching.
[0055] Then, as shown in FIG. 8D, after treatment such as (wet)
cleaning of the opening, a film prevented from a reflection, a
photoresist, and an etching mask are deposited to fabricate an
upper layer interconnection groove 82. As shown in FIG. 8E, after
normal treatment such as wet cleaning and/or cleaning, as in the
case of the lower layer interconnection, sputtering of a barrier
metal layer 12c mainly made of high melting point metal such as Ta,
and a seed Cu layer 14d are executed, impurities such as Ta 13c are
injected by injection energy of 5 keV, and a dose amount of 1.0E15
cm.sup.-2, and subjected to annealing, and Cu in the vicinity of an
interface between the seed Cu layer and the Ta barrier layer
becomes amorphous.
[0056] Subsequently, a Cu layer 16d is fabricated thick by a method
such as electro-plating. This layer is subjected to heat treatment
at about 350.degree. C. for 10 min. to several hours in accordance
with an interconnection thickness and/or an interconnection width
to grow Cu grains, and uniformly fill the groove.
[0057] Subsequently, by using CMP method or the like, an
interconnection is fabricated. A surface of the interconnection is
treated such as cleaning and/or plasma irradiation to remove a Cu
natural oxide layer and, then, an SiN layer 17 or the like is
fabricated by sputtering. Thus, a laminated structure can be
fabricated, where there is an amorphous Cu layer 14f in an
interface between the seed Cu layer and the Ta layer, and this
interconnection is set as a lower layer interconnection.
[0058] The embodiment shows the structure where the amorphous Cu
layer 14f is present in the interface between the seed Cu layer and
the Ta layer in both of the lower layer interconnection/the via
hole and the upper layer interconnection. However, a structure can
also be fabricated, where the invention is applied to one of the
lower layer interconnection/the via hole and the upper layer
interconnection. Moreover, the number of interconnection layers is
not limited to two, and the invention can be applied to a case of
much more layers.
[0059] Next, as a dual damascene fabrication method, in addition to
the method for opening the via hole shown in the copper
interconnection fabrication method of the seventh embodiment of the
invention, and then fabricating the interconnection groove for the
upper layer interconnection (via first), an example of a method for
first fabricating an interconnection groove, and then a via hole
(trench first) will be described as a copper interconnection
fabrication method of an eight embodiment of the present
invention.
[0060] That is, description is made of a case where the invention
is applied to a trench first structure in a dual damascene
structure. FIGS. 9A to 9E are sectional views showing a copper
interconnection fabrication process according to an eighth
embodiment of the present invention.
[0061] According to the fabrication method of the multiplayer
interconnection of the eighth embodiment of the invention where the
copper interconnection fabrication method of the embodiment is
applied to a via first structure in a dual damascene structure, as
shown in FIG. 9A, after a Cu interconnection groove is fabricated,
a barrier metal layer 12 mainly made of high melting point metal
such as Ta, and a seed Cu layer 14 are thinly sputtered.
[0062] Subsequently, a solid phase containing impurities such as Si
(18) are deposited, and subjected to annealing at about 400.degree.
C. for several min., to fabricate a Cu--Si compound 18a in an
interface between the seed layer Cu 14 and the Ta barrier metal
layer 12 as shown in FIG. 9B. Subsequently, a Cu layer 16a is
fabricated thick by a method such as electro-plating. This layer is
subjected to heat treatment at about 350 to 400.degree. C. for 10
min. to several hours in accordance with an interconnection
thickness and/or an interconnection width to grow Cu grains, and
uniformly fill the groove.
[0063] Subsequently, as shown in FIG. 9C, by using CMP method or
the like, an interconnection is fabricated. A surface of the
interconnection is treated such as cleaning and/or plasma
irradiation to remove a Cu natural oxide layer and, then, an SiN
layer 17 or the like is fabricated by sputtering. Thus, an
interconnection structure is obtained, where there is a Cu--Si
compound 18a in the interface between the seed Cu layer and the Ta
layer, and this interconnection is set as a lower layer
interconnection.
[0064] A low dielectric constant film 11c as an interlayer
insulating film of a via hole part, and an SiCN layer 17d or the
like are fabricated. Subsequently, a low dielectric constant film
as an interlayer insulating film of an upper layer interconnection,
and an SiO.sub.2 film 11d are fabricated. Then, a reflection
prevention film, a photoresist and an etching mask are fabricated
and, by using gas containing fluorocarbon or the like, an upper
layer interconnection groove 91 is opened by etching.
[0065] Then, as shown in FIG. 9D, after removal of the etching
mask, a reflection prevention film for via hole opening, a
photoresist, and an etching mask are fabricated, and etched to
fabricate a via hole 92.
[0066] After normal treatment such as wet cleaning and/or cleaning,
as in the case of the lower layer interconnection, sputtering of a
barrier metal layer 12d mainly made of high melting point metal
such as Ta, and a seed Cu layer 14g are executed, impurities such
as Ta 12d are injected (injection energy of 5 keV, and a dose
amount of 1.0E15 cm.sup.-2), and subjected to annealing, and Cu
18b, 18c in the vicinity of an interface between the seed Cu layer
and the Ta barrier layer becomes amorphous.
[0067] Subsequently, as shown in FIG. 9E, a Cu layer 16e is
fabricated thick by a method such as electro-plating. This layer is
subjected to heat treatment at about 380.degree. C. for 10 min. to
several hours in accordance with an interconnection thickness
and/or an interconnection width to grow Cu grains, and uniformly
fill the groove. Subsequently, by using CMP method or the like, an
interconnection is fabricated. A surface of the interconnection is
treated such as cleaning and/or plasma irradiation to remove a Cu
natural oxide layer and, then, an SiN layer 17f or the like is
fabricated by sputtering. Thus, an interconnection structure can be
fabricated, where there is a seed Cu layer 14g in an interface
between the seed Cu layer and the Ta layer, and this
interconnection is set as an upper layer interconnection.
[0068] The embodiment shows the interconnection structure where the
amorphous Cu layer is present in the interface between the seed Cu
layer and the Ta layer in the lower layer interconnection, and the
Cu--Si compound is present, in the interface between the seed Cu
layer and the Ta layer in the via hole and the upper layer
interconnection. However, application can be made to various
combinations, e.g., a case where structures are similar between the
lower layer interconnection/the via hole and the upper layer
interconnection, a case where in one of the structures, one of the
copper interconnection fabrication methods of the first to fifth
embodiments of the invention is employed, and other cases.
Moreover, the number of interconnection layers is not limited to
two, and the invention can be applied to a case of much more
layers.
[0069] In the diffusion mechanism of the EM, there are lattice
diffusion, grain boundary diffusion, interface diffusion, and the
like depending on a main diffusion path. It is known that the
diffusion is carried out via holes in many cases. In such a case,
hole generation occurs at a first stage, holes are exchanged
(accordingly material movement) at a second stage, and it is said
that substantially equal amounts of activation energy are needed
for both. Thus, in both grain boundary diffusion and interface
diffusion executed through a grain boundary or an interface where
there are many holes, activation energy is lower than lattice
diffusion becase of lack of hole-generation activation energy to
make diffusion faster.
[0070] For an EM suppression in the Al interconnection, as
described in Patent Document 1, there is an example of adding a
small amount of impurities such as Cu to Al. This is employed
because as described in Nonpatent Document 1, impurities are
deposited in an Al grain boundary to lower a hole density, whereby
contribution of grain boundary diffusion is reduced. In the Cu
interconnection, an dominant EM diffusion path is considered to be
an interface with other materials. Thus, interface holes may be
selectively removed.
[0071] As impurities to be added to Cu, many are possible. In
addition to those deposited in the interface, as,an example, Nb or
Ta which fully fabricates a solid solution with Cu is suitable. For
example, in the Cu and Nb system, a Cu--Nb compound is continuously
present in an interface between Cu and Nb to greatly reduce holes.
Compared with the case where impurities are deposited, this example
is also advantageous in that there no resistance increases by
impurities. V belonging to the same group as Nb may also be
suitable.
[0072] Recently, a Cu--Si compound has been considered to
contribute to an EM improvement. Thus, a method of implanting Si
ions by good controllability, or the like is also preferable. In
addition, Ru which causes an oxide to exhibit good conductivity is
also preferable from the standpoint of removing CuOx from the
interface and maintaining conductivity as RuOx.
[0073] Further, from the standpoint of making an interface
structure continuous, it may be effective to make Cu amorphous to
remove holes. Accordingly, ion implantation conditions of
impurities may be conditions for making the vicinity of a very
surface of Cu amorphous. An advantage accompanying the amorphous
vicinity of the Cu interface is an improvement in physical
properties such as adhesiveness and mechanical strength made by
elimination of stress imbalance or local concentration to a
passivation film such as a cap layer caused by a difference in
growth rate according to criystal orientation during Cu crystal
growth which occurs even at a room temperature. Moreover, the Cu
amorphous treatment executed before the above-described CuSix
treatment provides many effects such as uniform generation of
CuSix.
[0074] As apparent from the foregoing, the present invention is
effective in that when an interconnection width is narrower than an
average Cu grain size, and a grain boundary becomes a bamboo
structure, a bamboo effect for increasing a lifetime appears, and
thus a lifetime is increased by about two digits compared with the
Al interconnection.
[0075] A reason is that if there are impurities deposited in a gap
in the vicinity of the interface between Cu and barrier metal (or
cap), or if there is amorphous Cu in the interface between Cu and
barrier metal (or cap), the number of holes, many being present in
the interface between normal different materials, is reduced, and
thus interface diffusion occurring through the holes can be
suppressed. Accordingly, as Cu diffusion path by the EM, interface
contribution is reduced, whereby a main Cu diffusion mechanism
becomes lattice diffusion.
[0076] The impurities are not only precipitated in the interface,
but may fabricate a compound in the interface. For example, it is
known that Ta, Nb or the like fully fabricates a solid solution
with Cu. Presence of such a compound may reduce holes in the
interface to increase an EM lifetime. There is a report that
silicide treatment of the Cu surface increases an EM lifetime, and
its combination with the present invention can expectedly increase
the lifetime more.
[0077] Use in the multilayer interconnection provides large
resistance to stress migration caused by heat treatment executed
for fabrication of each layer. In the single damascene structure,
selection of a material of a melting point higher than that of Cu
for a via hole enables fabrication of an interconnection structure
of high interconnection reliability. In the dual damascene
structure, since via adhesiveness can be enhanced, contribution can
be made to a reduction in an initial failure rate, and Cu
aggregation in the via which is one of failure modes can be
suppressed.
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