U.S. patent application number 10/023723 was filed with the patent office on 2003-06-26 for semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses.
Invention is credited to Chandran, Biju, Gonzalez, Carlos A..
Application Number | 20030116860 10/023723 |
Document ID | / |
Family ID | 21816824 |
Filed Date | 2003-06-26 |
United States Patent
Application |
20030116860 |
Kind Code |
A1 |
Chandran, Biju ; et
al. |
June 26, 2003 |
Semiconductor package with low resistance package-to-die
interconnect scheme for reduced die stresses
Abstract
A low resistance package-to-die interconnect scheme for reduced
die stresses includes a relatively low melting temperature and
yield strength solder on the die and a relatively higher melting
temperature and electrically conductive material such as copper on
the substrate. A soldered joint connects the solder to the
electrically conductive material to couple/connect the die and
substrate to one another. The soldered joint is formed by heating
the die and solder thereon to at least the melting temperature of
the solder and thereafter contacting the molten solder with the
conductive material on the substrate, which is at a substantially
lower temperature for minimizing residual stress from soldering due
to coefficient of thermal expansion mismatch between the substrate
and die.
Inventors: |
Chandran, Biju; (Chandler,
AZ) ; Gonzalez, Carlos A.; (Chandler, AZ) |
Correspondence
Address: |
ANTONELLI TERRY STOUT AND KRAUS
SUITE 1800
1300 NORTH SEVENTEENTH STREET
ARLINGTON
VA
22209
|
Family ID: |
21816824 |
Appl. No.: |
10/023723 |
Filed: |
December 21, 2001 |
Current U.S.
Class: |
257/778 ;
257/737; 257/779; 257/E21.511; 438/108; 438/612; 438/613 |
Current CPC
Class: |
H05K 2201/10992
20130101; H05K 2201/10674 20130101; H01L 2924/15787 20130101; H01L
2924/01005 20130101; H01L 2924/01006 20130101; H01L 2924/0105
20130101; H01L 2924/014 20130101; H01L 24/81 20130101; Y02P 70/613
20151101; H05K 3/3436 20130101; H01L 2224/13111 20130101; Y02P
70/50 20151101; H01L 2224/81801 20130101; H01L 2924/01322 20130101;
H01L 2924/01029 20130101; H01L 2924/01082 20130101; H01L 2224/13147
20130101; H01L 2224/16 20130101; H01L 2924/01047 20130101; H01L
2924/15787 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/778 ;
257/737; 257/779; 438/108; 438/612; 438/613 |
International
Class: |
H01L 023/48 |
Claims
We claim:
1. An electronic assembly comprising: a substrate; a die; a
plurality of interconnections between the substrate and die;
wherein respective ones of the interconnections include a
relatively low melting temperature and yield strength solder on the
die, a relatively higher melting temperature and electrically
conductive material on the substrate, and a soldered joint
connecting the solder to the electrically conductive material.
2. The electronic assembly according to claim 1, wherein the
relatively higher melting temperature and electrically conductive
material on the substrate is formed as a standoff extending above a
surface of the substrate.
3. The electronic assembly according to claim 2, wherein the top
surface of the standoff is wetted by the solder to form the
soldered joint.
4. The electronic assembly according to claim 2, wherein the
standoff is a bump in the form of a column or stud.
5. The electronic assembly according to claim 1, wherein the
relatively higher melting temperature and electrically conductive
material is copper.
6. The electronic assembly according to claim 1, wherein the
relatively higher melting temperature and electrically conductive
material is solder having a melting temperature higher than the
melting temperature of the solder on the die.
7. The electronic assembly according to claim 1, wherein the die
has an inter layer dielectric material under the
interconnections.
8. The electronic assembly according to claim 7, wherein the inter
layer dielectric material has cohesive and adhesive strengths at
least about an order of magnitude less than those of carbon doped
oxide inter layer dielectric material.
9. The electronic assembly according to claim 1, wherein the
coefficient of thermal expansion of the substrate is at least 15
ppm/.degree. C. and the coefficient of thermal expansion of the die
is at least 2.7 ppm/.degree. C. less than that of the
substrate.
10. The electronic assembly according to claim 1, wherein the
coefficient of thermal expansion of the substrate is more than two
times greater than the coefficient of thermal expansion of the
die.
11. A semiconductor package comprising: a package substrate having
a coefficient of thermal expansion of at least 15 ppm/.degree. C.,
the package substrate having a plurality of relatively high melting
temperature and electrically conductive contact members on the
substrate; a die having a coefficient of thermal expansion which is
at least 2.7 ppm/.degree. C. less than that of the substrate, a
front side of the die having a plurality of relatively lower yield
strength solder connections thereon, the die being located on the
substrate with the solder connections connected to the respective
ones of the contact members by soldered joints electrically
coupling the die to the substrate.
12. The semiconductor package according to claim 11, wherein the
coefficient of thermal expansion of the substrate is more than
twice that of the die.
13. The semiconductor package according to claim 12, wherein the
contact members comprise a plurality of standoff elements
upstanding from a surface of the substrate, and wherein the
soldered joints connect the semiconductor chip to the tops of
respective ones of the standoff elements.
14. The semiconductor package according to claim 13, wherein the
standoff elements are non-melting at the solder liquidous
temperature.
15. The semiconductor package according to claim 13, wherein the
standoff elements are copper bumps.
16. The semiconductor package according to claim 13, wherein the
soldered joints each comprise solder on the die which is wetted
onto a surface of a contact member of the substrate to form the
soldered joint.
17. The semiconductor package according to claim 11, wherein the
die has an inter layer dielectric material under the solder
connections thereon.
18. The semiconductor package according to claim 17, wherein the
inter layer dielectric material has cohesive and adhesive strengths
at least about on an order of magnitude less than those of carbon
doped oxide inter layer dielectric material.
19. A method of interconnecting a die and substrate to one another
for reduced die stresses, the method comprising: providing a
relatively low melting temperature and yield strength solder on a
die and a relatively higher melting temperature and electrically
conductive material contact member on a substrate; and forming a
soldered joint connecting the solder to the electrically conductive
material.
20. The method according to claim 19, wherein the contact member is
formed as a standoff extending above a surface of the
substrate.
21. The method according to claim 20, wherein the solder is wetted
on the top surface of the standoff to form the soldered joint.
22. The method according to claim 19, wherein the solder is
provided over an inter layer dielectric material in the die.
23. The method according to claim 22, wherein the inter layer
dielectric material has cohesive and adhesive strengths at least
about an order of magnitude less than those of carbon doped oxide
inter layer dielectric material.
24. The method according to claim 19, wherein the coefficient of
thermal expansion of the substrate is at least 15 ppm/.degree. C.
and the coefficient of thermal expansion of the die is at least 2.7
ppm/.degree. C. less than that of the substrate.
25. The method according to claim 19, wherein the soldering
includes separately heating the die and solder to at least a
soldering temperature and thereafter contacting the solder with the
contact member on the substrate for forming the soldered joint.
26. The method according to claim 25, further comprising separately
heating the substrate to a temperature substantially lower than the
soldering temperature before contacting the solder on the die with
the contact member on the substrate to form the soldered joint.
Description
FIELD
[0001] The invention relates to an improved low resistance
package-to-die interconnect scheme for reduced die stresses, and
particularly to an electronic assembly/semiconductor package
employing the same. A method of interconnecting a die and substrate
according to the invention is also disclosed.
BACKGROUND
[0002] A conventional die to package interconnect architecture is
illustrated in FIGS. 1-3 of the drawings. In the prior art
semiconductor package 1, the interconnect scheme between die 2 and
substrate 3 comprises copper bumps 4 which are electroplated on the
die, and eutectic AgSn solder 5 which is paste printed on the
substrate lands. Soldered joints are formed in the conventional
process by placing the die with copper bumps and the substrate with
contact lands or pads to which solder has been applied in contact
with one another and heating the die and substrate together to a
temperature higher than the solder melting temperature, followed by
cooling the soldered assembly. The solder on the contact pads of
the substrate is reflowed during this joining process to wet the
copper standoffs on the die to form the soldered joints.
[0003] The die in the conventional package comprises thin film,
inter layer dielectric (ILD) layers 6, see FIG. 4, on its front,
lower surface under the copper bumps of the interconnect
architecture. Due to the inherent weakness (cohesive and adhesive
strengths) of the ILD material, stresses on the dielectric layers
during reliability testing of the package can cause gross
delamination of the ILD interfaces. A current focus for addressing
the reliability issue posed by such ILD delamination in the die is
on increasing the ILD material cohesive and adhesive strengths by
modifying its chemistry, and by interface toughening schemes.
[0004] The ILD material that is typically used is carbon doped
oxide. However, other ILD materials being evaluated for possible
use are significantly weaker than the carbon doped oxide ILD
material. Measurements on candidate materials indicate they are in
some cases 10 to 100 times, e.g., at least about an order of
magnitude, weaker than carbon doped oxide. These materials may be
too weak to be accommodated in dies which are to be packaged using
the current package-to-die interconnect architecture. An improved,
low resistance package-to-die interconnect scheme for reducing die
stresses would make it possible to use these significantly weaker
ILD materials in the packaged die.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is a schematic illustration of a current interconnect
scheme.
[0006] FIG. 2 is an enlarged view of a portion of the prior art
interconnect scheme within the box A of FIG. 1.
[0007] FIG. 3 is a schematic view of the die with copper bumps of
the conventional interconnect scheme of FIGS. 1 and 2.
[0008] FIG. 4 is an enlarged view of a portion of the die with
copper bumps within the circle B in FIG. 3, marked with the line
b-b1 for stress plots, and showing thin film ILD layers in the
lower, front surface of the die under a copper bump.
[0009] FIG. 5 is a schematic drawing of the die with ILD layer and
copper bump wherein stresses in the ILD layer when the die is
subjected to a thermal transient are shown in a stress contour plot
along the ILD layer wherein the more darkly shaded region
represents the region of highest stresses.
[0010] FIG. 6 shows plots of peeling stress in the ILD layer as a
function of distance along the die bump for a copper bump of the
prior art interconnect scheme and for two solder die bumps
according to the present invention, when heated to the same
temperature.
[0011] FIG. 7 is a comparison of normalized ILD peeling stress for
the interconnect scheme of the present invention wherein a copper
bump is provided on the substrate and the prior art interconnect
scheme of FIGS. 1-3 where the copper bump is on the die.
[0012] FIG. 8 is a schematic illustration of an interconnect
scheme/electronic assembly/semiconductor package of an example
embodiment of the present invention.
[0013] FIG. 9 is an enlarged view of a portion of the interconnect
scheme of FIG. 8 shown within the box C.
[0014] FIG. 10 is a schematic illustration of the die and substrate
for making the interconnect scheme of FIGS. 8 and 9, shown before
contacting the solder bump on the die with the copper contact
member/bump on the substrate for soldering.
DETAILED DESCRIPTION
[0015] An example embodiment of a package 7 with a package-die
interconnect scheme according to the present invention is depicted
in FIGS. 8-10. The package utilizes copper bumps 8 on a substrate 9
and solder bumps 10 on a die 11. In the example embodiment, the
lower yield strength solder material, a AgSn solder in the example,
acts as the die bump. The solder is electroplated on the die to
form the die bumps 10. The copper bumps 8 on the substrate may be
copper columns or studs, as needed. They are electroplated on the
substrate lands or pads to provide standoffs, and to lower the
resistance of the interconnect. If copper columns are not needed
for performance, a solder with a melting temperature higher than
the melting temperature of the solder on the die could be
electroplated on the substrate for stand-off.
[0016] The present invention addresses the problem of ILD
delamination under the die bumps during temperature cycling of the
package by lowering the yield strength of the die bump material in
relation to the copper or other conductive material of the contact
member/stand-off on the substrate. This change has been found to
help ILD integrity. Lowering the yield strength of the die bump
material reduces the stresses transferred to the die
(simplistically, the bump deforms in-elastically absorbing energy).
More specifically, crystal structure correlations, and measurements
indicate that the yield strength of the electroplated copper used
for the die bumps in the conventional interconnect scheme of FIGS.
1-3, is in the 350-450 MPa range, making the bump extremely stiff.
During temperature excursions (before and after die-attach), this
stiff bump induces a significant amount of normal stresses on the
dielectric layers in the die. These stresses cause gross
delamination of the ILD interfaces during reliability testing.
Modeling indicates that the biggest single contributor effecting
ILD stresses on the die is the yield strength of the die bump. In
many packages, performance requirements necessitate the use of
electrically conductive standoffs/copper bumps in the interconnect
stack-up. The present invention provides a method to incorporate
the copper bumps in the interconnect stack-up, while significantly
reducing the stresses in the ILD material.
[0017] Lowering the yield strength of the die bump material in
accordance with the present invention has been shown by modeling to
reduce the stresses transferred to the die. This benefit of the
invention is also borne out by reliability test results comparing
ILD cracking with Cu die bumps and high lead solder die bumps
according to the invention. Putting the material that melts during
chip-join on the die, enables the use of a modified
"instant-chip-join" like die-attach process according to the
invention to significantly reduce coefficient of thermal expansion
mismatch induced stresses (and die warpage) from soldering. In this
process, the die with solder die bumps is heated to a temperature
above the melting temperature of the solder of the die bumps, apart
from the substrate. The substrate is preferably heated only to a
substantially lower temperature and the two components are then
joined for soldering the die to the substrate. The differential
heating of the die and substrate exploits the principle that if
elongation of the adherents, the die and substrate, at the
temperature the solder solidifies, are the same, then, the
coefficient of thermal expansion (CTE) mismatch induced stresses
between the die and substrate from soldering can be minimized.
[0018] The modeling or simulation results comparing the
interconnect scheme of the present invention with the conventional
interconnect scheme of FIGS. 1-3 are illustrated in the drawings.
That is, FIGS. 3 and 4 show details of a copper bump on the die of
the conventional interconnect scheme of FIGS. 1 and 2, and the thin
film ILD region under the bump. During heating and cooling the bare
die, the CTE mismatch between the materials in the die cause
stresses and strains in the thin film ILD layers in the die as
shown in FIG. 5. In FIG. 5, the ILD layer represents a stress
contour plot showing that the region 12 of highest stresses is at
the edge of the copper bump, when the die is subjected to a thermal
transient. The area under consideration is represented by the line
B-B1 on the ILD layer in FIG. 4.
[0019] FIG. 6 compares the modeled stresses in the ILD layer along
the line B-B1 (marked in FIG. 4), for different die bump materials,
when they are subjected to the same .DELTA.T. Since the bump
materials are electroplated at room temperature, room temperature
is the stress-free state for the die. Heating (and cooling) induces
CTE mismatch stresses on the die thin film layers due to the bump,
as shown in FIG. 6. The peeling stress at the edge of the bump is
markedly lower with the lead tin and silver tin solder materials
used in accordance with the present invention, as compared with the
copper die bump of the conventional interconnect scheme.
[0020] Since ILD delamination is the key failure mode, only the
normal component of stress (peeling stress) is being compared in
FIG. 6. It should be noted that even though the compressive peeling
stress at the die edge (produced during heating the bare die) is in
itself not a big concern, cooling the die reverses the direction of
the stresses. Also, interaction of the package induced stresses
with this copper bump induced stresses during different thermal
loading conditions creates a significant increase in ILD stresses
with the copper bump.
[0021] FIG. 7 compares the maximum ILD peeling stress for two
different die-bump/substrate bump/substrate combinations. For a
case where the copper bump is on the substrate as in the present
invention (the right side column in FIG. 7), as compared with the
conventional interconnect scheme where the copper bump is on the
die (the left side column in FIG. 7), it is noted that the maximum
peeling stress after die-attach in the case of having the copper
bump on the substrate is about half that of the current case where
the copper bump is on the die. This difference is due to the large
yield strength of electroplated copper (400 MPa) as opposed to the
much lower yield strength for the AgSn solder (around 40 MPa at
room temperature). The lower yield strength of the solder die bump
of the present invention will relieve some of the stress (by
undergoing local plastic deformation), without transferring it to
the die ILD layers. The difference will be even more in the case of
temperature cycling, where the cooling cycle will make the residual
stress at the bump edge (shown in FIG. 6) positive, increasing the
stress for the case where the copper bump is on the die. To put the
50% reduction in ILD stresses with the AgSn/Cu/organic material
substrate (OLGA) combination of the invention (in the right side of
FIG. 7) in perspective, the reduction in ILD stresses by going to a
ceramic substrate (Cu/AgSn/ceramic) with 6.5 ppm/.degree. C. CTE is
only about 20%. Note, that even though the substrate in the
conventional package of FIGS. 1-3 and the substrate in the package
of the present invention illustrated in FIGS. 8-10 is a low cost
organic substrate, this method can be applied to other common
substrate materials like ceramic. However, the plastic and organic
substrate materials have relatively high CTEs, along the order of
17 ppm/.degree. C. The relatively larger CTE mismatch in packages
using the higher CTE package substrate materials, where the silicon
semiconductor chip typically has a CTE of about 2.6-3.3
ppm/.degree. C., can induce higher ILD stresses.
[0022] This concludes the description of the example embodiment.
Although the present invention has been described with reference to
one illustrative embodiment thereof, it should be understood that
numerous other modifications and embodiments can be devised by
those skilled in the art that will fall within the spirit and scope
of the principles of this invention. For example, convention die
attach reflow process was used to demonstrate the ILD stress
reduction using this invention in the example embodiment. Even more
stress reduction can be obtained by combining this invention with a
modified die attach process which makes the thermal expansion of
the chip and the substrate before soldering the same or
substantially the same due to separate heating of each to a
different temperature in relation to their CTEs. More particularly,
reasonable variations and modifications are possible in the
component parts and/or arrangements of the subject combination
arrangement within the scope of the foregoing disclosure, the
drawings and the appended claims without departing from the spirit
of the invention. In addition to variations and modifications in
the component parts and/or arrangements, alternative uses will also
be apparent to those skilled in the art.
* * * * *