U.S. patent application number 10/055940 was filed with the patent office on 2003-06-19 for apparatus for fabricating a semiconductor device and method of doing the same.
Invention is credited to Tokashiki, Ken.
Application Number | 20030114015 10/055940 |
Document ID | / |
Family ID | 14265298 |
Filed Date | 2003-06-19 |
United States Patent
Application |
20030114015 |
Kind Code |
A1 |
Tokashiki, Ken |
June 19, 2003 |
Apparatus for fabricating a semiconductor device and method of
doing the same
Abstract
There is provided a method of fabricating a semiconductor
device, including the steps of (a) generating plasma in the
following conditions: (a1) an RF bias voltage has a frequency equal
to or greater than 1 MHz, (a2) an RF source voltage has a frequency
equal to or greater than 1 MHz, (a3) the RF source voltage is
modulated by pulses in a cycle equal to or greater than 100
.mu.sec, and (a4) pulse-on time is equal to or greater than 50
.mu.sec, and (b) patterning multi-layered metal wirings by etching
through the plasma The method makes it possible to reduce charging
damage to a gate insulating film, even if wirings are further
spaced away from adjacent ones and/or an antenna ratio of
multi-layered metal wirings is further increased.
Inventors: |
Tokashiki, Ken; (Tokyo,
JP) |
Correspondence
Address: |
MCGINN & GIBB, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA
VA
22182-3817
US
|
Family ID: |
14265298 |
Appl. No.: |
10/055940 |
Filed: |
January 28, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10055940 |
Jan 28, 2002 |
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09543734 |
Apr 5, 2000 |
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6372654 |
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Current U.S.
Class: |
438/746 |
Current CPC
Class: |
H01L 21/67069 20130101;
H01J 37/321 20130101; H01L 21/32136 20130101 |
Class at
Publication: |
438/746 |
International
Class: |
H01L 021/302; H01L
021/461 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 7, 1999 |
JP |
11-100112 |
Claims
What is claimed is:
1. A method of fabricating a semiconductor device, comprising the
steps of: (a) generating plasma in the following conditions: (a1)
an RF bias voltage has a frequency equal to or greater than 1 MHz;
(a2) an RF source voltage has a frequency equal to or greater than
1 MHz; (a3) said RF source voltage is modulated by pulses in a
cycle equal to or greater than 100 .mu.sec; and (a4) pulse-on time
is equal to or greater than 50 .mu.sec, and (b) patterning
multi-layered metal wirings by etching through said plasma.
2. The method as set forth in claim 1, wherein said pulses have a
rectangular waveform.
3. The method as set forth in claim 1, wherein said cycle is equal
to or smaller than 500 .mu.sec, and said pulse-on time is equal to
or smaller than 450 .mu.sec.
4. The method as set forth in claim 1, wherein said multi-layered
metal wirings are composed of aluminum or aluminum alloy.
5. The method as set forth in claim 4, wherein said multi-layered
metal wirings make electrical contact with an n-channel MOSFET.
6. The method as set forth in claim 5, wherein said n-channel MOSET
includes a gate insulating film having a thickness equal to or
smaller than 6 nm.
7. The method as set forth in claim 1, wherein said multi-layered
metal wirings have an antenna ratio in the range of 1,000 to
100,000 both inclusive, and wirings in said multi-layered metal
wirings are spaced away from adjacent ones by 0.3 .mu.m or
greater.
8. The method as set forth in claim 7, wherein said multi-layered
metal wirings have an antenna ratio in the range of 1,000 to 40,000
both inclusive.
9. The method as set forth in claim 1, wherein pulse-off time is
equal to or smaller than 100 .mu.sec.
10. The method as set forth in claim 9, wherein said pulse-off time
is equal to or greater than 20 .mu.sec.
11. The method as set forth in claim 10, wherein said pulse-off
time is equal to or greater than 30 .mu.sec.
12. An apparatus for fabricating a semiconductor device,
comprising: (a) a hermetically sealed chamber; (b) a gas introducer
introducing gas into said chamber; (c) a gas exhauster exhausting
gas from said chamber; (d) an RF source voltage supplier applying
an RF source voltage having a frequency equal to or greater than 1
MHz to said chamber to thereby generate inducive coupling plasma
from said gas; (e) an RF bias voltage source applying an RF bias
voltage to a substrate put in said chamber, said RF bias voltage
having a frequency equal to or greater than 1 MHz; and (f) a pulse
generator which transmits pulses to said RF source voltage supplier
to thereby modulate said RF source voltage in a cycle equal to or
greater than 100 .mu.sec with pulse-on time being kept equal to or
greater than 50 .mu.sec.
13. The apparatus as set forth in claim 12, wherein said pulse
generator generates pulses each having a rectangular waveform.
14. The apparatus as set forth in claim 12, wherein said pulse
generator transmits to said RF source voltage supplier to thereby
modulate said RF source voltage in a cycle equal to or smaller than
500 .mu.sec with said pulse-on time being kept equal to or smaller
than 450 .mu.sec.
15. The apparatus as set forth in claim 12, wherein said
semiconductor device includes multi-layered metal wirings composed
of aluminum or aluminum alloy.
16. The apparatus as set forth in claim 15, wherein said
semiconductor device further includes an n-channel MOSFET with
which said multi-layered metal wirings make electrical contact.
17. The apparatus as set forth in claim 16, wherein said n-channel
MOSET includes a gate insulating film having a thickness equal to
or smaller than 6 nm.
18. The apparatus as set forth in claim 15, wherein said
multi-layered metal wirings have an antenna ratio in the range of
1,000 to 100,000 both inclusive, and wirings in said multi-layered
metal wirings are spaced away from adjacent ones by 0.3 .mu.m or
greater.
19. The apparatus as set forth in claim 18, wherein said
multi-layered metal wirings have an antenna ratio in the range of
1,000 to 40,000 both inclusive.
20. The apparatus as set forth in claim 12, wherein said pulse
generator transmits pulses to said RF source voltage supplier to
thereby modulate said RF source voltage with pulse-off time being
equal to or smaller than 100 .mu.sec.
21. The apparatus as set forth in claim 20, wherein said pulse-off
time is equal to or greater than 20 .mu.sec.
22. The apparatus as set forth in claim 21, wherein said pulse-off
time is equal to or greater than 30 .mu.sec.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a method and an apparatus for
fabricating a semiconductor device, and more particularly to such a
method including a step of patterning multi-layered metal wirings
composed of aluminum, through inducive coupling plasma, and also to
such an apparatus for generating inducive coupling plasma to
thereby pattern multi-layered metal wirings.
[0003] 2. Description of the Related Art
[0004] A wiring layer is required to be patterned in a size smaller
and smaller with enhancement in integration of LSI. In order to
transfer a small-sized mask pattern to a layer such as an
electrically conductive layer and an insulating layer, such a layer
is usually etched by anisotropic dry etching which makes use of
plasma, such as reactive ion etching (RIE) and electron cyclotron
resonance (ECR) plasma etching.
[0005] On the other hand, as a semiconductor device has been
fabricated in a size smaller and smaller, a gate insulating film in
an insulating gate type field effect transistor (FET) is made
thinner and thinner. For instance, a latest gate insulating film is
designed to have a thickness of 10 nm or smaller. Such a thin gate
insulating film is likely to be damaged by just small electric
stress.
[0006] An electrically conductive layer is usually composed of
aluminum or alloy thereof. There are known a couple of anisotropic
dry etching methods in which plasma is generated, as methods for
dry-etching such an electrically conductive layer.
[0007] For instance, in one of such dry etching methods, an
electrically conductive layer composed of aluminum or alloy
thereof, formed on a semiconductor substrate, is etched with a
patterned resist film being used as a mask through plasma generated
from a mixture gas of and Cl.sub.2 gas. In plasma, the BCl.sub.3
gas exists as BCl.sup.2+, and the Cl.sub.2 gas produces Cl
radicals. These Cl species make chemical reaction with aluminum or
alloy thereof of which the electrically conductive layer is
composed, to thereby generate volatile AlCl.sub.3 having high vapor
pressure. The thus generated volatile AlCl.sub.3 is evaporated, and
resultingly, the electrically conductive layer composed of aluminum
or alloy thereof is etched.
[0008] In a plasma etching process, electrons as well as the
above-mentioned Cl ion species are incident to a substrate. If
there is a difference between incident positive and negative
electric charges, electric charges are accumulated in an
electrically conductive layer which is formed on a gate insulating
film and is electrically insulated from the substrate. As a result,
there is generated a difference in a voltage between the
electrically conductive layer and the substrate. Such a difference
in a voltage allows tunnel current to pass through the gate
insulating film, resulting in that dielectric characteristics of
the gate insulating film is varied, and hence, the gate insulating
film might reach dielectric breakdown.
[0009] As mentioned above, a plasma etching process in which a gate
electrode or an electrically conductive layer formed on a gate
insulating film, and electrically conductive layers electrically
connected to the gate electrode (hereinafter, a gate electrode and
such electrically conductive layers are referred to as "gate
wirings") are charged up, that is, electric charges are accumulated
in the gate wirings, might cause the gate insulating film to be
damaged. A plasma etching process is carried out, for instance,
when a gate wiring layer is patterned, when a contact hole is
formed reaching a gate wiring layer, when a contact hole reaching a
gate insulating layer is cleaned by sputter etching, and when
plasma-enhance chemical vapor deposition is carried out to a
surface of a substrate at which a gate wiring layer partially
appears.
[0010] In addition, if plasma formed non-uniformly above a
semiconductor substrate, there would be generated a difference
between an ion current and an electron current both to be
introduced into the semiconductor substrate. This difference might
allow a tunnel current to pass through a gate insulating film.
[0011] As a semiconductor device is integrated highly and highly,
an antenna ratio defined as a ratio of an area of a gate insulating
film to an area of an electrically conductive layer composed of
aluminum or alloy thereof is significantly increased. When an
electrically conductive film having a high antenna ratio is to be
etched by a plasma etching process, small non-uniformity in plasma
might allow much tunnel current to pass through a gate insulating
film.
[0012] It has been reported that even if there is generated plasma
having a profile of electric charges which is uniform to a flat
surface, there would occur charging damage called electron shading
damage inherent to high-density plasma etching, in a plasma etching
step in which a resist mask including an aperture having a high
aspect ratio, that is, a narrow space.
[0013] The above-mentioned electron shading damage is caused by
both charge imbalance between ion flux and electron flux at a
bottom of a space formed between wirings, and micro-loading which
is one of characteristics of dry etching.
[0014] Hereinbelow is explained the electron shading damage with
reference to FIG. 1.
[0015] With reference to FIG. 1, in ion sheath formed in an
electrode to which RF voltage is applied when plasma is discharged,
ion flux 101 is anisotropically incident to spaces formed between
adjacent metal wirings 105, whereas electron flux 102 is
isotropically incident to the spaces in the same manner as electron
flux being incident in plasma bulk.
[0016] Anisotropy of the electron flux 102 causes a majority of
electrons 104 is incident onto sidewalls of an insulating mask such
as resist masks 103. As a result, the electrons 104 are much
accumulated on the sidewalls of the resist masks 103 to thereby
generate a negative voltage on the resist masks 103. As a space
between the resist masks 103 is small, that is, as an aspect ratio
is high, negative voltages generated on the sidewalls of the resist
masks 103 overlap each other, resulting in that the negative
voltages generated around the resist masks 103 are further
increased. Accordingly, an amount of the electron flux 102 reaching
bottoms 106 of holes formed between the adjacent resist masks 103
is significantly reduced. Thus, there is generated imbalance
between the electron flux 102 and the ion flux 101 at the bottoms
106 of the holes having a high aspect ratio.
[0017] Dry etching has many characteristics, one of which is
micro-loading effect. Herein, the micro-loading effect is a
phenomenon in which an etching rate varies in dependence on an
aspect ratio. In general, an etching rate lowers as an aspect ratio
increases. Hence, though the metal wirings 105 have been already
etched in portions having a relatively low aspect ratio, the
bottoms 106 of the holes having a relatively high aspect ratio have
not been etched yet. In a period of time after the portions having
a relatively low aspect ratio have been etched for removal until
the bottoms 106 have been completely etched (hereinafter, such a
period of time is referred to as "injection time"), positive
electric charges are accumulated on the bottoms 106 due to charge
imbalance.
[0018] As a result, a gate electrode 108 has a positive voltage
relative to a silicon substrate 109. Then, electrons 111 are
injected into the gate electrode 108 from the silicon substrate 109
through a gate oxide film 110 in order to dissolve the charge
imbalance. A current caused by the injected electrons 111 is in
proportion to both a gate voltage and the above-mentioned injection
time.
[0019] If a current caused by the injected electrons 111 flow
excessively through the gate oxide film 110, the gate oxide film
110 would be degraded and/or damaged.
[0020] The explanation mentioned above is the reason why the
electron shading damage occurs.
[0021] Many attempts have been made to uniformize plasma by
generating plasma by virtue of pulse modulation. For instance,
Japanese Unexamined Patent Publications Nos. 6-267900 and 8-181125
have suggested methods of etching a wiring layer. In the methods,
an ECR plasma source applies RF bias voltage having a frequency of
600 kHz or smaller to a gas with a pulse cycle being 100 .mu.sec or
smaller and pulse-off time being in the range of 10 to 100 .mu.sec.
As a result, positive and negative ions are effectively produced,
and thus, electric charges are not accumulated on sidewalls of a
resist mask.
[0022] In particular, Japanese Unexamined Patent Publication No.
6-267900 teaches that it would be possible to prevent micro-loading
which occurs when a contact hole having a high aspect ratio is to
be formed by etching, by generating plasma which is modulated with
pulses having a frequency of 50 kHz.
[0023] Japanese Unexamined Patent Publication No. 61-13625 has
suggested a plasma-etching apparatus comprising first means for
generating plasma from process gas introduced into a reaction
chamber, second means for accelerating ions in plasma to thereby
radiate the thus accelerated ions to an object, third means for
modulating a discharge voltage, and fourth means for modulating an
applied voltage. The fourth means AM- or FM-modulates an applied
voltage to thereby control a profile of electron temperature, a
composition ratio of reaction species, and an ion energy
profile.
[0024] The above-mentioned conventional plasma etching apparatuses,
in particular, ECR plasma etching apparatus make use of expensive
magnets. In addition, it is reported that those magnets would
degrade electric characteristics of a sample. For this reason, an
inducive coupling plasma (ICP) etching apparatus is presently
suggested in place of the above-mentioned conventional plasma
etching apparatuses. Though the ICP etching apparatus generates
plasma having a smaller density than a density of plasma generated
in ECR plasma etching apparatus, the ICP etching apparatus has a
simpler structure than that of ECR plasma etching apparatus,
because the ICP etching apparatus includes no magnets. In addition,
the ICP etching apparatus has advantages of less electric damage to
a gate insulating film, higher mechanical reliability, higher
maintenance ability and lower fabrication and running costs
relative to the other etching apparatuses.
[0025] Japanese Unexamined Patent Publication No. 9-92645 has
suggested a method of fabricating a semiconductor device,
comprising the steps of transferring a semiconductor wafer into a
plasma etching chamber, and applying plasma to a semiconductor
wafer. The semiconductor wafer includes a gate insulating film
having a dielectric breakdown voltage of X volts and a thickness of
10 nm or smaller, an electrically conductive layer formed on the
gate insulating film and having an antenna structure having an
antenna ratio of 500 or greater, and a patterned insulator formed
on the electrically conductive layer and including apertures each
having an aspect ratio greater than 1. In plasma, electron
temperature Te (eV) is kept equal to or smaller than X
(Te.ltoreq.X).
[0026] In the suggested method, RF voltage having a frequency of
13.56 MHz is applied to process gas to thereby plasma in ICP
etching apparatus, and RF power having a frequency of 66.7 kHz is
applied to a substrate to thereby control a substrate voltage. RF
signals having waveforms analogous to RF output waveforms are
detected from an RF bias voltage source, and the thus detected RF
signals are transmitted to a pulse generator. The pulse generator
generates pulses having desired pulse-on time which is synchronized
to a desired phase in a cycle period equal to a cycle period of the
received RF signals. The pulses generated by the pulse generator
are transmitted to a power source to modulate or turn on or off RF
power having a frequency of 13.56 MHz, in accordance with the
pulses. Specifically, pulse-on time is set equal to 5 .mu.sec, a
pulse-off time is set equal to 10 .mu.sec, and a phase angle is set
equal to 240 degrees. Thus, it would be possible to keep an
electron temperature below a dielectric breakdown voltage of a gate
insulating film.
[0027] According to the Publication, as a pulse-off time is set
longer, a period of time in which an electron temperature is
reduced becomes longer, and an electron temperature at the end of
the period is further reduced. The Publication sets forth that
remarkable reduction in damage to a gate insulating layer is
dependent on the above-mentioned reduction in an electron
temperature.
SUMMARY OF THE INVENTION
[0028] It is an object of the present invention to provide a method
for fabricating a semiconductor device, including a step of
patterning a wiring layer through inducive coupling plasma, which
method makes it possible to prevent occurrence of electron shading
damage to a gate insulating film and etch a wiring layer with high
accuracy and high reliability.
[0029] It is also an object of the present invention to provide an
apparatus for fabricating a semiconductor device, which apparatus
generates inducive coupling plasma to thereby etch a wiring layer
without occurrence of electron shading damage to a gate insulating
film.
[0030] In one aspect of the present invention, there is provided a
method of fabricating a semiconductor device, including the steps
of (a) generating plasma in the following conditions: (a1) an RF
bias voltage has a frequency equal to or greater than 1 MHz, (a2)
an RF source voltage has a frequency equal to or greater than 1
MHz, (a3) the RF source voltage is modulated by pulses in a cycle
equal to or greater than 100 .mu.sec, and (a4) pulse-on time is
equal to or greater than 50 .mu.sec, and (b) patterning
multi-layered metal wirings by etching through the plasma.
[0031] It is preferable that the pulses have a rectangular
waveform.
[0032] It is preferable that the cycle is equal to or smaller than
500 .mu.sec, and the pulse-on time is equal to or smaller than 450
.mu.sec.
[0033] It is preferable that the multi-layered metal wirings are
composed of aluminum or aluminum alloy, in which case, the
multi-layered metal wirings preferably make electrical contact with
an n-channel MOSFET. It is also preferable that the n-channel MOSET
includes a gate insulating film having a thickness equal to or
smaller than 6 nm.
[0034] It is preferable that the multi-layered metal wirings have
an antenna ratio in the range of 1,000 to 100,000 both inclusive,
and wirings in the multi-layered metal wirings are spaced away from
adjacent ones by 0.3 .mu.m or greater.
[0035] It is preferable that the multi-layered metal wirings have
an antenna ratio in the range of 1,000 to 40,000 both
inclusive.
[0036] It is preferable that pulse-off time is equal to or smaller
than 100 .mu.sec, and that the pulse-off time is equal to or
greater than 20 .mu.sec, preferably than 30 .mu.sec.
[0037] In another aspect of the present invention, there is
provided an apparatus for fabricating a semiconductor device,
including (a) a hermetically sealed chamber, (b) a gas introducer
for introducing gas into the chamber, (c) a gas exhauster for
exhausting gas from the chamber, (d) an RF source voltage supplier
applying an RF source voltage having a frequency equal to or
greater than 1 MHz to the chamber to thereby generate inducive
coupling plasma from the gas, (e) an RF bias voltage source
applying an RF bias voltage to a substrate put in the chamber, the
RF bias voltage having a frequency equal to or greater than 1 MHz,
and (f) a pulse generator which transmits pulses to the RF source
voltage supplier to thereby modulate the RF source voltage supplier
in a cycle equal to or greater than 100 .mu.sec with pulse-on time
being kept equal to or greater than 50 .mu.sec.
[0038] It is preferable that the pulse generator generates pulses
each having a rectangular waveform.
[0039] It is preferable that the pulse generator transmits pulses
to the RF source voltage supplier to thereby modulate the RF source
voltage supplier in a cycle equal to or smaller than 500 .mu.sec
with the pulse-on time being kept equal to or smaller than 450
.mu.sec.
[0040] It is preferable that the semiconductor device includes
multi-layered metal wirings composed of aluminum or aluminum alloy,
in which case, it is also preferable that the semiconductor device
further includes an n-channel MOSFET with which the multi-layered
metal wirings make electrical contact. It is preferable that the
n-channel MOSET includes a gate insulating film having a thickness
equal to or smaller than 6 nm.
[0041] It is preferable that the pulse generator transmits pulses
to the RF source voltage supplier to thereby modulate the RF source
voltage with pulse-off time being equal to or smaller than 100
.mu.sec, but equal to or greater than 20 .mu.sec, preferably than
30 .mu.sec.
[0042] The advantages obtained by the aforementioned present
invention will be described hereinbelow.
[0043] In accordance with the present invention, conditions for
generating plasma when multi-layered metal wirings are to be
patterned are determined as follows.
[0044] A frequency of the RF bias voltage: 1 MHz or greater
[0045] A frequency of the RF source voltage: 1 MHz or greater
[0046] A cycle in which the RF source voltage is modulated: 100
.mu.sec or greater
[0047] Pulse-on time: 50 .mu.sec or greater
[0048] By determining the conditions as mentioned above, it would
be possible to reduce charging damage to a gate insulating film,
even if wirings are further spaced away from adjacent ones and/or
an antenna ratio of the multi-layered metal wirings is further
increased
[0049] It should be noted that conditions for generating plasma are
not to be limited to the above-mentioned ones, but may be varied
within the scope of the present invention.
[0050] In addition, the present invention is preferably applied to
multi-layered metal wirings composed of aluminum or alloy thereof,
but may be applied to a layer composed of other materials such as
polysilicon or silicon dioxide.
[0051] The above and other objects and advantageous features of the
present invention will be made apparent from the following
description made with reference to the accompanying drawings, in
which like reference characters designate the same or similar parts
throughout the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0052] FIG. 1 illustrates a model for explaining electron shading
damage.
[0053] FIG. 2 illustrates an apparatus for etching a wiring layer
in accordance with an embodiment of the present invention.
[0054] FIG. 3 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers.
[0055] FIG. 4 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 50 .mu.sec.
[0056] FIG. 5 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 120 .mu.sec.
[0057] FIG. 6 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 200 .mu.sec.
[0058] FIG. 7 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers without the scope of the present invention.
[0059] FIG. 8 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 450 .mu.sec.
[0060] FIG. 9 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 50 .mu.sec.
[0061] FIG. 10 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 120 .mu.sec.
[0062] FIG. 11 is a graph showing a relation between an antenna
ratio and a threshold voltage in various spacings between wiring
layers at pulse-on time of 200 .mu.sec.
[0063] FIG. 12 is a graph showing a relation between an electron
temperature and pulse-on time.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0064] FIG. 2 illustrates an apparatus for patterning a wiring
layer through inducive coupling plasma, in accordance with a
preferred embodiment of the present invention.
[0065] The illustrated apparatus is comprised of a container 1 made
of stainless, a bell jar 2 made of quartz or ceramics and located
above the container 1 to cooperate with the container 1 to define a
hermetically sealed reaction chamber 6 in the container 1 and the
bell jar 2, a coil 3 located on the bell jar 2 for generating
micro-waves which are transmissible through the bell jar 2, a
susceptor 4 placed in the reaction chamber 6 for mounting a
substrate 5 thereon, an RF source voltage supplier 8 applying an RF
source voltage to the reaction chamber 6 through the coil 3, a
pulse generator 10 transmitting pulses to the RF source voltage
supplier 8, and an RF bias source 9 applying an RF bias voltage to
the susecptor 4.
[0066] Though not illustrated, the apparatus further includes a gas
exhauster which exhausts gas out of the reaction chamber 6 to
thereby keep the reaction chamber 6 at a desired vacuum degree, a
gas introducer which introduces etchant gas such as BCl.sub.3 and
Cl.sub.2 into the reaction chamber 6 in a controlled amount, and a
temperature controller incorporated in the susceptor 4 for cooling
or heating the substrate 5 to thereby keep the substrate 5 at a
constant temperature.
[0067] When inducive coupling plasma 7 is to be generated in the
reaction chamber 6, an RF source voltage having a frequency equal
to or greater than 1 MHz is applied into the reaction chamber 6
from the RF source voltage supplier 8 through the coil 3. At the
same time, an RF bias voltage having a frequency equal to or
greater than 1 MHz is applied to the susceptor 4 from the RF bias
source 9 to thereby control a voltage of the substrate 5 such that
ions in the inducive coupling plasma 7 are accelerated to a desired
degree and thus caused to impinge on the substrate 5.
[0068] In the embodiment, both of the RF source voltage and the RF
bias voltage are designed to have a frequency of 1 MHz or greater.
The reason why the RF source voltage has a frequency equal to or
greater than 1 MHz is that inducive coupling plasma can be
generated more readily and more stably than when the RF source
voltage has a frequency smaller than 1 MHz. The reason why the RF
bias voltage has a frequency equal to or greater than 1 MHz is as
follows. If the RF bias voltage had a frequency smaller than 1 MHz,
a profile of ion energy becomes extensive from a lower energy band
to a higher energy band, that is, a half band width is made
extensive. As a result, ions in higher energy band deteriorate
resist selectivity. By designing the RF bias voltage to have a
frequency equal to or greater than 1 MHz, a half band width can be
made narrower, and hence, resist selectivity would be less
deteriorated.
[0069] In the embodiment, the RF source voltage generated by the RF
power source 8 is modulated by pulses generated by the pulse
generator 10 and having rectangular waveforms, into a voltage
having both a period of 100 .mu.sec or greater, that is, a
frequency of 10 kHz or smaller, and pulse-on time of 50 .mu.sec or
greater.
[0070] Hereinbelow is explained an example showing how much an
insulating layer is damaged in dependence on how the RF source
voltage is modulated with pulses.
[0071] In this example, it is assumed that there are formed a gate
insulating film having a thickness of 6 nm, a gate electrode having
a gate length of 0.25 .mu.m and a gate width of 10 .mu.m, and
wirings formed around the gate electrode and having an antenna
structure. Varying a space between adjacent wirings and an antenna
ratio, there was measured a threshold voltage Vt of an n-channel
MOSFET. In the measurement of the threshold voltage Vt, a drain
voltage Vd was set equal to 2.0 V, and a drain current Id was set
equal to 0.2 A.
[0072] The results of the measurement were shown in FIGS. 3 to
11.
[0073] In FIGS. 3 to 8, Cl.sub.2 and BCl.sub.3 gases were used as
etchant gases in flow rates of 110 and 45 sccm, respectively, and
CHF.sub.3 gas was used as an additive gas in a flow rate of 10
sccm. The RF source voltage supplied from the RF power source 8 was
designed to have a frequency of 2 MHz and to be equal to 1000 W,
and the RF bias voltage generated from the RF bias voltage source 9
was designed to have a frequency of 13.56 MHz and to be equal to
300 W. The substrate 5 was etched at a pressure of 10 mTorr and at
a temperature of 60 degrees centigrade in the apparatus illustrated
in FIG. 2.
[0074] In FIGS. 9 to 11, Cl.sub.2, BCl.sub.3 and CHF.sub.3 gases
were flown into the reaction chamber 6 in amounts of 80, 100 and 10
sccm, respectively. The other conditions are the same as the
above-mentioned conditions in FIGS. 3 to 8.
[0075] FIG. 3 shows the result of the measurement in prior art in
which pulse discharge is not carried out. In FIG. 3, the threshold
voltage Vt starts increasing when an antenna ratio is over 1000 in
the cases that spacings between adjacent wirings are 0.3 .mu.m, 0.4
.mu.m and 0.5 .mu.m. In particular, in a case that a spacing
between adjacent wirings is equal to 0.3 .mu.m, the threshold
voltage Vt starts lowering when an antenna ratio is over 10000.
This reduction in the threshold voltage Vt corresponds to complete
breakdown of a gate oxide film.
[0076] In FIG. 4, pulse-on time and pulse-off time were both set
equal to 50 .mu.sec. In cases that spacings between adjacent
wirings are 0.3 .mu.m and 0.4 .mu.m, the threshold voltage Vt
starts increasing when an antenna ratio is over about 1000.
However, in cases that spacings between adjacent wirings are 0.5
.mu.m, 0.6 .mu.m and 0.8 .mu.m, the threshold voltage Vt is kept
constant, even if an antenna ratio is higher and higher. This shows
that the present invention properly works in the case illustrated
in FIG. 4.
[0077] As illustrated in FIGS. 5 and 6, it is understood that the
threshold voltage Vt is prevented from increasing, as pulse-on time
is set longer and longer.
[0078] FIG. 7 shows a case which is out of the scope of the present
invention. In FIG. 7, the threshold voltage Vt increases even in a
case that a spacing between adjacent wirings is set equal to 0.5
.mu.m.
[0079] However, if pulse-on time is set too long, the threshold
voltage Vt increases again. As illustrated in FIG. 8, an upper
limit of a pulse cycle is about 500 .mu.sec, and an upper limit of
pulse-on time is about 450 .mu.sec.
[0080] In FIGS. 9 to 11 wherein a flow rate ratio among etchant
gases is varied, it is confirmed that the threshold voltage Vt is
prevented from increasing. Since FIG. 9 exhibits almost the same
results as the results shown in FIG. 3, it is understood that a
pulse cycle has to be equal to or greater than 100 .mu.sec, and
pulse-on time has to be equal to or greater than 50 .mu.sec.
[0081] Hereinbelow is explained why the advantages can be obtained
in the present invention.
[0082] FIG. 12 shows how a temperature of electrons in plasma
varies when pulse-off time is kept equal to 50 .mu.sec and pulse-on
time is varied. As references, FIG. 12 also shows how a temperature
of electrons varies in successive discharge not modulated with
pulses and how a temperature of electrons in plasma varies when
pulse-off time is kept equal to 30 .mu.sec and pulse-on time is
kept equal to 50 .mu.sec. The latter corresponds to the case
illustrated in FIG. 7.
[0083] It is conventionally known to those skilled in the art that
plasma damage could be suppressed by lowering a temperature of
electrons. A temperature of electrons has been conventionally
requested to lower in average among electrons. However, thereafter,
it is said that a gate insulating layer is not so much damaged at
an initial stage in generation of plasma.
[0084] In the present invention, a temperature of electrons is
slightly higher than a temperature of electrons observed in
successive discharge at a start-up of generation of pulses as
pulse-on time is set longer. However, at the same time, an
amplitude of a temperature of electrons becomes greater, and a
temperature of electrons becomes smaller. It is considered that a
temperature of electrons is more likely to be reduced by setting
pulse-on time longer, and as a result, the above-mentioned
advantages can be obtained.
[0085] This is just contrary to the conventional belief that longer
pulse-off time is more effective for reducing a temperature of
electrons than longer pulse-on time. This fact that longer pulse-on
time is effective for reducing a temperature of electrons was first
discovered by the inventor.
[0086] It should be noted that pulse-off time is not to be limited
to specific time. However, if pulse-off time is set too long,
plasma would be vanished with the result of failure in etching.
Thus, though dependent on a pulse cycle, pulse-off time is
necessary to be equal to or smaller than about 100 .mu.sec.
[0087] To the contrary, shorter pulse-off time would provide a
plasma density almost equal to a density of successive discharge.
However, if pulse-off time is set too short, a temperature of
electrons would be insufficiently lowered. Hence, though dependent
on length of pulse-on time, pulse-off time is necessary to be equal
to or greater than 20 .mu.sec, preferably, than 30 .mu.sec.
[0088] While the present invention has been described in connection
with certain preferred embodiments, it is to be understood that the
subject matter encompassed by way of the present invention is not
to be limited to those specific embodiments. On the contrary, it is
intended for the subject matter of the invention to include all
alternatives, modifications and equivalents as can be included
within the spirit and scope of the following claims.
[0089] The entire disclosure of Japanese Patent Application No.
11-100112 filed on Apr. 7, 1999 including specification, claims,
drawings and summary is incorporated herein by reference in its
entirety.
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