U.S. patent application number 10/336808 was filed with the patent office on 2003-06-05 for semiconductor wafer, method of manufacturing the same and semiconductor device.
This patent application is currently assigned to Kabushiki Kaisha Toshiba.. Invention is credited to Fukaura, Yasuhiro, Inohara, Masahiro, Kasai, Kunihiro, Matsumoto, Masahiko, Nakayama, Takeo, Oyamatsu, Hisato.
Application Number | 20030102530 10/336808 |
Document ID | / |
Family ID | 17627158 |
Filed Date | 2003-06-05 |
United States Patent
Application |
20030102530 |
Kind Code |
A1 |
Matsumoto, Masahiko ; et
al. |
June 5, 2003 |
Semiconductor wafer, method of manufacturing the same and
semiconductor device
Abstract
The object of the present invention is to provide a
semiconductor wafer in which a diffusion of Cu generated by a
thermal treatment such as a Cu wiring formation step into silicon
is prevented, and variations of transistor characteristics are
lessened. The object of the present invention is to provide a
method of manufacturing the same and a semiconductor device formed
from the same. In the present invention, a protection insulating
film for preventing Cu from diffusing into the inside of the wafer
is formed on a peripheral portion of a principal plane, a external
side plane and a rear plane of the wafer. With this protection
insulating film, the diffusion of Cu that is a wiring material into
a chip formation region of the wafer is prevented, so that the
variations of the transistor characteristic.
Inventors: |
Matsumoto, Masahiko;
(Kanagawa-ken, JP) ; Oyamatsu, Hisato;
(Kanagawa-ken, JP) ; Nakayama, Takeo;
(Kanagawa-ken, JP) ; Fukaura, Yasuhiro;
(Kanagawa-ken, JP) ; Kasai, Kunihiro;
(Kanagawa-ken, JP) ; Inohara, Masahiro; (Tokyo,
JP) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
1300 I STREET, NW
WASHINGTON
DC
20005
US
|
Assignee: |
Kabushiki Kaisha Toshiba.
|
Family ID: |
17627158 |
Appl. No.: |
10/336808 |
Filed: |
January 6, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10336808 |
Jan 6, 2003 |
|
|
|
09395204 |
Sep 14, 1999 |
|
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|
6525402 |
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Current U.S.
Class: |
257/618 |
Current CPC
Class: |
H01L 21/32051
20130101 |
Class at
Publication: |
257/618 |
International
Class: |
H01L 029/06 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 15, 1998 |
JP |
10-280590 |
Claims
What is claimed is:
1. A semiconductor wafer comprising: a semiconductor wafer having a
first plane in which an integrated circuit is going to be formed, a
second plane opposite the first plane and a peripheral region
between the first and the second planes; and a protection film
formed on said second plane and said peripheral region.
2. The semiconductor wafer according to claim 1, wherein said
protection film is a silicon nitride film.
3. The semiconductor wafer according to claim 1, wherein said
protection film prevents a diffusion of copper into a semiconductor
substrate.
4. A method of manufacturing a semiconductor wafer, comprising the
steps of: forming a protection film on substantially the entire
outside surface of a semiconductor wafer; and removing the
protection film on a region of said first plane in which an
integrated circuit will be formed.
5. The method according to claim 4, wherein the protection film is
a silicon nitride film.
6. The method according to claim 4, wherein the protection film
prevents a diffusion of copper into a semiconductor substrate.
7. The method according to claim 4, wherein the protection film
also forms gate insulation saidewalls of an integrated circuit.
8. A method for manufacturing a semiconductor wafer, comprising the
steps of: growing a cylindrical single crystal semiconductor ingot;
forming a protection insulating film on a surface of said single
crystal semiconductor ingot, the protection insulating film
preventing a diffusion of copper into said single crystal
semiconductor ingot; and slicing said single crystal semiconductor
ingot into a plurality of semiconductor wafers, each semiconductor
wafer having an external peripheral plane on which said protection
insulating film is formed.
9. The method according to claim 8, further comprising the step of:
forming a protection insulating film also on a peripheral portion
of a principal plane and a rear plane of said semiconductor wafer,
the protection insulating film preventing a diffusion of copper
into said semiconductor wafer and extending to said external
peripheral plane.
10. A semiconductor device comprising: a semiconductor chip having
a first plane in which an integrated circuit is going to be formed
and a second plane opposite the first plane; and a protection
insulating film formed on said second plane.
11. The semiconductor device according to claim 10, wherein a
copper ion or a copper composition is on a surface of said
protection insulating film or within said protection insulating
film.
12. The semiconductor device according to claim 10, wherein a
copper ion or a copper composition is contained in a surface
between said protection insulating film and said semiconductor
chip.
13. The semiconductor device according to claim 10, wherein said
protection insulating film prevents a diffusion of copper into a
semiconductor substrate.
14. The semiconductor device according to claim 10, wherein said
protection insulating film is formed of silicon nitride.
15. The semiconductor device according to claim 10, where the
integrated circuit includes at least one element or layer formed of
copper.
16. A method of manufacturing a semiconductor device, comprising
the steps of: forming a protection film on substantially the entire
outside surface of a semiconductor wafer; removing the protection
film from a region of the semiconductor wafer, and forming a
integrated circuit in the region, the integrated circuit including
a copper wiring.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor wafer
(hereinafter, referred to as a wafer) in which a semiconductor
device is formed, a novel semiconductor device exhibiting less
variation in a transistor characteristic, and a method for
manufacturing the same.
[0003] 2. Description of the Related Art
[0004] A wafer formed of silicon or germanium, which is used for a
semiconductor device, has heretofore been manufactured usually by
slicing a cylindrical ingot that is grown by a single crystal
growth method such as a high frequency induction-heating method or
a pulling-up method. A plurality of processed semiconductor
integrated circuits are formed on a principal plane of the wafer
which has been formed from the ingot. Thereafter, the wafer is cut
along scribe lines into chips in which an integrated circuit area
is formed, and the chips are separated from each other.
[0005] FIG. 1 is a section view showing a conventional
semiconductor device formed in a semiconductor substrate. The
semiconductor device is formed on a wafer, and the wafer is cut
into chips in which an integrated circuit is formed. The chips are
finally separated from each other. Accordingly, FIG. 1 is a section
view of the chip, and especially illustrates a chip formed in a
portion of the wafer, which is close to an external peripheral
surface and a peripheral region where no integrated circuit is
formed. A semiconductor substrate 1 is, for example, a p-type
silicon semiconductor. The left side of FIG. 1 is an external
peripheral portion of the wafer and a peripheral portion thereof,
and in these portions the surface of the semiconductor substrate 1
is exposed for the reason described later. An inner portion of the
external peripheral portion and the peripheral portion, that is, a
central portion and a right side, show a chip region. In the chip
region, an element isolation region 2 formed of silicon dioxide
(SiO2), which has a Shallow Trench Isolation (STI), is formed by a
Local Oxidation of Silicon (LOCOS) method. N-type source/drain
regions 3 are formed in an element region partitioned by the
element isolation region 2. A gate electrode 5 formed of
polysilicon or the like is formed by a thermal oxide method on a
portion of a gate insulating film formed of a silicon oxide film,
the portion thereof being located between the source/drain regions
3. The gate insulating film 4 is formed on the entire surface of
the semiconductor substrate 1, and, on the semiconductor substrate
1, a silicon oxide film is formed so as to cover the gate electrode
5.
[0006] The silicon oxide film is subjected to an anisotropic
etching such as an RIE (Reactive Ion Etching) and processed to a
side wall insulating film 6 left on the side wall of the gate
electrode 5. Subsequently, on the semiconductor substrate 1, an
interlayer insulating film 7 formed of such as BPSG (Boron-doped
Phospho-Silicate Glass) is deposited, and flattened. A contact hole
which communicates with one of the source/drain regions 3 is formed
in the interlayer insulating film 7, and a connection wiring 8
formed of such as tungsten, for example (W) is filled in the
contact hole. A metal film formed of copper (Cu) is deposited on
the flattened surface of the interlayer film 7, and patterned, thus
forming a copper wiring 9 electrically connected to the connection
wiring 8. On the copper wiring 9, a protection insulating film can
be formed, or a plurality of copper wirings can be formed
interposing the interlayer insulating film during the formation of
the protection insulating film.
[0007] The above-described copper wiring technology used for
semiconductor devices has been involved in a problem that diffusion
of copper into a silicon wafer is seriously anxious for.
[0008] In the conventional copper wiring technology, copper is
principally covered with a barrier film such as Ta, TiN and SiN.
However, copper may attach to a wafer edge and a rear surface of
the wafer during formation of the barrier film, or the copper may
attach to them from a manufacturing apparatus and a wafer carrier.
Since resist is usually removed from the wafer edge by about 1 to 3
mm before the time of patterning the wafer, the surface of the
semiconductor substrate corresponding to the portion where the
resist is removed is exposed after an etching treatment.
[0009] A SiN film is formed on a region where transistors are
formed, so that the diffusion of the copper into that region can be
prevented. However, the silicon substrate formed of silicon is
exposed in its rear surface and its wafer edge portion, and in such
situation, when the wafer is subjected to the copper processing
step, the copper diffuses into a chip from the external periphery
of the wafer, so characteristics of the transistors formed in the
chip may vary.
[0010] To be more specific, with regard to the conventional
semiconductor substrate, for example, a silicon wafer is formed of
only silicon. In order to prevent the attachment of resist to the
carrier, the resist of the periphery portion of the wafer is
removed in manufacturing steps of the semiconductor device using
such wafer, especially in a lithography step as described above.
Accordingly, since the wafer edge portion is always exposed to
etching atmosphere, so that the silicon substrate comes to be
exposed. As a result, the contamination of the semiconductor
substrate due to the attachment of the copper to the silicon
portion in forming the copper wiring occurs as described above.
Furthermore, there has been a problem that when a high
concentration semiconductor substrate having a p-type epitaxial
silicon semiconductor layer formed therein (p-epi on p.sup.+
substrate) is employed, impurities diffuse to the outside of the
semiconductor substrate during a thermal step.
SUMMARY OF THE INVENTION
[0011] The present invention was made in view of the foregoing
circumstances, and the object of the present invention is to
provide a wafer which prevents a diffusion of copper to silicon due
to a thermal treatment such as a copper wiring formation step and
lessens the variations in transistor characteristics, a method for
manufacturing the same, and a semiconductor device formed of the
same.
[0012] The present invention is featured by forming a protection
insulating film in a peripheral area (peripheral portion) of a
principal plane of the wafer, an external side plane and a rear
plane, which prevents a diffusion of copper to the inside of the
wafer, specifically a protection insulating film formed of a
material having a small Cu diffusion coefficient. The protection
insulating film prevents the copper that is a wiring material from
diffusing into a chip formation region of the wafer, and controls
the changes of transistor characteristics caused by the Cu
diffusion.
[0013] The wafer of the present invention is first characterized in
that the wafer has a semiconductor wafer having a first plane where
an integrated circuit is formed, a second plane and a peripheral
area, and a protection film formed in the second plane and the
peripheral area. The wafer of the present invention is secondly
characterized in that the wafer has a semiconductor wafer having a
first plane where an integrated circuit is formed, a second plane
and a peripheral area, and a protection film formed of silicon
nitride, which is formed in the second plane and the peripheral
area.
[0014] A first aspect of a method for manufacturing the wafer of
the present invention is that the method comprises the step of:
forming a protection film on a first plane having an integrated
circuit formed therein, a second plane and a peripheral area of a
semiconductor wafer; and removing the protection film in a region
forming the integrated circuit on the first plane. A MOS transistor
which has a gate electrode having a side wall insulating film on
its side wall is included in the integrated circuit. The foregoing
protection insulating film may be formed in the step for forming
this side wall insulating film.
[0015] Furthermore, a second aspect of the method for manufacturing
the wafer of the present invention is that the method comprises the
steps of: growing a cylindrical semiconductor single crystal ingot;
forming a protection insulating film in a surface of the single
crystal ingot, the protection insulating film preventing a
diffusion of copper into the interior of the single crystal ingot;
and slicing the single crystal ingot, thereby forming a plurality
of semiconductor wafers, each having an external side plane, in
which the protection insulating film is formed. The second aspect
of the method for manufacturing the wafer of the present invention
may comprises a step for forming a protection insulating film which
extends to the external side plane and prevents the diffusion of
the copper to the interior of the semiconductor wafer.
[0016] A semiconductor device of the present invention comprises a
semiconductor chip having a first plane where an integrated circuit
is formed and a second plane, the integrated circuit formed in the
first plane; and a protection insulating film formed on the entire
surface of the second plane.
[0017] Other objects, features, and advantages of the present
invention will become apparent from the following detailed
description. It should be understood, however, that the detailed
description and specific examples, while indicating preferred
embodiments of the invention, are given by way of illustration
only, since various changes and modifications within the spirit and
scope of the invention will become apparent to those skilled in the
art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] A more complete appreciation of the present invention and
many of its attendant advantages will be readily obtained by
reference to the following detailed description considered in
connection with the accompanying drawings, in which:
[0019] FIG. 1 is a section view showing a manufacturing step of a
conventional semiconductor device;
[0020] FIG. 2 is a plan view showing a principle plane of a wafer
of a first embodiment;
[0021] FIGS. 3(a) and 3(b) are section views showing manufacturing
steps for manufacturing the wafer of the first embodiment;
[0022] FIGS. 4(a) and 4(b) are section views showing manufacturing
steps for manufacturing the wafer of the first embodiment;
[0023] FIG. 5 is a section view showing a manufacturing steps for
manufacturing the wafer of the first embodiment;
[0024] FIG. 6 is a plan view showing a principal plane of the wafer
of the first embodiment;
[0025] FIGS. 7(a) and 7(b) are section views showing manufacturing
steps for manufacturing a wafer of a second embodiment;
[0026] FIG. 8 is a section view showing a manufacturing step of the
wafer of the second embodiment;
[0027] FIG. 9 is a section view showing a manufacturing step of a
wafer of a third embodiment;
[0028] FIGS. 10(a) and 10(b) are section views showing
manufacturing steps for manufacturing the wafer of the third
embodiment;
[0029] FIGS. 11(a) and 11(b) are section views showing
manufacturing steps for manufacturing a wafer of a fourth
embodiment;
[0030] FIGS. 12(a) and 12(b) are section views showing
manufacturing steps for manufacturing the wafer of the fourth
embodiment;
[0031] FIG. 13 is a section view showing a manufacturing step for
manufacturing the wafer of the fourth embodiment;
[0032] FIG. 14 is a plan view showing a principal plane of the
wafer of the fourth embodiment;
[0033] FIG. 15 is a plan view showing a principal plane of a wafer
of a fifth embodiment;
[0034] FIG. 16 is a plan view of a semiconductor substrate of the
fifth embodiment;
[0035] FIGS. 17(a) and 17(b) are perspective views of an ingot of
the fifth embodiment;
[0036] FIGS. 18(a) and 18(b) are perspective views of the ingot of
the fifth embodiment and a plan view of a wafer of the fifth
embodiment;
[0037] FIGS. 19(a) and 19(b) are section views showing
manufacturing steps for manufacturing a semiconductor device of a
sixth embodiment;
[0038] FIGS. 20(a) and 20(b) are section views showing
manufacturing steps for manufacturing the semiconductor device of
the sixth embodiment; and
[0039] FIG. 21 is a section view showing the semiconductor device
of the sixth embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0040] Embodiments of the present invention will be described with
reference to the accompanying drawings in detail. A first
embodiment will be described with reference to FIGS. 2 to 6.
[0041] FIG. 2 is a plan view of a principal plane of a wafer, FIGS.
3(a) to 5 are section views of the wafer, and FIG. 6 is a plan view
of the principal plane of the wafer after formation of a chip in
its chip formation region. A wafer 100 is formed of, for example, a
p-type silicon semiconductor substrate which is obtained by slicing
an semiconductor ingot and processing to a predetermined shape. A
trench is formed in its principal plane, and an insulating film
such as a silicon oxide film (SiO.sub.2) is filled in the trench.
Thus, an element isolation region such as an STI structure is
formed. A chip formation region 101 is formed on the principal
plane of the wafer 100 when the STI structure is formed. After the
element isolation region is formed, a silicon oxide (SiO2) film 102
is formed on the entire surface of the wafer 100 by a thermal
oxidation and the like. Next, a silicon nitride (SiN) film 103 is
deposited on the silicon oxide film 102 by a LPCVD (Low Pressure
Chemical Vapor Deposition) method. Subsequently, a polysilicon film
104 is deposited on the silicon nitride film 103 by the LPCVD
method. Furthermore, a silicon nitride film 105 is deposited on the
polysilicon film 104 by the LPCVD method (FIG. 3(a)).
[0042] Next, photoresist 106 is applied onto the silicon nitride
film 105 formed on the principal plane of the wafer 100, and the
photoresist 106 on the peripheral portion of the wafer 100 is
removed by patterning the photoresist 106. Then, the portions of
the silicon nitride film 105 on the peripheral portion of the
principal plane, the external side plane and the rear plane of the
wafer 100 are removed by an isotropic etching such method as an RIE
using the patterned photoresist 106 as a mask. Specifically, the
silicon nitride film 105 and the photoresist 106 formed on the
silicon nitride film 105 cover the region other than the peripheral
portion of the principal plane where the chip is to be formed (FIG.
3(b)).
[0043] Next, the photoresist 106 is removed, and then the
polysilicon film 104 on the peripheral portion of the principal
plane of the wafer 100, the external side plane of the wafer 100
and the rear plane of the wafer 100 is oxidized by a thermal
treatment step, and a silicon oxide film 107 is formed (FIG. 4(a)).
Subsequently, the silicon nitride film 105 is removed, and
thereafter the polysilicon film 104 which has been covered with the
silicon nitride film 105 is removed by, for example, a dry etching
method, so as to expose the silicon nitride film 103 partially
(FIG. 4(b)). Next, the exposed silicon nitride film 103 is removed
by hot phosphoric acid using the silicon oxide film 107 on the
peripheral portion of the principal plane of the wafer 100, the
external side plane of the wafer 100, and the rear plane of the
wafer 100 as a mask (FIG. 5).
[0044] Thus, the main central area of the principal plane of the
wafer 100 where the chip is formed is covered with the silicon
oxide film 102, and the peripheral portion of the principal plane,
the external side plane, and the rear plane are covered with a
stacked body composed of the silicon nitride film 103 and the
silicon oxide film 107. The silicon oxide film 102 is used as a
gate insulating film formed on the wafer 100.
[0045] The wafer 100 is subjected to treatments (a thin film
formation treatment, an oxidation treatment, a doping treatment, an
annealing treatment, a resist treatment, an exposure treatment, an
etching treatment and the like) after the element isolation region
formation step and the gate insulating film formation step, thus
forming an integrated circuit in each of the chip formation region
101, and the chip formation region 101 is processed to the chip
108. Thereafter, the wafer 100 is cut along the scribe line formed
in its principal plane, and the chip 108 is separated from each
other (FIG. 6). Since the chips A, B and C partially covered with
the protection insulating film 107 shown in FIG. 5 sometimes
exhibit unstable characteristics, these chips are not used as the
product.
[0046] Since the wafer used in this embodiment is covered with the
silicon nitride film covered with the silicon oxide film in its
peripheral portion of the principal plane, its external side plane
and its rear plane, it is possible to prevent the silicon substrate
from being exposed in its peripheral portion of the principal plane
during the Cu wiring formation step among the foregoing treatment
steps. As a result, diffusion of copper that is a wiring material
into the chip formation region of the wafer can be prevented, and
variations of transistor characteristics due to the copper
diffusion can be controlled. Specifically, the silicon nitride film
and the silicon oxide film are used as a protection insulating film
for preventing the copper diffusion.
[0047] Next, a second embodiment will be described with reference
to FIGS. 7 and 8.
[0048] FIGS. 7 and 8 are section, a views of a wafer. The wafer 200
is formed of, for example, a p-type silicon semiconductor substrate
obtained by slicing an ingot and processing to a predetermined
shape. The wafer 200 forms a trench in its principal plane, and an
insulating film such as a silicon oxide (SiO.sub.2) film is filled
in the trench, thus forming an element isolation region of an STI
structure. When the element isolation region is formed, a chip
formation region (not shown) is formed in the principal plane of
the wafer 200. After the formation of the element isolation region,
a silicon oxide (SiO.sub.2) film 201 is deposited by, for example,
an LPCVD method on the entire surface of the silicon wafer 200
(FIG. 7(a)).
[0049] Subsequently, photoresist 202 is applied onto the silicon
oxide film 201 on the principal plane of the wafer 200, and the
photoresist is patterned, thus removing the portion of the
photoresist 202 on the peripheral portion of the principal plane of
the wafer 200. Then, the silicon oxide film 201 on the peripheral
portion of the principal plane, the external side plane and the
rear plane of the wafer 200 is removed by an isotropic etching such
as an RIE. Thus, the region other than the peripheral portion of
the principal plane, where chips are to be formed, is covered with
the silicon oxide film 201, and the photoresist 202 is left on the
film 201 (FIG. 7(b)).
[0050] Next, after removing the photoresist 202, a silicon nitride
film 203 is deposited on the silicon oxide film 201 by, for
example, a LPCVD method. Thereafter, the surface of the silicon
nitride film 203 is subjected to a flattening treatment by a CMP
(Chemical Mechanical Polishing) technique using the silicon oxide
film 201 as a stopper until the silicon oxide film 201 is exposed
(FIG. 8). As a result of the flattening treatment, the situation
where the silicon nitride film 203 is formed on the peripheral
portion of the wafer 200 and the rear plane thereof is created. The
silicon oxide film 201 is afterward removed by etching.
[0051] Thus, the peripheral portion of the principal plane, the
external side plane and the rear plane of the wafer 200 are covered
with the silicon nitride film 203. The wafer 200 is subjected to
treatments (a thin film formation treatment, an oxidation
treatment, a doping treatment, an annealing treatment, a resist
treatment, an exposure treatment, an etching treatment and the
like) after the element isolation region formation step, thus
forming an integrated circuit in each of the chip formation region,
and the chip formation regions are processed to the chip 108.
Thereafter, the wafer is cut along the scribe line formed in its
principal plane, and the chips are separated from each other.
[0052] Since the wafer used in this embodiment is covered with the
silicon nitride film covered with the silicon oxide film in its
peripheral portion of the principal plane, its external side plane
and its rear plane, it is possible to prevent the silicon substrate
from being exposed in its peripheral portion of the principal plane
during the Cu wiring formation step among the foregoing treatment
steps. Specifically, the silicon nitride film is used as a
protection insulating film for preventing the copper diffusion. By
the presence of this protection insulating film, diffusion of
copper that is a wiring material into the chip formation region of
the wafer can be prevented, and variations of transistor
characteristics due to the copper diffusion can be controlled.
[0053] Next, a third embodiment of the present invention will be
described with reference to FIGS. 9 and 10(a) and 10(b). FIGS.
9,10(a) and 10(b) are section, a views for explaining manufacturing
steps to form a protection insulating film on a wafer.
[0054] The wafer 300 is formed of, for example, a p-type silicon
semiconductor substrate obtained by slicing an ingot and processing
to a predetermined shape. This embodiment has a feature in that in
order to form the protection insulating film, a dummy wafer is
employed. The silicon wafer 300 and the dummy wafer 301 having a
diameter slightly smaller than that of the wafer 300 are stacked.
The peripheral portion of the silicon wafer 300 projects from the
dummy wafer after stacking the wafer 300 and the dummy wafer 301
upon another (FIG. 9). In a situation where the plurality of
silicon wafers and dummy wafers are placed upon another, a silicon
nitride (SiN) film is deposited by a LPCVD method around the
lamination body composed of the plurality of silicon wafers and
dummy wafers (FIG. 10(a)). Thereafter, when the silicon wafers are
separated from the lamination body, the silicon wafer having a
wafer edge portion in which the silicon nitride film is deposited
is prepared (FIG. 10(b)). However, the central portion of the rear
plane is not covered with the silicon nitride film as shown in FIG.
10(b). Accordingly, before the Cu wiring step is performed, the
silicon nitride film is left as a protection insulating film for
preventing the diffusion of copper to the interior of the wafer in
the wafer processing step when the side wall insulating film of the
gate electrode is formed by the silicon nitride film. Thus, it is
possible to cover a specified portion with the protection
insulating film completely. In other words, in such case, the
protection insulating film is formed in the two steps, that is, in
the pretreatment prior to the wafer processing step and in the
wafer processing step.
[0055] As described above, the peripheral portion of the principal
plane, the side plane and the rear plane of the wafer 300 are
covered with the silicon nitride film 302. The wafer 300 is
subjected to treatments (a thin film formation treatment, an
oxidation treatment, a doping treatment, an annealing treatment, a
resist treatment, an exposure treatment and an etching treatment)
after the element isolation region formation step, and an
integrated circuit is formed in each chip formation region. The
chip formation region is processed to a chip. Thereafter, the wafer
is cut along the scribe line formed in the principal plane of the
wafer 300, and the chip is separated from each other.
[0056] Since the wafer used in this embodiment is covered with the
silicon nitride film covered with the silicon oxide film in its
peripheral portion of the principal plane, its external side plane
and its rear plane, it is possible to prevent the silicon substrate
from being exposed in its peripheral portion of the principal plane
during the Cu wiring formation step among the foregoing treatment
steps. Specifically, the silicon nitride film is used as a
protection insulating film for preventing the copper diffusion. By
the presence of this protection insulating film, diffusion of
copper that is a wiring material into the chip formation region of
the wafer can be prevented, and variations of transistor
characteristics due to the copper diffusion can be controlled.
Moreover, since the step in the wafer processing steps is used, the
step is simplified.
[0057] A material of the dummy wafer is not limited to silicon, any
material may be satisfactorily used for the dummy wafer as long as
the dummy wafer is used for a spacer.
[0058] Next, a fourth embodiment will be described with reference
to FIGS. 11(a) to 14.
[0059] This embodiment has a feature in that two wafers are adhered
to each other, thus forming a single wafer. FIGS. 11(a), 11(b) and
FIGS. 12(a), 12(b) are sectional views for explaining steps to form
a protection insulating film on a wafer, and FIG. 13 is a plan view
of the wafer. The wafers 400a and 400b are formed of, for example,
a p-type silicon semiconductor substrate, which is obtained by
slicing an ingot and by processing to a predetermined shape. A
silicon nitride film 401 is deposited on the entire surface of the
wafer 400a by a LPCVD method. Subsequently, the surface of the
silicon nitride film 401 is oxidized by a thermal treatment, and a
silicon oxide film 402 is formed (FIG. 11(a)).
[0060] Next, the other silicon wafer 400b is integrated with the
wafer 400a by adhering the wafer 400b to the silicon oxide film 402
formed on the silicon nitride film 401 (FIG. 11(b)). Subsequently,
photoresist (not shown) patterned is applied onto the wafer 400b,
and thereafter the wafer 400b is etched by a RIE using the
photoresist as a mask. Thus, a trench 403 reaching to the silicon
nitride film 401 is formed on the peripheral portion of the
principal plane of the wafer 400b (FIG. 12(a)). A silicon nitride
film 404 is deposited by a CVD method (FIG. 12(b)). Thereafter, the
surface of the silicon nitride film 404 is flattened by a CMP until
the principal plane of the wafer 400b is exposed (FIG. 13).
[0061] It is possible to produce a situation where a part of the
peripheral portion of the principal plane, the external side plane
and the rear plane of the wafer 400b are covered with the silicon
nitride film. Although the part of the peripheral portion of the
principal plane is exposed as shown in FIG. 14, the copper never
enters from the peripheral portion of the wafer 400b into the
central portion thereof.
[0062] As described above, the peripheral portion of the principal
plane, the external side plane and the rear plane of the wafer are
covered with the silicon nitride film. The wafer is subjected to
treatments (a thin film formation treatment, an oxidation
treatment, a doping treatment, an annealing treatment, a resist
treatment, an exposure treatment and an etching treatment) after
the element isolation region formation step, and an integrated
circuit is formed in each chip formation region. The chip formation
region is processed to a chip. Thereafter, the wafer is cut along
the scribe line formed in the principal plane of the wafer, and the
chip is separated from each other.
[0063] Since the wafer used in this embodiment is covered with the
silicon nitride film covered with the silicon oxide film in its
peripheral portion of the principal plane, its external side plane
and its rear plane, it is possible to prevent the silicon substrate
from being exposed in its peripheral portion of the principal plane
during the Cu wiring formation step among the foregoing treatment
steps. Specifically, the silicon nitride film is used as a
protection insulating film for preventing the copper diffusion. By
the presence of this protection insulating film, the diffusion of
copper that is a wiring material into the chip formation region of
the wafer can be prevented, and variations of transistor
characteristics due to the copper diffusion can be controlled.
Moreover, since the step in the wafer processing steps is used, the
step is simplified.
[0064] Next, a fifth embodiment of the present invention will be
described with reference to FIGS. 15 to 18.
[0065] FIG. 15 is a plan view of a wafer having a side plane
covered with a protection insulating film for preventing diffusion
of copper, and FIG. 16 is a partial section view showing a half of
a principal plane of the wafer and a half of the left portion of
the wafer. FIG. 17 is a perspective view of an ingot, and FIG. 18
is a perspective view of the ingot and a plan view of the wafer. In
this embodiment, the peripheral portion of the wafer 500 is covered
with a protection insulating film 501 for preventing the diffusion
of copper. Specifically, the portion extending from the outermost
of the wafer to the central portion of the wafer by several mm, for
example, 1 mm, is composed of the protection insulating film 501
formed of a silicon nitride film (FIG. 15). Accordingly, an end
portion of the interlayer insulating film 503 formed of a silicon
oxide film which covers the gate electrode 502 is disposed inside
the external periphery of the wafer 500, and the end portion of the
interlayer insulating film 503 is formed on the protection
insulating film 501. Thus, even though the Cu wiring is formed on
the interlayer insulating film 503, the Cu wiring does not contact
with the silicon wafer directly, so that the diffusion of the
copper into the wafer can be prevented (FIG. 16). Furthermore, also
when a high concentration semiconductor substrate like a
p-epitaxial on p.sup.+ substrate is employed, the exposed portion
of the rear plane at the peripheral portion of the wafer is formed
of a silicon nitride (SiN), so that diffusion of impurities toward
the outside of the wafer due to thermal steps during the
manufacturing of the semiconductor device can be prevented.
[0066] The wafer 500 shown in FIG. 5 is manufactured in the
following manner. The silicon ingot prepared, for example, by a
well-known pulling-up method is processed to a predetermined
diameter (FIG. 17(a)). In the conventional method, the ingot is
sliced, thus cutting out the wafer. In this embodiment, the entire
surface of the ingot 510 is subjected to a nitriding treatment,
whereby the entire surface of the ingot is converted to a silicon
nitride film 501 serving as a protection insulating film. As
another method, there is a method in which the silicon nitride film
501 is deposited to a predetermined thickness on the surface of the
ingot 510 by a chemical vapor deposition (CVD) method (FIG. 17(b)).
The ingot 510 covered with the protection insulating film 501
formed in the above described manner is sliced to a predetermined
thickness, and the surface of the sliced ingot is processed. Thus,
a wafer shown in FIG. 15 is formed.
[0067] The protection insulating film for preventing the diffusion
of copper, which is formed on the wafer, is not limited to the
foregoing silicon nitride film, and, for example, a silicon oxide
film may be satisfactory. Such silicon oxide film is formed in the
following manner. An oxidation treatment by a thermal oxidation
method is performed for the foregoing ingot 510 that has not been
undergone a surface treatment, thus chemically converting the
surface of the ingot to a silicon oxide film 505 having a
predetermined thickness (FIG. 18(a)). As another method, there is a
method to deposit a silicon oxide film 505 having a predetermined
thickness on the surface of the ingot 510 by a chemical vapor
deposition (CVD) method. The ingot 510 that has been subjected to
the surface treatment is sliced and polished, thus obtaining a
silicon wafer 500 having a peripheral portion formed of the silicon
oxide film 505 (FIG. 18(b)).
[0068] In this embodiment, since the foregoing protection
insulating film is formed on the peripheral portion of the
principal plane of the wafer where the integrated circuit is
formed, the peripheral portion of the principal plane of the wafer
in which no photoresist is inherently formed is not exposed by
etching when the Cu wiring is formed on the principal portion.
Accordingly, the copper does not diffuse into the chip formation
region of the wafer from this portion. Furthermore, since the rear
plane of the wafer is exposed, it is expected that the copper may
diffuse from the rear plane of the wafer. When such diffusion must
be prevented, the protection insulating film such as a silicon
oxide film or a silicon nitride film can be formed on the rear
plane of the wafer after the preparation of the wafer. Among the
wafer treatment steps, in a step for forming a side wall insulating
film formed of a silicon nitride film, which is performed before
the Cu wiring formation step, the foregoing silicon nitride film as
the protection insulating film may be formed.
[0069] A sixth embodiment of the present invention will be
described with reference to FIGS. 19(a) and 19(b), FIGS. 20(a) and
20(b) and FIG. 21. In this embodiment, a protection insulating film
for preventing a diffusion of copper is formed by utilizing the
formation of the foregoing side wall insulating film of the gate
electrode. A method of this embodiment will be described below.
[0070] FIGS. 19(a) and 19(b) and FIGS. 20(a) and 20(b) are
sectional views showing manufacturing steps of a semiconductor
device of this embodiment. The semiconductor device is formed on a
wafer. The wafer is finally cut, and each chip in which the
semiconductor device is formed is separated from others.
Accordingly, FIGS. 19(a) and 19(b) and FIGS. 20(a) and 20(b) show
sectional views of the chip communicated with the peripheral
portion of the wafer. This peripheral portion of the wafer is
removed when the chip is separated from each other. The
semiconductor device 601 is formed of, for example, a p-type
silicon semiconductor. The peripheral portion of the wafer is
located on the left side of the view. The inside of the peripheral
portion of the wafer, that is, the central portion and right side
of the drawing, are a chip region. An element isolation region 602
of a STI structure, which is formed of SiO2, is formed in the chip
region by a LOCOS method. By an ion-implantation, a n-type
extension region 603 and source/drain regions 3 are formed in the
element region partitioned by the element isolation region 602. A
gate insulating film 604 formed of SiO2 is formed on the chip
region of the semiconductor substrate 601 by a thermal oxidation. A
gate electrode 605 formed of polysilicon is formed on the gate
insulating film 604 (FIG. 19(a)).
[0071] Next, a silicon nitride film 606 is formed, by a LPCVD
method or the like, on the entire surface of the semiconductor
substrate 601, that is, on the principal plane, the external side
plane and the rear plane of the wafer (FIG. 19(b)). Next, the
portion where the protection insulating film is to be formed is
masked, and a side wall insulating film 607 formed of a silicon
nitride film is formed on the side surface of the gate electrode
605 by an isotropic etching such as an RIE. The protection
insulating film 608 for preventing the diffusion of copper is
formed on the peripheral portion, the external side plane and the
rear plane of the wafer. Thereafter, impurities are implanted into
source/drain formation regions using the side wall insulating film
607 as a mask, and the n-type source/drain regions 609 is formed
(FIG. 19(a)).
[0072] Next, an interlayer insulating film 610 formed of, for
example, BPSG is deposited on the semiconductor substrate 601, and
flattened. Furthermore, a silicon nitride film 611 having a smaller
thickness than that of the interlayer insulating film 610 is
deposited on the flattened surface of the interlayer insulating
film 610. A contact hole 612 reaching to any of the source/drain
regions 609 is formed, and a barrier metal layer 613 formed of, for
example, Ti or TiN/Ti is formed within the contact hole 612 and on
the surface of the silicon nitride film 611. Furthermore, a Cu film
614 is deposited on the barrier metal layer 613. Then, a Cu wiring
614 is formed by patterning the Cu film 614 (FIG. 19(b)). A
protection insulating film may be further formed on the Cu wiring
614, or a plurality of upper Cu wirings may be formed interposing
an interlayer insulating film between the Cu wiring 614 and the
upper Cu wirings during formation of the protection insulating
film. As shown in FIG. 20, the side wall insulating film 608 formed
of a silicon nitride film prevents the diffusion of copper into the
inside of the wafer 601. Since a coefficient of diffusion of copper
into the silicon nitride film is small, copper atoms and copper
composition remain in the surface of the protection insulating film
608, within the protection insulating film 608 and at the interface
between the protection insulating film 608 and the wafer. For this
reason, it is possible to prevent the diffusion of the copper atoms
and the copper composition almost perfectly.
[0073] In this embodiment, since the foregoing protection
insulating film is formed in the peripheral portion of the
principal plane of the wafer, in which the integrated circuit is
formed, the peripheral portion of the principal plane of the wafer
in which no photoresist is inherently formed is not exposed by
etching when the Cu wiring is formed on the principal portion.
Accordingly, the copper does not diffuse into the chip formation
region of the wafer from this portion. Among the wafer treatment
steps, in a step for forming a side wall insulating film formed of
a silicon nitride film, which is performed before the Cu wiring
formation step, the foregoing silicon nitride film as the
protection insulating film may be used.
[0074] In the present invention, when a part of the wafer treatment
steps is employed, the protection insulating film may be formed in
a step other than the side wall insulating formation step. It is
possible to use any step, for example, the step for forming the
silicon nitride film 611 as shown in FIG. 20(b), as long as it is a
step before the Cu wiring formation step.
[0075] Since the silicon nitride film or the silicon oxide film as
the protection insulating film for preventing the diffusion of the
copper is formed on the peripheral portion, the external side plane
and the rear plane of the wafer, it is possible to prevent the
diffusion of the copper into the semiconductor substrate, so that
the variation of the transistor characteristic, for example, a
threshold, can be controlled. Furthermore, the protection
insulating film can be formed by using a step among the wafer
treatment steps for forming the integrated circuit in the chip
region of the wafer, so that the manufacturing steps can be
simplified.
[0076] While there has been illustrated and described what are
presently considered to be preferred embodiment of the present
invention, it will be understood by those skilled in the art that
various changes and modifications may be made, and equivalents may
be substituted for devices thereof without departing from the true
scope of the invention. In addition, many modifications may be made
to adapt a particular situation or material to the teaching of the
present invention without departing from the central scope thereof.
Therefore, it is intended that this invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention includes all
embodiments falling within the scope of the appended claims.
* * * * *