U.S. patent application number 09/968793 was filed with the patent office on 2003-05-22 for method for fabricating different gate oxide thickness within the same chip.
Invention is credited to Crowder, Scott W., Domenicucci, Anthony Gene, Han, Liang-Kai, Hargrove, Michael John, Ronsheim, Paul Andrew.
Application Number | 20030094660 09/968793 |
Document ID | / |
Family ID | 22869984 |
Filed Date | 2003-05-22 |
United States Patent
Application |
20030094660 |
Kind Code |
A1 |
Crowder, Scott W. ; et
al. |
May 22, 2003 |
Method for fabricating different gate oxide thickness within the
same chip
Abstract
A semiconductor structure having silicon dioxide layers of
different thicknesses is fabricated by forming a sacrificial
silicon dioxide layer on the surface of a substrate; implanting
nitrogen ions through the sacrificial silicon dioxide layer into
first areas of the semiconductor substrate; implanting chlorine
and/or bromine ions through the sacrificial silicon dioxide layer
into second areas of the semiconductor substrate where silicon
dioxide having the highest thickness is to be formed; removing the
sacrificial silicon dioxide layer; and then growing a layer of
silicon dioxide on the surface of the semiconductor substrate. The
growth rate of the silicon dioxide will be faster in the areas
containing the chlorine and/or bromine ions and therefore the
silicon dioxide layer will be thicker in those regions as compared
to the silicon dioxide layer in the regions not containing the
chlorine and/or bromine ions. The growth rate of the silicon
dioxide will be slower in the areas containing the nitrogen ions
and therefore the silicon dioxide layer will be thinner in those
regions as compared to the silicon dioxide layer in the regions not
containing the nitrogen ions. Also provided are structures obtained
by the above process.
Inventors: |
Crowder, Scott W.;
(Ossining, NY) ; Domenicucci, Anthony Gene;
(Hopewell Junction, NY) ; Han, Liang-Kai;
(Fishkill, NY) ; Hargrove, Michael John; (Clinton
Corners, NY) ; Ronsheim, Paul Andrew; (Hopewell
Junction, NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION
DEPT. 18G
BLDG. 300-482
2070 ROUTE 52
HOPEWELL JUNCTION
NY
12533
US
|
Family ID: |
22869984 |
Appl. No.: |
09/968793 |
Filed: |
October 3, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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|
09968793 |
Oct 3, 2001 |
|
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|
09231617 |
Jan 14, 1999 |
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6335262 |
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Current U.S.
Class: |
257/391 ;
257/E21.285; 257/E21.625 |
Current CPC
Class: |
H01L 21/823462 20130101;
Y10S 148/116 20130101; Y10S 438/981 20130101; Y10S 148/163
20130101; H01L 21/31662 20130101 |
Class at
Publication: |
257/391 |
International
Class: |
H01L 029/94 |
Claims
What is claimed is:
1. A method for simultaneously fabricating different oxide
thicknesses on the same semiconductor substrate which comprises:
forming a sacrificial silicon dioxide layer on the surface of a
semiconductor substrate; implanting nitrogen ions through the
sacrificial silicon oxide layer into at least one first area of the
semiconductor substrate to be oxidized while masking the other
areas of the semiconductor substrate; and wherein the nitrogen ions
retard the oxidation rate of the semiconductor substrate;
implanting second ions selected from the group consisting of
chlorine ions, bromine ions, and mixtures thereof through the
sacrificial silicon dioxide layer into at least one second area of
the semiconductor substrate to be oxidized while masking the other
areas of the semiconductor substrate; and wherein the second ions
increase the oxidation rate of the semiconductor substrate;
removing the sacrificial silicon dioxide layer; and then growing a
layer of silicon dioxide on the surface of the semiconductor
substrate wherein the growth rate of the silicon dioxide will be
faster in the second area containing the second ions; and wherein
the growth rate of the silicon dioxide will be slower in the first
areas containing the nitrogen ions; and wherein the silicon dioxide
layer will be thicker in the second areas compared to the silicon
dioxide in the first areas not containing the second ions; and
wherein the silicon dioxide layer will be thinner in the first
areas compared to the silicon dioxide in the areas not containing
the nitrogen ions.
2. The method of claim 1 wherein nitrogen ions are implanted prior
to implanting second ions.
3. The method of claim 1 wherein second ions are implanted prior to
implanting nitrogen ions.
4. The method of claim 1 wherein the dosage of the nitrogen ions is
about 2.times.10.sup.13 to about 2.times.10.sup.15
atoms/cm.sup.2.
5. The method of claim 1 wherein the nitrogen ions are implanted at
an energy of about 1 to about 15 keV.
6. The method of claim 1 wherein the substrate is silicon or SOI
substrate.
7. The method of claim 1 wherein the second ions are chlorine
ions.
8. The method of claim 1 wherein the dosage of the second ions is
about 2.times.10.sup.13 to about 2.times.10.sup.15
atoms/cm.sup.2.
9. The method of claim 1 wherein the second ions are implanted at
an energy of about 1 to about 15 keV.
10. The method of claim 1 wherein at least one of the nitrogen ions
and second ions are implanted in at least two different areas of at
least two different dosages.
11. A semiconductor device obtained by the process of claim 1.
12. A semiconductor structure comprising: a semiconductor substrate
containing selected first areas with implanted nitrogen ions;
selected second areas with second implanted ions selected from the
group consisting of chlorine, bromine, and mixtures thereof; a
silicon dioxide layer of differing thickness wherein the dioxide
layer above the portion of the substrate having the second
implanted ion is thicker than the thickness of the silicon dioxide
above the first areas.
13. The semiconductor structure of claim 12 wherein the dosage of
the nitrogen ions is about 2.times.10.sup.13 to about
2.times.10.sup.15 atoms/cm.sup.2.
14. The semiconductor structure of claim 12 wherein the dosage of
the second ions is about 2.times.10.sup.13 to about
2.times.10.sup.15 atoms/c.sup.2.
15. The semiconductor structure of claim 12 wherein the second ions
are chlorine.
16. The semiconductor structure of claim 12 wherein the substrate
is silicon or SOI substrate.
17. The semiconductor structure of claim 12 which further includes
silicon dioxide above areas of the semiconductor substrate that are
non-implanted areas.
18. The semiconductor structure of claim 12 wherein the silicon
dioxide layer above the portion of the substrate having the
nitrogen implanted ion is thinner than the thickness of the silicon
dioxide above the areas not having the nitrogen implanted ions.
19. The semiconductor structure of claim 12 wherein the silicon
dioxide layer above the portion of the substrate having the
chlorine or bromine ion is thicker than the thickness of the
silicon dioxide above the areas not having the chlorine or bromine
implanted ions.
Description
TECHNICAL FIELD
[0001] The present invention is concerned with a method for
simultaneously fabricating different oxide thicknesses on the same
semiconductor substrate. The present invention is especially
advantageous when fabricating CMOS semiconductor devices and
especially for providing gate oxide insulators of different
thicknesses.
BACKGROUND OF INVENTION
[0002] An increasing demand exists for providing semiconductor
chips having gate oxide layers of varying thicknesses. In fact, the
gate oxide thickness is a major concern in terms of reliability
considerations when providing integrated circuit devices containing
transistors and other circuit elements that operate at differing
voltage levels. By way of example, a relatively thin gate oxide of
about 40 .ANG. is typically grown in a conventional 1.8 volt, 0.25
micron process while a relatively thick gate oxide of about 70
.ANG. is grown in a conventional 3.3 volt, 0.5 micron process.
[0003] Device scaling trends have led to low voltage operation with
relatively thin gate oxides; whereas, some circuit applications
still require a relatively thick gate oxide, such as
driver/receiver circuitry at the chip I/O, and some analog output
devices. The thick oxide is necessary for the high voltage devices
in order to ensure reliability, while the thin gate oxide is
desirable for the relatively fast logic devices that use low
voltages at the gate. Use of relatively thick oxide for the lower
voltage transistors cause poor device performance and significantly
decrease the speed.
[0004] Moreover, with the trend of trying to put as many different
circuits as possible in the same chip to achieve more functionality
and/or improved performance (such as Merged logic-DRAM, embedded
NVM microcontrols), there are even more different possible
combinations for different parts of circuits in the same chip to
have different gate oxide thickness to achieve the optimized
performance and reliability in the system level.
[0005] One prior method of forming different gate oxide thickness
on the same substrate involves multiple masking, strip, and oxide
formation steps. However, such approach typically significantly
increases the overall manufacturing cost and degrades the
reliability as well as yield due to the potential resist residues
contamination. Besides, the oxide thickness control is more
difficult because the thick oxide layer results from the
combination of multiple oxide formation cycles.
[0006] Another method for providing dual gate oxide thicknesses
employs nitrogen implant for retarding the oxidation rate on the
thin gate oxide device component, while permitting a thicker oxide
to grow where the nitrogen implant has been blocked. However, the
use of nitrogen implant alone has resulted in certain problems. For
instance, implanting nitrogen at high doses introduces beam damage
in the channel region of the device. This damage in turn results in
changes in the channel impurity distributions as well as
introducing silicon defects which can degrade sub-Vt leakage (off
current), gate oxide breakdown voltage as well as reliability.
[0007] Low dose of nitrogen implant for thin oxide with n-type
dopant (such as As) co-implant for thick oxide is another approach
proposed to achieve multi-gate oxide thickness on the wafer. The
problem with this process is that it depends on the dopant to
enhance the oxidation rate which limits the freedom of usage
because the dopant at the same time determines the substrate
concentration which is a very important parameter in the device
structure.
[0008] It has also been suggested to implant relatively high
concentrations of fluoride ion into selected areas of a
semiconductor substrate in order to increase or enhance oxide
growth in those areas. The relatively high fluoride ion
concentrations promote higher oxidation rates primarily through
silicon damage. Moreover, use of fluoride ions are problematic
since such are not compatible, for instance, with boron-doped PFET
gates, as currently used in advanced logic CMOS. In particular,
fluorine promotes penetration or diffusion of boron ions into the
gate oxide. Accordingly, using fluoride ions as discussed in U.S.
Pat. No. 5,480,828 is not especially suitable for advanced CMOS
from a practical application viewpoint.
[0009] More recently, an improved process for simultaneously
fabricating different oxide thicknesses on the same semiconductor
substrate employs implanting chlorine and/or bromine ions into
areas of a semiconductor substrate where silicon oxide having the
highest thicknesses is to be formed. This improved fabrication
technique is the subject matter of U.S. patent application Ser. No.
09/090,735 filed Jun. 4, 1998, entitled "Method for Fabricating
Different Gate Oxide Thicknesses within the Same Chip" to Ronsheim
and assigned to International Business Machines Corporation, the
assignee of this application, disclosure of which is incorporated
herein by reference.
[0010] Although this latter process represents a significant
improvement, there still exists room for improvement.
SUMMARY OF INVENTION
[0011] The present invention provides a process for simultaneously
fabricating different oxide thicknesses on the same semiconductor
substrate that overcome problems of prior suggested techniques.
[0012] The present invention makes it possible to increase or
extend the range of differences in thicknesses between thicker and
thinner silicon dioxide layers. According to the present invention,
at least two different ions are used, one being nitrogen and the
other being chlorine and/or bromine. The nitrogen is used in those
areas where a slower or reduced oxidation rate is desired, while
chlorine and/or bromine is used in those areas where a faster
oxidation rate is desired. By employing the chlorine and bromine,
the dosage of the nitrogen used can be lower than that required by
prior art processes. This in turn, significantly reduces, if not
entirely eliminates, problems discussed above due to nitrogen
doping.
[0013] According to the present invention, chlorine and/or bromine
implants are employed to affect the thick oxide device regions,
which are the non-critical gate dielectrics instead of the
relatively thin gate oxide regions. The thin gate oxide uniformity
is critical especially as the oxides are scaled to 25 .ANG. and
less. Accordingly, controlling the thickness of thin gate oxide
regions is achieved according to the present invention by employing
nitrogen implants.
[0014] More particularly, the present invention is concerned with a
method for simultaneously fabricating different oxide thicknesses
on the same semiconductor substrate. The method of the present
invention comprises forming a sacrificial layer on the surface of
the semiconductor. Chlorine and/or bromine ions are implanted
through the sacrificial layer into areas of the semiconductor
substrate where silicon dioxide having the higher thicknesses is to
be formed. It is preferred according to the present invention that
the chlorine and/or bromine ions be implanted at relatively low
energy levels and modest dosage levels. In particular, the chlorine
and/or bromine ions are typically implanted at a dose of about
2.times.10.sup.13 to 2.times.10.sup.15 atoms/cm.sup.2 and at an
energy of about 1 to about 15 keV.
[0015] Nitrogen ions are implanted through the sacrificial layer
into areas of the semiconductor substrate where silicon dioxide
having the thinner thicknesses is to be formed. It is preferred
according to the present invention that the nitrogen ions be
implanted at relatively low energy levels and modest dosage levels.
In particular, the nitrogen ions are typically implanted at a dose
of about 2.times.10.sup.13 to about 2.times.10.sup.15
atoms/cm.sup.2 and an energy of about 1 to about 15 keV.
[0016] The particular sequence of the implanting steps is not
crucial and can be carried out in any order.
[0017] Moreover, according to the present invention, when more than
two oxide thicknesses are desired, more than one nitrogen and/or
chlorine and/or bromine implantation step can be employed with
different dosages of nitrogen and/or chlorine and/or bromine. This
makes it possible to tailor and fine tune many silicon dioxide
thicknesses as is desired on the substrate. Furthermore, if
desired, areas of the substrate where silicon dioxide is to be
formed can be left undoped to achieve one more different gate oxide
thickness.
[0018] After the ions are implanted, the sacrificial silicon
dioxide layer is removed and a layer of silicon dioxide is then
grown by thermal oxidation on the surface of the semiconductor
substrate. The growth rate of the silicon dioxide in the regions
containing the chlorine and/or bromine implanted ions is greater
than the growth rate in regions not containing the implanted
chlorine and/or bromine ions and therefore the silicon dioxide
layer will be thicker in those areas compared to the silicon
dioxide layer in the areas not containing the implanted chlorine
and/or bromine ions.
[0019] Similarly, the growth rate of the silicon dioxide in the
regions containing the nitrogen implanted ions is less than the
growth rate in regions not containing the implanted nitrogen ions
and therefore the silicon dioxide layer will be thinner in those
areas compared to the silicon dioxide layer in the areas not
containing the implanted nitrogen ions.
[0020] In addition, the present invention is concerned with a
semiconductor substrate having different oxide thicknesses thereon
obtained by the above method.
[0021] Also, the present invention is concerned with a
semiconductor substrate having nitrogen doping in selected areas
thereof, chlorine and/or bromine doping in other selected areas
thereof and thermally grown silicon oxide layers on the substrate
having different thicknesses, wherein the silicon dioxide layer in
the regions located above those areas having the chlorine and/or
bromine doping is thicker than the silicon dioxide layer in areas
above the semiconductor substrate that do not include the chlorine
and/or bromine doping, and wherein the silicon dioxide layer in the
regions located above those areas having the nitrogen doping is
thinner than the silicon dioxide layer in areas above the
semiconductor substrate that do not include the nitrogen
doping.
[0022] Still other objects and advantages of the present invention
will become readily apparent by those skilled in the art from the
following detailed description, wherein it is shown and described
only the preferred embodiments of the invention, simply by way of
illustration of the best mode contemplated of carrying out the
invention. As will be realized the invention is capable of other
and different embodiments, and its several details are capable of
modifications in various obvious respects, without departing from
the invention. Accordingly, the description is to be regarded as
illustrative in nature and not as restrictive.
SUMMARY OF DRAWINGS
[0023] FIG. 1 is a schematic diagram of a semiconductor structure
during the ion implantation of chlorine and/or bromine stage of
fabrication according to the process of the present invention.
[0024] FIG. 2 is a schematic diagram of a semiconductor structure
during the nitrogen ion implantation stage of fabrication according
to the process of the present invention.
[0025] FIG. 3 is a schematic diagram of a semiconductor structure
at the fabrication stage of removing a sacrificial layer according
to the process of the present invention.
[0026] FIG. 4 is a schematic diagram of a semiconductor structure
at the fabrication stage of growing a layer of silicon oxide on the
semiconductor substrate.
BEST AND VARIOUS MODES FOR CARRYING OUT INVENTION
[0027] In order to facilitate an understanding of the present
invention, reference is made to the figures which illustrate a
portion of a partially fabricated integrated circuit. In
particular, see FIG. 1 wherein is shown a semiconductor substrate
1, which is typically monocrystalline silicon or a SOI substrate
(silicon on insulator). Shallow trench isolation regions 2 are
formed as is conventional in the art. A layer of sacrificial
silicon dioxide 3 is grown on the surface of the semiconductor
substrate, typically to a thickness of about 25 to about 120 .ANG.,
with 60 .ANG. being an example. The sacrificial silicon dioxide
layer is provided for cleaning the active silicon regions of
residual nitride from the previous isolation process as well as for
removing the near surface silicon which may have been damaged or
contaminated in the previous processing.
[0028] By way of illustration only, the discussion that follows
refers to a sequence whereby chlorine and/or bromine doping occurs
first and then nitrogen doping. It is understood, of course, that
the sequence can be reversed. Likewise, if more than one dosage of
nitrogen and/or chlorine and/or bromine is used, any sequence of
the various doping steps can be employed.
[0029] A photoresist 6 is applied over the sacrificial silicon
dioxide layer and is patterned by conventional lithographic
technique so as to selectively open regions in the resist where a
thicker gate oxide is desired.
[0030] Chlorine and/or bromine ions, and preferably chlorine ions,
are implanted through the sacrificial silicon dioxide layer into
the semiconductor substrate in the regions not covered by the
photoresist. The ions are implanted at a dosage of about
2.times.10.sup.13 to about 2.times.10.sup.15 atoms/cm.sup.2 and
preferably about 5.times.10.sup.13 to about 1.times.10.sup.15
atoms/cm.sup.2 and at an energy from about 1 to about 15 keV
depending upon the thickness and preferably at an energy of about 2
to about 10 keV of the sacrificial oxide. In particular, the
implant energy needed to position the implant distribution peak
below the oxide/substrate interface is directly proportional to the
thickness of the sacrificial oxide layer.
[0031] For example, a 60 .ANG. sacrificial oxide would require a 5
keV implant; whereas, a 100 .ANG. sacrificial oxide would require
about 5-10 kev energy. Calculations of the mean range of the
implanted ions are shown in the following table.
1 Implant energy Chlorine range Bromine range (keV) (A) (A) 2 51 47
5 93 79 10 155 118 15 206 154
[0032] The chlorine and/or bromine will enhance the subsequent
thermal oxidation rate as well as immobilizing any sodium and
lithium ion contamination that might be present in the gate.
Moreover, in view of the relatively narrow implant distribution of
chlorine and bromine, implant damage from such is confined to the
regions of the subsequent thick oxide growth and the damaged
silicon will be consumed in the gate oxidation process.
[0033] As illustrated in FIG. 2, the remaining photoresist 6 is
next stripped by dissolution in a suitable solvent, and a
photoresist 7 is applied over the sacrificial silicon dioxide layer
and is patterned by conventional lithographic technique so as to
mask the thicker gate oxide device areas (i.e. where doped with
chlorine and/or bromine) and open regions in the resist where a
thinner gate oxide is desired.
[0034] Nitrogen ions are implanted through the sacrificial silicon
dioxide layer into the semiconductor substrate in the regions not
covered by the photoresist. The ions are implanted at a dosage of
about 2.times.10.sup.13 to about 2.times.10.sup.15 atoms/cm.sup.2
and preferably about 5.times.10.sup.13 to about 1.times.10.sup.15
atoms/cm.sup.2 and at an energy from about 1 to about 15 keV
depending upon the thickness and preferably at an energy of about 2
to about 10 keV of the sacrificial oxide. In particular, the
implant energy needed to position the implant distribution peak
below the oxide/substrate interface is directly proportional to the
thickness of the sacrificial oxide layer.
[0035] For example, a 60 .ANG. sacrificial oxide would require a 2
to 5 keV implant of nitrogen; whereas, a 100 .ANG. sacrificial
oxide would require about 10 keV energy. Calculations of the mean
range of the implanted ions are shown in the following table:
2 Implant energy Nitrogen range (KeV) (A) 2 78 5 161 10 295 15
438
[0036] The nitrogen retards the subsequent thermal oxidation
rate.
[0037] As illustrated in FIG. 3, the remaining photoresist 7 is
next stripped by dissolution in a suitable solvent. Then, the
sacrificial silicon dioxide layer 3 is removed such as by chemical
etching for example in a HF solution.
[0038] As shown in FIG. 4, a layer of silicon dioxide is then grown
on the substrate by thermal oxidation by heating the substrate to a
temperature of from about 800.degree. C. to about 1000.degree. C.
and subjecting the substrate to an oxidizing ambient such as wet or
dry O.sub.2. Following oxidation, the gate oxide layer 4 grown on
the chlorine and/or bromine ion implanted portion of the substrate
will be thicker than the gate oxide layer 5 of the nitrogen
implanted portion of the substrate. This is due to the fact that
the chlorine and bromine ions cause a significant increase in the
growth rate of the gate oxide layer grown on the ion implanted
portion, while the nitrogen causes a decrease in the growth rate of
the oxide. Thus, gate oxide layers of varying thickness are
simultaneously formed on a single substrate.
[0039] For example, implanting of chlorine ion at a dose of
2.times.10.sup.15 chlorine atoms/cm.sup.2 at an energy level of 10
keV provided an increase of about 2.2 times the thickness of the
oxide where nitrogen ions are implanted at a dose of about
6.times.10.sup.14 atoms/cm.sup.2 at an energy level of 5 keV.
[0040] The gate oxide for the N-implanted portions was about 18
.ANG. and that for the Cl-implanted portions was about 40 .ANG. as
determined by TEM analysis. The gate oxide grown on the portions
without any implants was about 25 .ANG..
[0041] Next if desired, a deposited nitride layer (not shown) can
be provided over the oxide or a nitridization of the oxide may be
performed using the well-known nitridization by heating in NO or
N.sub.2O.
[0042] Next the device can be subjected to conventional techniques
to provide CMOS structures conventional in the art such as NMOS and
PMOS devices. For example, a layer of polysilicon can be deposited
over the gate silicon dioxide layers for instance to a thickness of
about 1000 to about 2000 .ANG. and then delineated to provide the
desired gate regions.
[0043] Next, source and drain regions can be provided where
necessary and a dielectric layer composed of, for example,
borophosphosilicate glass and/or silicon dioxide over the
semiconductor device structures can be provided. Openings are then
made through the dielectric layer to the source and drain regions
within the semiconductor substrate where contacts are desired. A
metal layer such as aluminum is deposited to fill the contact
openings and patterned. Finally, a passivation layer can be
provided over the integrated circuit.
[0044] The foregoing description of the invention illustrates and
describes the present invention. Additionally, the disclosure shows
and describes only the preferred embodiments of the invention but,
as mentioned above, it is to be understood that the invention is
capable of use in various other combinations, modifications, and
environments and is capable of changes or modifications within the
scope of the inventive concept as expressed herein, commensurate
with the above teachings and/or the skill or knowledge of the
relevant art. The embodiments described hereinabove are further
intended to explain best modes known of practicing the invention
and to enable others skilled in the art to utilize the invention in
such, or other, embodiments and with the various modifications
required by the particular applications or uses of the invention.
Accordingly, the description is not intended to limit the invention
to the form disclosed herein. Also, it is intended that the
appended claims be construed to include alternative
embodiments.
* * * * *