U.S. patent application number 09/932636 was filed with the patent office on 2003-02-20 for thermal bus design to cool a microelectronic die.
This patent application is currently assigned to Intel Corporation. Invention is credited to Chiu, Chia-Pin.
Application Number | 20030035269 09/932636 |
Document ID | / |
Family ID | 25462635 |
Filed Date | 2003-02-20 |
United States Patent
Application |
20030035269 |
Kind Code |
A1 |
Chiu, Chia-Pin |
February 20, 2003 |
THERMAL BUS DESIGN TO COOL A MICROELECTRONIC DIE
Abstract
A novel thermal bus is shown that more effectively transmits
heat away from a die of an IC. The innovative thermal bus is
capable of transmitting heat to other heat dissipating devices such
as heat sinks, which eventually transmit the heat out to ambient.
One aspect of the thermal bus leading to increased performance
includes an added path for conducting heat in addition to the path
through the backside of the die. Another aspect of the thermal bus
leading to increased performance includes coupling the thermal bus
to the active side of the die to more directly transmit heat from
the electronic devices that are generating the heat. Local hot
spots are therefore minimized, and the overall average temperature
of the die is reduced, which allows improved performance of the
microelectronic chip, such as operating at a higher frequency for a
given upper threshold temperature.
Inventors: |
Chiu, Chia-Pin; (Tempe,
AZ) |
Correspondence
Address: |
Schwegman, Lundberg
Woessner & Kluth, P.A.
P.O. Box 2938
Minneapolis
MN
55402
US
|
Assignee: |
Intel Corporation
|
Family ID: |
25462635 |
Appl. No.: |
09/932636 |
Filed: |
August 17, 2001 |
Current U.S.
Class: |
361/704 ;
165/80.3; 257/713; 257/E23.079; 257/E23.102 |
Current CPC
Class: |
H01L 2224/16225
20130101; H01L 23/50 20130101; H01L 2224/32225 20130101; H01L
2224/73253 20130101; H01L 2924/15311 20130101; H01L 23/367
20130101; H01L 2924/01037 20130101; H01L 2924/15192 20130101; H01L
2224/16 20130101; H01L 2924/16152 20130101; H01L 2224/73204
20130101; H01L 2924/16152 20130101; H01L 2224/73253 20130101 |
Class at
Publication: |
361/704 ;
165/80.3; 257/713 |
International
Class: |
H05K 007/20 |
Claims
We claim:
1. A thermal bus, comprising: a heat conducting layer having a
first portion and a second portion, the first portion adapted to
mount between a package substrate and a side of the die adjacent to
the package substrate; a conducting member having a first side and
a second side, the first side being coupled to the second portion
of the heat conducting layer and the second side being adapted to
couple to a heat transfer device; wherein heat is conducted from
the first portion, through the heat conducting layer to the second
portion, and into the conducting member.
2. The thermal bus of claim 1, wherein the heat conducting layer
includes copper.
3. The thermal bus of claim 1, wherein the conducting member
includes copper.
4. The thermal bus of claim 1, wherein the conducting member is
soldered to the heat conducting layer.
5. An Integrated Circuit (IC) package, comprising: a package
substrate; a microelectronic die having an active side and a
backside, the microelectronic die mounted to the package substrate
with the active side oriented toward the package substrate; a heat
transfer device; and a thermally conductive channel formed on the
package substrate, including: a first portion thermally coupled
between the package substrate and the active side of the die; and a
second portion laterally spaced from the die and in thermal
communication with the heat transfer device.
6. The Integrated Circuit (IC) package of claim 5, wherein the heat
transfer device is in thermal communication with the backside of
the microelectronic die.
7. The Integrated Circuit (IC) package of claim 5, wherein the
thermally conductive channel includes copper.
8. The Integrated Circuit (IC) package of claim 5, further
comprising a thermal interface material located between the second
portion of the thermally conductive channel and the heat transfer
device.
9. The Integrated Circuit (IC) package of claim 5, wherein the
thermally conductive channel is electrically conductive, the
conductive channel functioning as a ground between the heat
transfer device and the package substrate.
10. The Integrated Circuit (IC) package of claim 5, wherein the
thermally conductive channel includes: a heat conducting layer
having a first portion and a second portion, the first portion
adapted to mount between the active side of the microelectronic die
and the package substrate; and a conducting member coupled to the
second portion of the heat conducting layer, wherein heat is
conducted from the first portion, through the heat conducting layer
to the second portion, and into the conducting member.
11. The Integrated Circuit (IC) package of claim 10, wherein the
thermally conductive contact is soldered to the thermally
conductive layer.
12. An information handling system, comprising: a memory device; a
system bus coupled to the memory device; a processor chip package
coupled the system bus, the processor chip package comprising: a
package substrate; a microelectronic die having an active side and
a backside, the microelectronic die mounted to the package
substrate with the active side oriented toward the package
substrate; a thermally conductive package cover located over the
backside of the die; and a thermally conductive channel formed on
the package substrate, including: a first portion thermally coupled
between the package substrate and the active side of the die; and a
second portion laterally spaced from the die and in thermal
communication with the thermally conductive package cover.
13. The information handling system of claim 12, wherein the
thermally conductive package cover is in thermal communication with
the backside of the microelectronic die.
14. The information handling system of claim 12, wherein the
thermally conductive channel includes copper.
15. The information handling system of claim 12, further comprising
a thermal interface material located between the second portion of
the thermally conductive channel and the thermally conductive
package cover.
16. The information handling system of claim 13, further comprising
a thermal interface material located between the backside of the
microelectronic die and the thermally conductive package cover.
17. The information handling system of claim 12, wherein the
thermally conductive channel includes: a heat conducting layer
having a first portion and a second portion, the first portion
adapted to mount between the active side of the microelectronic die
and the package substrate; and a conducting member coupled to the
second portion of the heat conducting layer, wherein heat is
conducted from the first portion, through the heat conducting layer
to the second portion, and into the conducting member.
18. The information handling system of claim 17, wherein the
thermally conductive contact is soldered to the thermally
conductive layer.
19. A method of cooling an Integrated Circuit (IC) die, comprising:
conducting heat from between a package substrate and a side of the
die adjacent to the package substrate into a heat conducting
channel; conducting heat along the heat conducting channel to a
location laterally spaced from the die; and conducting heat from
the laterally spaced location to a thermally conductive package
cover.
20. The method of claim 19 further comprising conducting heat from
the thermally conducting package cover to a heat sink device.
21. The method of claim 19 wherein: conducting heat along the heat
conducting channel to a location laterally spaced from the die
includes conducting heat through a heat conducting layer; and
conducting heat along the heat conducting channel from the
laterally spaced location to a thermally conductive package cover
includes conducting heat from the heat conducting layer through a
conducting member.
22. The method of claim 19 wherein conducting heat along the heat
conducting channel from the laterally spaced location to a
thermally conductive package cover includes conducting heat through
a thermal interface material between the heat conducting channel
and the thermally conductive package cover.
23. A method of manufacturing an Integrated Circuit (IC) package,
comprising: forming a heat conducting channel on a package
substrate; mounting a microelectronic die with an active side
oriented toward the package substrate with a portion of the active
side of the die coupled to a first portion of the heat conducting
channel, leaving a second portion of the heat conducting channel
laterally accessible; and positioning a thermally conductive
package cover over the die in thermal communication with the second
portion of the heat conducting channel.
24. The method of claim 23, wherein forming a heat conducting
channel on a package substrate includes forming a copper containing
channel on the package substrate.
25. The method of claim 23, wherein forming a heat conducting
channel on a package substrate includes: attaching a heat
conducting layer to the package substrate, the heat conducting
layer having a first portion and a second portion; and attaching a
conducting member to the second portion of the heat conducting
layer.
26. The method of claim 25, wherein attaching a conducting member
to the second portion of the heat conducting layer includes
soldering a conducting member to the second portion of the heat
conducting layer.
27. The method of claim 23, wherein positioning a thermally
conductive package cover over the die includes positioning a
thermally conductive package cover over the die in thermal
communication with a backside of the die.
28. The method of claim 25, wherein positioning a thermally
conductive package cover over the die includes; coupling a first
thermal interface material layer to the backside of the die;
coupling a second thermal interface material layer to the
conducting member; and positioning the thermally conductive package
cover over the die and the conducting member wherein the first and
second thermal interface materials contact the thermally conductive
package cover.`
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates generally to the field of heat
transfer and, in particular, the present invention relates to
thermal management of microelectronic electronic devices.
BACKGROUND
[0002] In one embodiment, the present invention is used to transfer
heat generated by electronic devices or groups of devices, such as
transistors, as are commonly included on integrated circuit (IC)
chips. A brief discussion of some electronic systems using IC's,
such as personal computers or lower level computer components, is
included below to show some possible areas of application for the
present invention.
[0003] IC's are typically formed on microelectronic dies and
assembled into microelectronic packages by physically and
electrically coupling them to a package substrate made of organic
or ceramic material. One or more microelectronic packages can be
physically and electrically coupled to a printed circuit board
(PCB) to form an "electronic assembly". The "electronic assembly"
can be part of an "electronic system". An "electronic system" is
broadly defined herein as any product comprising an "electronic
assembly". Examples of electronic systems include computers (e.g.,
desktop, laptop, hand-held, server, etc.), wireless communications
devices (e.g., cellular phones, cordless phones, pagers, etc.),
computer-related peripherals (e.g., printers, scanners, monitors,
etc.), entertainment devices (e.g., televisions, radios, stereos,
tape and compact disc players, video cassette recorders, MP3
(Motion Picture Experts Group, Audio Layer 3) players, etc.), and
the like.
[0004] An IC is fabricated on a microelectronic die that may
comprise a number of metal layers selectively patterned to provide
metal interconnect lines (referred to herein as "traces"), and one
or more electronic devices attached in or on one or more surfaces
of the microelectronic die. The electronic device or devices are
functionally connected to other elements of an electronic system
through a hierarchy of electrically conductive paths that include
the metal traces. The traces typically carry signals that are
transmitted between the electronic devices, such as transistors, of
the IC. Electronic devices and traces can be configured in an IC to
form processors.
[0005] In the field of electronic systems there is an incessant
competitive pressure among manufacturers to drive the performance
of their equipment up while driving down production costs. This is
particularly true regarding forming electronic devices such as
transistors in IC's, where each new generation of IC must provide
increased performance, particularly in terms of an increased number
of devices and higher clock frequencies, while generally being
smaller or more compact in size. As the density and clock frequency
of IC's increase, they accordingly generate a greater amount of
heat. However, the performance and reliability of IC's are known to
diminish as the temperature to which they are subjected increases,
so it becomes increasingly important to adequately dissipate heat
from IC environments.
[0006] Additionally, specific areas of a die on which an IC is
formed are often more frequently used than other areas of the die.
For example, a floating point unit (FPU) area will typically
generate a higher amount of heat than other areas on the die. These
areas lead to "hot spots" on the die that significantly increase
the local temperature surrounding these hot spots, and also elevate
the overall average temperature of the die.
[0007] FIG. 1 illustrates a cross-sectional representation of a
common configuration microelectronic package 30. Microelectronic
package 30 represents a typical structure that includes a
microelectronic die 40 mounted in "flip-chip" orientation with its
active side 44 facing downward to couple with electrical contacts
or lands on the package substrate 50. Solder balls or bumps 42 make
the electrical connection with the contacts on the package
substrate, while an underfill material 52 maintains a mechanical
bond between the microelectronic die 40 and the package substrate
50. The package substrate 50 can include additional lands 54 and
solder balls 56 on its opposite surface for mating with additional
packaging structure (not shown).
[0008] Die 40 generates its heat from internal structure, including
wiring traces, that is located near its active side 44. However, a
significant portion of the heat is dissipated through its back side
46. Heat that is concentrated within the die is dissipated to a
large surface that is in contact with the die in the form of a
thermally conductive package cover 60. To improve the thermal
conductivity between the die and the package cover 60, a first
thermal interface material (TIM) 70 is often provided between the
die and package cover 60. To further dissipate heat from the
package cover 60, a heat sink 80 optionally having heat fins 82 is
often coupled to the package cover 60. Heat sink 80 dissipates heat
into the ambient environment. A second layer of TIM 75 may be
included between the package cover 60 and the heat sink 80 to
further facilitate the conduction of heat to the heat sink 80 and
out to ambient. Arrows 84 show the conduction of heat from the
microelectronic die 40 out to the heat sink 80, where the heat is
transmitted to ambient.
[0009] FIG. 2 schematically shows the resistance to the flow of
heat generated in the microelectronic package from FIG. 1. The
resistor symbols represent the thermal resistance through the
thickness of each material noted. The shaded circles represent the
interfaces between the various materials. In this schematic, heat
is conducted from a heat generating electronic device, such as a
transistor junction, through the microelectronic die 40 to the
backside 46 of the die, through the first TIM 70, and into the
package cover 60.
[0010] A device 210 is schematically located on the active side 44
of the microelectronic die 40. The die resistance 220 is shown from
the device 210, to the backside 46 of the microelectronic die 40.
The die/TIM interface 230 is between the backside 46 of the die and
the first TIM 70. The first TIM resistance 240 is shown from the
die/TIM interface 230 to the package cover 60, which defines a
TIM/cover interface 250.
[0011] For ease of discussion, any conducting member resistance or
thermal resistance associated with the interfaces is included in
the bulk resistance values. The calculation for total thermal
resistance of a single conduction path with multiple materials in
series is defined as:
R.sub.tot=R.sub.1+R.sub.2. . . +R.sub.n Equation 1:
[0012] where R.sub.1 to R.sub.n represent the thermal resistance
values of the individual materials. A typical thermal resistance
value for bulk silicon is 2.5 C/W and a typical value for a first
TIM is 0.5 C/W. A typical total thermal resistance (R.sub.tot) for
the system in FIG. 2 would therefore be 2.5 C/W+0.5 C/W=3.0 C/W
[0013] With the advent of high performance IC's and their
associated packages, electronic devices have size required more
innovative thermal management to dissipate heat. Increasing speed
and power in processors, for example, generally carry with it a
"cost" of increased heat in the microelectronic die that must be
dissipated. What is needed is a device and method to more
effectively cool microelectronic dies containing IC's such as
processors. What is also needed is a device and method that can
specifically cool local hot spots on a microelectronic die.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 shows a cross section of a common microelectronic
package.
[0015] FIG. 2 shows a thermal resistance schematic diagram of the
microelectronic package from FIG. 1.
[0016] FIG. 3 shows a cross section of a microelectronic package
according to one embodiment of the invention.
[0017] FIG. 4 shows a thermal resistance schematic diagram of the
microelectronic package from FIG. 3.
[0018] FIG. 5 shows a perspective view of a thermal bus according
to one embodiment of the invention.
DETAILED DESCRIPTION
[0019] In the following detailed description of the invention
reference is made to the accompanying drawings which form a part
hereof, and in which are shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized, and structural,
logical, and electrical changes may be made, without departing from
the scope of the present invention. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims.
[0020] The term "active side" as used in this description is
defined as the conventional horizontal, large plane or surface of a
chip or die where electrical devices have typically been
fabricated, regardless of the orientation of the chip or die. The
term "back side" as used in this description is defined as a
conventional horizontal, large plane or surface of a chip or die
that generally does not contain active devices on it's surface. The
term "vertical" refers to a direction perpendicular to the
horizontal as defined above. Prepositions, such as "on", "higher",
"lower", "above" and "below" are defined with respect to the
conventional plane or surface being on the active side of the chip
or die, regardless of the orientation of the chip or die.
[0021] FIG. 3 shows one embodiment of a microelectronic package
300. The microelectronic package 300 includes a microelectronic die
340 mounted in "flip-chip" orientation with its active side 344
facing downward to couple with electrical contacts or lands on the
package substrate 350. Solder balls or bumps 342 make the
electrical connection with the contacts on the package substrate,
while an underfill material 352 maintains a mechanical bond between
the microelectronic die 340 and the package substrate 350. Although
solder balls 342 and underfill 352 are shown connecting the
microelectronic die 340 to the package substrate 350, other
mounting techniques known in the art, such as surface mount
technology, are also contemplated within the scope of the
invention. The present invention is applicable in conjunction with
any mounting technique used to mount the microelectronic die 340
with it's active side 344 against a package substrate 350. The die
shown will typically include bulk silicon, however other
microelectronic materials such as gallium arsenide may also be used
within the scope of the invention.
[0022] The microelectronic package in FIG. 3 also includes a
thermally conductive package cover 360, that is in thermal
communication with a backside 346 of the microelectronic die 340
through a first Thermal Interface Material (TIM) 370. TIMs are
known in the art, and typically consist of a silicone based grease
filled with conductive particles such as aluminum or aluminum
nitride. Other TIMs may include solder. While a thermally
conductive package cover 360 is shown in this embodiment, any of a
number of heat transfer devices could be coupled to the backside of
the microelectronic die 340. The package cover 360 is in thermal
communication with a heat sink 380, the heat sink 380 optionally
having a number of fins 382 to better dissipate heat to ambient.
The package cover 360 is in thermal communication with the heat
sink 380 through a second TIM 375.
[0023] Heat generated by electronic devices such as transistor
junctions located on the active side 344 of the microelectronic die
340 is transmitted by a first conduction path 384 through the
backside 346 of the microelectronic die 340 as indicated by the
conduction path arrows 384. Heat is transmitted along the first
conduction path 384 from a heat generating device, through the bulk
of the microelectronic die 340, through the first TIM 370, and into
the package cover 360. Although in this embodiment, heat is further
transferred from the package cover 360, through the second TIM 375,
into the heat sink 380, and out to ambient, several alternative
methods of cooling the die may be used once the heat is moved to
the package cover 360. Additionally, fans or heat pipes may be used
in combination with the invention to further facilitate heat
transfer away from the microelectronic die 340.
[0024] FIG. 3 further shows a thermal bus 305 partially embedded in
the package substrate 350. The thermal bus 305 in this embodiment
includes a thermally conductive layer 310, the layer having a first
portion 309 and a second portion 311. The first portion 309 is
located between the active side 344 of the die, and the package
substrate 350. The first portion 309 is in thermal communication
with the active side 344 of the die. In this embodiment, the
thermal communication with the active side 344 is facilitated by
conducting heat from the active side 344, through the solder balls
342 and the underfill 352, to the first portion 309, which is in
direct contact with the solder balls 342 and underfill 352. The
second portion 311 is laterally spaced apart from the
microelectronic die 340. This feature is important because it
allows the heat being conducted through the layer 310 to be
transported around the microelectronic die 340 in contrast to
solely transporting the heat through the die as in the prior
art.
[0025] A conducting member 315 is coupled to the second portion 311
of the layer 310. In this embodiment, the conducting member is
soldered to the layer 310 as indicated by solder layer 312. The
conducting member 315 transmits heat from the second portion 311 to
the thermally conductive package cover 360. While a thermally
conductive package cover 360 is shown in this embodiment, any of a
number of heat transfer devices could be coupled to the conducting
member 315. In this embodiment, the conducting member 315 is
coupled to the package cover 360 by a third TIM 320. It should be
noted that the various TIMs in the invention may include a single
composition in each location, or different compositions for each
TIM may be used.
[0026] Using this embodiment, heat can be conducted away from
devices on the active side 344 of the microelectronic die 340 more
directly from the active side of the die in contrast to conducting
through the bulk of the microelectronic die 340 as shown in the
prior art. Using this embodiment, heat can also be conducted
through two different conduction paths in contrast to the single
conduction path described in the prior art. As shown in FIG. 3, a
second conduction path 386 is included in addition to the first
conduction path 384. Although two different conduction paths are
shown in this embodiment, the novel second conduction path 386 may
also be used alone.
[0027] Although the thermal bus 305 shown in FIG. 3 is comprised of
a number of different components that are thermally coupled, the
thermal bus need not contain multiple components such as the
conducting layer 310 and the conducting member 315. An important
functional aspect of the thermal bus 305 is that it conducts heat
away from near the active side 344 of the microelectronic die 340,
around to a lateral side of the microelectronic die 340 instead of
through the microelectronic die 340. Although only a single thermal
bus 305 is shown in this embodiment, a number of thermal busses
could be used to specifically cool a number of hot spots on the
microelectronic die 340.
[0028] FIG. 4 schematically shows the resistance to the flow of
heat generated in the microelectronic package from FIG. 3. The
resistor symbols represent the thermal resistance through the
thickness of each material noted. The shaded circles represent the
interfaces between the various components or materials. The
schematic in FIG. 4 illustrates how heat is conducted along the
first conduction path 384 from FIG. 3, starting at a heat
generating electronic device, such as a transistor junction,
through the microelectronic die 340 to the backside 346 of the die,
through the first TIM 370, and into the package cover 360.
[0029] Similar to the device shown in FIG. 1, FIG. 4 shows a device
210 schematically located on the active side 344 of the
microelectronic die 340. The die resistance 220 is shown from the
device 210, to the backside 346 of the microelectronic die 340. The
die/TIM interface 230 is between the backside 346 of the die and
the first TIM 370. The first TIM resistance 240 is shown from the
die/TIM interface 230 to the package cover 360, which defines a
TIM/cover interface 250. This path of FIG. 4 illustrates the first
conduction path 384 from FIG. 3.
[0030] The schematic in FIG. 4 also illustrates how heat is
conducted along the second conduction path 386 from FIG. 3,
starting at a heat generating electronic device, such as a
transistor junction, through a composite layer of solder bumps 342
and underfill 352, into the conducting layer 310, through the
solder 312, into the conducting member 315, through the third TIM
320, and into the package cover 360.
[0031] A conducting layer/solder-underfill interface 420 is shown
between the composite layer of solder bumps 342 and underfil 352,
and the conducting layer 310. The composite layer resistance 410 is
shown from the device 210, to the conducting layer/solder-underfill
interface 420. A conducting layer/solder interface 440 is between
the conducting layer 310 and the solder 312. The conducting layer
resistance 430 is shown from the conducting layer/solder-underfill
interface 420 to the conducting layer/solder interface 440. A
solder/conducting member interface 460 is between the solder 312
and the conducting member 315. The solder resistance 450 is shown
from the conducting layer/solder interface 440 to the
solder/conducting member interface 460. A conducting member/TIM
interface 480 is between the conducting member 315 and the third
TIM 320. The conducting member resistance 470 is shown from the
solder/conducting member interface 460 to the conducting member/TIM
interface 480. A TIM/cover interface 495 is between the third TIM
320 and the package cover 360. The third TIM resistance 490 is
shown from the conducting member/TIM interface 480 to the TIM/cover
interface 495. This path of FIG. 4 illustrates the second
conduction path 386 from FIG. 3.
[0032] For ease of discussion, any conducting member resistance or
thermal resistance associated with the interfaces is included in
the bulk resistance values. The calculation for total thermal
resistance of dual parallel conduction paths with multiple
materials in series is defined in Equations 2-4.
R.sub.tot=(R.sub.a*R.sub.b)/(R.sub.a+R.sub.b) Equation 2:
R.sub.a=R.sub.1+R.sub.2 Equation 3:
R.sub.b=R.sub.3+R.sub.4+R.sub.5+R.sub.6+R.sub.7 Equation 4:
[0033] where R.sub.a and R.sub.b represent the thermal resistances
of the two conduction paths, and R.sub.1 to R.sub.7 represent the
thermal resistance values of the individual materials.
[0034] Typical thermal resistance values for the materials in
Equation 3 are as follows:
[0035] bulk silicon=2.5 C/W
[0036] first TIM=0.5 C/V
[0037] A typical thermal resistance for R.sub.a would therefore be
2.5 C/W+0.5 C/W=3.0 C/W.
[0038] Typical thermal resistance values for the materials in
Equation 4 are as follows:
[0039] composite layer resistance 410=0.5 C/W
[0040] conducting layer resistance 430=1.25 C/W
[0041] solder resistance 450=0.1 C/W
[0042] conducting member resistance 470=0.08 C/W
[0043] third TIM resistance 490=1.0 C/W
[0044] A typical thermal resistance for R.sub.b would therefore be
0.5 C/W+1.25 C/W+0.1 C/W+0.08 C/W +1.0 C/W=2.93 C/W.
[0045] The total thermal resistance (R.sub.tot) for the system in
FIG. 4 would therefore be (3.0 C/W*2.93 C/W)/(3.0 C/W+2.93
C/W)=1.48 C/W, which is approximately 50% lower than the 3.0 C/W of
the prior art.
[0046] FIG. 5 shows one embodiment of a thermal bus 500. A
conducting layer 502 is shown with a first portion 504 and a second
portion 506. A conducting member 520 is shown coupled to the
conducting layer 502 by a solder layer 510. As previously
discussed, the conducting member may be coupled the conducting
layer 502 by any of several methods, provided the conducting member
520 is in thermal communication with the conducting layer 502. The
configuration used must be capable of conducting heat from the
first portion 504, through the conducting layer 502 to the second
portion 506, and into the conducting member 520 to a top portion
522 of the conducting member. In this embodiment, the conducting
member is shaped in a rectangular form with square cross section
dimensions 524 approximately equal to 0.5 cm. One skilled in the
art will understand that the conducting member may be designed with
any of a number of cross sections, such as a circle, or a
rectangle, or other complex shapes. The conducting layer, likewise,
may be designed in several configurations other than rectangular as
shown in FIG. 5.
[0047] It will also be understood that although this embodiment
shows two components soldered 125. together to form the thermal bus
500, a single component bus could be used, as well as more than two
components provided there is thermal communication between the
components. The two component design is convenient because
manufacturing of the conducting layer 502 within a package
substrate is easily accomplished with minimal added cost. The
conducting member 520 is also easily coupled to the conducting
layer 502 in a manufacturing step that is inexpensive to
produce.
[0048] The thermal bus 500 in this embodiment utilizes copper in
fabricating the conductive layer 502 and the conducting member 520.
However, any thermally conducting material may be used in place of
copper. The copper material used in this embodiment is electrically
conductive in addition to being thermally conductive. The thermal
bus need not be electrically conductive to be within the scope of
this invention, however if an electrically conductive material is
used, the thermal bus may also be used to electrically ground a
device such as a heat sink to a package substrate, thus protecting
the die from electrical damage.
Conclusion
[0049] A novel thermal bus included in an innovative package design
has been shown that more effectively transmits heat away from hot
areas on the die. The innovative thermal bus is capable of
transmitting heat to other heat dissipating devices such as heat
sinks, and eventually transmitting the heat out to ambient. One
aspect of the thermal bus leading to increased performance includes
an added path for conducting heat in addition to the path through
the backside of the die. Another aspect of the thermal bus leading
to increased performance includes coupling the thermal bus to the
active side of the die to more directly transmit heat from the
electronic devices that are generating the heat. Local hot spots
are therefore minimized, and the overall average temperature of the
die is reduced, which allows improved performance of the
microelectronic chip, such as operating at a higher frequency for a
given upper threshold temperature.
[0050] It is to be understood that the above description is
intended to be illustrative, and not restrictive. Many other
embodiments will be apparent to those of skill in the art upon
reviewing the above description. The scope of the invention should,
therefore, be determined with reference to the appended claims,
along with the full scope of equivalents to which such claims are
entitled.
* * * * *