U.S. patent application number 10/252898 was filed with the patent office on 2003-01-30 for semiconductor device and process for production thereof.
Invention is credited to Usami, Tatsuya.
Application Number | 20030020172 10/252898 |
Document ID | / |
Family ID | 18371471 |
Filed Date | 2003-01-30 |
United States Patent
Application |
20030020172 |
Kind Code |
A1 |
Usami, Tatsuya |
January 30, 2003 |
Semiconductor device and process for production thereof
Abstract
The present invention provides a semiconductor device
comprising: a semiconductor substrate having semiconductor
elements, and a plurality of wirings formed on the semiconductor
substrate via an isolation film, wherein the wirings are formed in
at least one layer level so that the region in which the wirings
are formed is divided into a wiring region of small
wiring-to-wiring distance and a wiring region of large
wiring-to-wiring distance; a first inter-level isolation film is
selectively formed in the wiring region of small wiring-to-wiring
distance and a second inter-level isolation film is formed in the
wiring region of large wiring-to-wiring distance to cover the
wirings; throughholes are formed only in the second inter-level
isolation film; and the dielectric constant of the first
inter-level isolation film is smaller than the dielectric constant
of the second inter-level isolation film. This semiconductor device
has a fine multi-layered wiring structure of high performance and
remarkably improved reliability.
Inventors: |
Usami, Tatsuya; (Tokyo,
JP) |
Correspondence
Address: |
PATENT GROUP
CHOATE, HALL & STEWART
EXCHANGE PLACE, 53 STATE STREET
BOSTON
MA
02109
US
|
Family ID: |
18371471 |
Appl. No.: |
10/252898 |
Filed: |
September 23, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10252898 |
Sep 23, 2002 |
|
|
|
08995298 |
Dec 22, 1997 |
|
|
|
Current U.S.
Class: |
257/773 ;
257/E21.58; 257/E23.144; 257/E23.167 |
Current CPC
Class: |
H01L 23/5222 20130101;
H01L 2924/0002 20130101; H01L 21/76801 20130101; H01L 23/5329
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/773 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 25, 1996 |
JP |
344721/1996 |
Claims
What is claimed is:
1. A semiconductor device comprising: a semiconductor substrate
having semiconductor elements, and a plurality of wirings formed on
the semiconductor substrate via an isolation film, wherein the
wirings are formed in at least one layer level so that the region
in which the wirings are formed is divided into a wiring region of
small wiring-to-wiring distance and a wiring region of large
wiring-to-wiring distance; a first inter-level isolation film is
selectively formed in the wiring region of small wiring-to-wiring
distance and a second inter-level isolation film is formed in the
wiring region of large wiring-to-wiring distance to cover the
wirings; throughholes are formed only in the second inter-level
isolation film; and the dielectric constant of the first
inter-level isolation film is smaller than the dielectric constant
of the second inter-level isolation film.
2. A semiconductor device according to claim 1, comprising: a
semiconductor substrate having semiconductor elements, and a
plurality of wirings formed on the semiconductor substrate via an
isolation film, wherein the wirings are formed in at least one
layer level so that the region in which the wirings are formed is
divided into a wiring region of small wiring-to-wiring distance and
a wiring region of large wiring-to-wiring distance; a first
inter-level isolation film is selectively formed in the wiring
region of small wiring-to-wiring distance, a second inter-level
isolation film is formed in the wiring region of large
wiring-to-wiring distance to cover the wirings; and a third
inter-level isolation film is formed so as to cover the first
inter-level-isolation film and the second inter-level isolation
film; throughholes are formed only in the second inter-level
isolation film and the third inter-level isolation film; and the
dielectric constant of the first inter-level isolation film is
smaller than the dielectric constants of the second inter-level
isolation film and the third inter-level isolation film.
3. A semiconductor device according to claim 1, wherein the
isolation film on the substrate is dented at the surface areas
corresponding to the wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region and the
resulting dents are filled with the first inter-level isolation
film.
4. A semiconductor device according to claim 2, wherein the
isolation film on the substrate is dented at the surface areas
corresponding to the wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region and the
resulting dents are filled with the first inter-level isolation
film.
5. A semiconductor device according to claim 1, wherein the first
inter-level isolation film is constituted by an organic film, an
organic SOG film, a polyimide film, a porous inorganic SOG film
having a density smaller than that of silicon oxide film, or a
porous organic SOG film, and the second inter-level isolation film
is constituted by a silicon oxide film or a silicon oxynitride
film.
6. A semiconductor device according to claim 2, wherein the first
inter-level isolation film is constituted by an organic film, an
organic SOG film, a polyimide film, a porous inorganic SOG film
having a density smaller than that of silicon oxide film, or a
porous organic SOG film, and the second inter-level isolation film
is constituted by a silicon oxide film or a silicon oxynitride
film.
7. A semiconductor device according to claim 1, wherein the wirings
are formed in a plurality of layer levels so that at each layer
level the region in which the wirings are formed is divided into a
wiring region of small wiring-to-wiring distance and a wiring
region of large wiring-to-wiring distance; a first inter-level
isolation film is selectively formed in the wiring region of small
wiring-to-wiring distance and a second inter-level isolation film
is formed in the wiring region of large wiring-to-wiring distance
to cover the wirings; through-holes are formed only in the second
inter-level isolation film; and the dielectric constant of the
first inter-level isolation film is smaller than the dielectric
constant of the second inter-level isolation film.
8. A semiconductor device according to claim 2, wherein the wirings
are formed in a plurality of layer levels so that at each layer
level the region in which the wirings are formed is divided into a
wiring region of small wiring-to-wiring distance and a wiring
region of large wiring-to-wiring distance; a first inter-level
isolation film is selectively formed in the wiring region of small
wiring-to-wiring distance, a second inter-level isolation film is
formed in the wiring region of large wiring-to-wiring distance to
cover the wirings; and a third inter-level isolation film is formed
so as to cover the first inter-level isolation film and the second
inter-level isolation film; throughholes are formed only in the
second inter-level isolation film and the third inter-level
isolation film; and the dielectric constant of the first
inter-level isolation film is smaller than the dielectric constants
of the second inter-level isolation film and the third inter-level
isolation film.
9. A semiconductor device according to claim 7, wherein the
isolation film on the substrate is dented at the surface areas
corresponding to the wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region and the
resulting dents are filled with the first inter-level isolation
film.
10. A semiconductor device according to claim 8, wherein the
isolation film on the substrate is dented at the surface areas
corresponding to the wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region and the
resulting dents are filled with the first inter-level isolation
film.
11. A semiconductor device according to claim 7, wherein the first
inter-level isolation film is constituted by an organic film, an
organic SOG film, a polyimide film, a porous inorganic SOG film
having a density smaller than that of silicon oxide film, or a
porous organic SOG film, and the second inter-level isolation film
is constituted by a silicon oxide film or a silicon oxynitride
film.
12. A semiconductor device according to claim 8, wherein the first
inter-level isolation film is constituted by an organic film, an
organic SOG film, a polyimide film, a porous inorganic SOG film
having a density smaller than that of silicon oxide film, or a
porous organic SOG film, and the second inter-level isolation film
is constituted by a silicon oxide film or a silicon oxynitride
film.
13. A process for producing a semiconductor device, which
comprises: a step of forming a plurality of wirings on a
semiconductor substrate via an isolation film so that the region in
which the wirings are formed is divided into a wiring region of
small wiring-to-wiring distance and a wiring region large
wiring-to-wiring distance, and forming thereon a first inter-level
isolation film so as to cover the wirings and then a protective
isolation film in this order, a step of selectively removing the
first inter-level isolation film and the protective isolation film
present on and in the wiring region of large wiring-to-wiring
distance, a step of forming, by deposition, depositing a second
inter-level isolation film on the whole surface of the resulting
material and then subjecting the second inter-level isolation film
to chemical mechanical polishing with the protective isolation film
used as an etching stopper, to obtain a flat surface, and a step of
forming throughholes only in the second inter-level isolation
film.
14. A process according to claim 13, wherein the dielectric
constant of the first inter-level isolation film is smaller than
the dielectric constant of the second inter-level isolation film
and the protective isolation film is more resistant to the chemical
mechanical polishing than the second inter-level isolation
film.
15. A process according to claim 14, wherein the protective
isolation film is constituted by a silicon nitride film, a silicon
oxynitride film or a silicon carbide film and the second
inter-level isolation film is constituted by a silicon oxide
film.
16. A process for producing a semiconductor device, which
comprises: a step of forming a plurality of wirings on a
semiconductor substrate via an isolation film so that the region in
which the wirings are formed is divided into a wiring region of
small wiring-to-wiring distance and a wiring region large
wiring-to-wiring distance, and forming thereon a second inter-level
isolation film so as to cover the wirings, a step of selectively
removing the second inter-level isolation film present on and in
the wiring region of small wiring-to-wiring distance, a step of
forming, by deposition, depositing a first inter-level isolation
film on the whole surface of the resulting material, and then
subjecting the first inter-level isolation film to chemical
mechanical polishing with the second inter-level isolation film
used as an etching stopper to obtain a flat surface, and a step of
forming throughholes only in the second inter-level isolation
film.
17. A process according to claim 16, wherein the dielectric
constant of the first inter-level isolation film is smaller than
the dielectric constant of the second inter-level isolation film
and the second inter-level isolation film is more resistant to the
chemical mechanical polishing than the first inter-level isolation
film.
18. A process according to claim 17, wherein the first inter-level
isolation film is constituted by an organic film, an organic SOG
film, a polyimide film, a porous inorganic SOG film having a
density smaller than that of silicon oxide film, or a porous
organic SOG film, and the second inter-level isolation film is
constituted by a silicon oxide film or a silicon oxynitride film.
Description
BACKGROUND OF THE INVENTION
[0001] (i) Field of the Invention
[0002] The present invention relates to a semiconductor device and
a process for production thereof. More particularly, the present
invention relates to a fine wiring structure of semiconductor
device and a process for production thereof.
[0003] (ii) Description of the Prior Art
[0004] As the semiconductor elements of semiconductor device become
finer, the semiconductor device must have a finer multi-layered
wiring structure. Currently, in semiconductor devices having such a
multi-layered wiring structure, there is mainly used, as the
inter-level isolation film, a silicon oxide-based isolation film of
relatively small dielectric constant and stable quality so that the
parasitic capacitance between upper-layer wirings and lower-layer
wirings and between adjacent wirings in the same wiring layer level
can be reduced.
[0005] As the semiconductor elements become finer, the wiring width
and wiring-to-wiring distance of lower-layer wirings are made
smaller; however, in order to avoid an increase in wiring
resistance, the wirings in said wiring layer level must have a
certain cross-sectional area. As a result, both the aspect ratio of
a wiring (wiring height/wiring width) and the aspect ratio between
wirings (wiring height/wiring-to-wiring distance) become large.
This invites a significant increase in parasitic capacitance
between wirings, resulting in (1) reduction in transfer speed of
signal and (2) frequent occurrence of cross-talk between wiring
layers (occurrence of signal noise between adjacent wirings).
[0006] Further, if the inter-level isolation film has a large step
in the surface, when an upper wiring layer is formed, it is
impossible to form a fine resist pattern by photolithography owing
to the shortage of focus margin. Even if it is possible, the
above-mentioned difference in surface level gives rise to (1) the
wiring disconnection in upper-layer wirings and (2) remaining of
unetched wiring material at the sites of level difference. Thus,
the inter-level isolation film must have a flat surface.
[0007] In order to avoid the above-mentioned problems appearing in
a fine multi-layered wiring structure, there have been proposed
various techniques of using an inter-level isolation film of low
dielectric constant. An example of such techniques is a technique
disclosed in Japanese Patent Application Laid-Open No. 55913/1996.
This technique is described below with reference to FIG. 7 and FIG.
8, both of which are sectional views showing the key production
steps of the wiring structure used in the technique.
[0008] As shown in FIG. 7(a), a thick isolation film 101 is formed
on a semiconductor substrate. On the thick isolation film 101 are
formed a metal layer 102 and a first dielectric layer 103 in this
order. On the first dielectric layer 103 is provided a resist mask
104. The first dielectric layer 103 is a highly reliable isolation
film made of silicon oxide or the like.
[0009] Then, the first dielectric layer 103 and the metal layer 102
are subjected to reactive ion etching (RIE) by using the resist
mask 104 as an etching mask. Thereafter, the remaining resist mask
104 is removed. Thus, as shown in FIG. 7(b), wirings 105 of small
wiring-to-wiring distance and wirings 106 of large wiring-to-wiring
distance are formed on the thick isolation film 101.
[0010] Next, as shown in FIG. 7(c), a low-dielectric constant
material 107 is applied so as to cover the whole surfaces of the
thick isolation film 101, the wirings 105 of small wiring-to-wiring
distance, the wirings 106 of large wiring-to-wiring distance and
the first dielectric layer 103, followed by levelling of the
surface of the applied low-dielectric constant material. As the
low-dielectric constant material 107, there is used, for example, a
dielectric made of a polymer such as Teflon (trade mark), Parylene
(trade mark) or the like.
[0011] On the whole surface of the low-dielectric constant material
107 is formed a hard oxide mask 108 as a resist layer. Then, the
material 107 and the mask 108 are subjected to selectvie etching.
That is, as shown in FIG. 8(a), the low-dielectric constant
material 107 and the hard oxide mask 108 both in the region of
wirings 106 of large wiring-to-wiring distance are removed and
those in the region of wirings 105 of small wiring-to-wiring
distance are allowed to remain.
[0012] Next, the hard oxide mask 108 on the region of the wirings
105 of small wiring-to-wiring distance is removed. As shown in FIG.
8(b), the low-dielectric constant material 107 is etched back and
removed down to a level lower than the upper surface of the first
dielectric layer 103 by dry etching. In that case, the first
dielectric layer 103 functions as an etching stopper for the
low-dielectric constant material 107. Preferably, the
low-dielectric constant material 107 is not etched down to a level
lower than the top of the wirings 105 of small wiring-to-wiring
distance.
[0013] Next, as shown in FIG. 8(b), a second dielectric layer 109
is formed by deposition on the whole surface of the resulting
material, that is, so as to cover the wirings 106 of large
wiring-to-wiring distance, the first dielectric layer 103 and the
etched-back low-dielectric constant material 107, then the surface
of the second dielectric layer 109 is leveled. The second
dielectric layer 109 is an isolation film made of silicon oxide or
the like.
[0014] As above, on the thick isolation film 101 formed on a
semiconductor substrate are formed lower-layer wirings and
inter-level isolation films. In that case, a highly reliable
isolation film made of silicon oxide or the like is formed in the
region of large wiring-to-wiring distance, and a low-dielectric
constant material is filled in the region of small wiring-to-wiring
distance.
[0015] In forming a multi-layered wiring structure (this is not
mentioned in the above literature), it is necessary to connect the
lower-layer wirings formed by the prior art, with upper-layer
wirings. In that case, as shown in FIG. 8(c), throughholes 110 and
110a are formed on a wiring 106 of large wiring-to-wiring distance
and a wiring 105 of small wiring-to-wiring distance, respectively.
Into the throughholes 110 and 110a are formed metal plugs 111 and
111a, respectively, and the lower-layer wirings and the upper-layer
wirings are electrically connected with the metal plugs.
[0016] In the prior art as mentioned above, an isolation film of
low-dielectric constant is selectively formed in the region of
small wiring-to-wiring distance, of the wiring structure of
semiconductor device. In this prior art, etching back of
low-dielectric constant material 107 is necessary as mentioned with
respect to FIG. 8(b). However, in the etching back, the
etching-back depth of low-dielectric constant material is very
difficult to control. It is also difficult to improve the
uniformity of etching-back depth in a semiconductor wafer.
Therefore, it is difficult to apply the prior art to production of
a semiconductor having a fine wiring structure or using a
semiconductor wafer of large diameter (e.g. diameter of 12
in.).
[0017] In the prior art, a first dielectric layer 103 and a second
dielectric layer 109 are formed on or above both wirings 105 of
small wiring-to-wiring distance and wirings 106 of large
wiring-to-wiring distance. That is, no low-dielectric constant
material 107 is formed on these wirings. Therefore, throughholes
can be formed on these wirings. However, if mask alignment is
deviated form the predetermined position as shown in FIG. 8(c) in
the photolithography employed for throughhole formation, the
low-dielectric constant material 107 is also etched in the region
of wirings 105 of small wiring-to-wiring distance. When the
low-dielectric constant material 107 is made of a polymer having a
relative dielectric constant of 3 or less such as mentioned in the
above-cited literature, the throughhole 110a formed in the region
of wirings 105 of small wiring-to-wiring distance has a very
disadvantageous shape. That is, the throughhole extends even to a
direction perpendicular to the throughhole axial direction and
comes to contain a void, whereby formation of a reliable metal plug
111a is difficult and the resulting semiconductor device has
significantly reduced reliability.
SUMMARY OF THE INVENTION
[0018] The objects of the present invention are to provide a simple
process for stably forming a fine wiring structure of semiconductor
device; a fine multi-layered wiring structure of high performance
and high reliability, of semiconductor device; and a process for
forming such a fine multi-layered wiring structure.
[0019] According to the present invention, there is provided a
semiconductor device comprising:
[0020] a semiconductor substrate having semiconductor elements,
and
[0021] a plurality of wirings formed on the semiconductor substrate
via an isolation film, wherein the wirings are formed in at least
one layer level so that the region in which the wirings are formed
is divided into a wiring region of small wiring-to-wiring distance
and a wiring region of large wiring-to-wiring distance; a first
inter-level isolation film is selectively formed in the wiring
region of small wiring-to-wiring distance and a second inter-level
isolation film is formed in the wiring region of large
wiring-to-wiring distance to cover the wirings; throughholes are
formed only in the second inter-level isolation film; and the
dielectric constant of the first inter-level isolation film is
smaller than the dielectric constant of the second inter-level
isolation film.
[0022] According to the present invention, there is also provided a
semiconductor device comprising:
[0023] a semiconductor substrate having semiconductor elements,
and
[0024] a plurality of wirings formed on the semiconductor substrate
via an isolation film, wherein the wirings are formed in at least
one layer level so that the region in which the wirings are formed
is divided into a wiring region of small wiring-to-wiring distance
and a wiring region of large wiring-to-wiring distance; a first
inter-level isolation film is selectively formed in the wiring
region of small wiring-to-wiring distance, a second inter-level
isolation film is formed in the wiring region of large
wiring-to-wiring distance to cover the wirings; and a third
inter-level isolation film is formed so as to cover the first
inter-level-isolation film and the second inter-level isolation
film; throughholes are formed only in the second inter-level
isolation film and the third inter-level isolation film; and the
dielectric constant of the first inter-level isolation film is
smaller than the dielectric constants of the second inter-level
isolation film and the third inter-level isolation film.
[0025] In each of the above semiconductors, it is preferable that
the isolation film on the substrate is dented at the surface areas
corresponding to the wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region and the
resulting dents are filled with the first inter-level isolation
film.
[0026] In each of the above semiconductors, the first inter-level
isolation film is constituted by an organic film, an organic SOG
film, a polyimide film, a porous inorganic SOG film having a
density smaller than that of silicon oxide film, a porous organic
SOG film, or a porous organic film, and the second inter-level
isolation film is constituted by a silicon oxide film or a silicon
oxynitride film.
[0027] In each of the above semiconductors, when the wirings are
formed in a multi-layered wiring structure, both the lower layer
and the upper layer have the above-mentioned wiring structure.
[0028] According to the present invention, there is also provided a
process for producing a semiconductor device, which comprises:
[0029] a step of forming a plurality of wirings on a semiconductor
substrate via an isolation film so that the region in which the
wirings are formed is divided into a wiring region of small
wiring-to-wiring distance and a wiring region large
wiring-to-wiring distance, and forming thereon a first inter-level
isolation film so as to cover the wirings and then a protective
isolation film in this order,
[0030] a step of selectively removing the first inter-level
isolation film and the protective isolation film present on and in
the wiring region of large wiring-to-wiring distance,
[0031] a step of forming, by deposition, a second inter-level
isolation film on the whole surface of the resulting material and
then subjecting the second inter-level isolation film to chemical
mechanical polishing with the protective isolation film used as an
etching stopper, to obtain a flat surface, and
[0032] a step of forming throughholes only in the second
inter-level isolation film.
[0033] In the above process, the dielectric constant of the first
inter-level isolation film is smaller than the dielectric constant
of the second inter-level isolation film and the protective
isolation film is more resistant to the chemical mechanical
polishing than the second inter-level isolation film.
[0034] According to the present invention, there is also provided a
process for producing a semiconductor device, which comprises:
[0035] a step of forming a plurality of wirings on a semiconductor
substrate via an isolation film so that the region in which the
wirings are formed is divided into a wiring region of small
wiring-to-wiring distance and a wiring region large
wiring-to-wiring distance, and forming thereon a second inter-level
isolation film so as to cover the wirings,
[0036] a step of selectively removing the second inter-level
isolation film present on and in the wiring region of small
wiring-to-wiring distance,
[0037] a step of forming, by deposition, a first inter-level
isolation film on the whole surface of the resulting material, and
then subjecting the first inter-level isolation film to chemical
mechanical polishing with the second inter-level isolation film
used as an etching stopper to obtain a flat surface, and a step of
forming throughholes only in the second inter-level isolation
film.
[0038] In the above process, the dielectric constant of the first
inter-level isolation film is smaller than the dielectric constant
of the second inter-level isolation film and the second inter-level
isolation film is more resistant to the chemical mechanical
polishing than the first inter-level isolation film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] FIG. 1 is a sectional view of a wiring region of
semiconductor device, for explaining the first embodiment of the
present invention.
[0040] FIG. 2 is sectional views showing the major production steps
of the first embodiment of the present invention.
[0041] FIG. 3 is a plan view of a semiconductor device to which the
present invention is applied.
[0042] FIG. 4 is a sectional view of a wiring region of
semiconductor device, for explaining the second embodiment of the
present invention.
[0043] FIG. 5 is sectional views showing the major production steps
of the second embodiment of the present invention.
[0044] FIG. 6 is sectional views showing the major production steps
of the second embodiment of the present invention.
[0045] FIG. 7 is sectional views showing the major production steps
of the conventional semiconductor device, for explaining the prior
art.
[0046] FIG. 8 is sectional views showing the production steps of
the conventional semiconductor device, for explaining the prior
art.
[0047] In FIGS. 1-8;
[0048] 1 is a base inter-level isolation film formed on a
semiconductor substrate;
[0049] 1a is a semiconductor chip;
[0050] 2 and 2a are each a lower-layer wiring;
[0051] 3 is a first inter-level isolation film;
[0052] 4 is a protective isolation film;
[0053] 5 and 5a are each a second inter-level isolation film;
[0054] 6, 16, 110 and 110a are each a throughhole;
[0055] 7, 111 and 111a are each a metal plug;
[0056] 8 and 8a are each an upper-layer wiring;
[0057] 9 is a first inter-level isolation film in upper layer;
[0058] 10 and 10a are each a second inter-level isolation film in
upper layer;
[0059] 11 is a throughhole in upper layer;
[0060] 12 is a metal plug in upper layer;
[0061] 13 is a groove;
[0062] 14 is a first inter-level isolation film;
[0063] 15 is a second inter-level isolation film;
[0064] 17 and 18 are each a third inter-level isolation film;
[0065] 19 and 104 are each a resist mark;
[0066] 101 is a thick isolation film;
[0067] 102 is a metal layer;
[0068] 103 is a first dielectric layer;
[0069] 105 is a wiring in a wiring region of small wiring-to-wiring
distance;
[0070] 106 is a wiring in a wiring region of large wiring-to-wiring
distance;
[0071] 107 is a low-dielectric constant material;
[0072] 108 is a hard oxide mask; and
[0073] 109 is a second dielectric layer.
DETAILED DESCRIPTION OF THE INVENTION
[0074] Embodiments of the present invention are described with
reference to accompanying drawings. FIG. 1 is a sectional view of a
wiring region of semiconductor device, for explaining the first
embodiment of the present invention. FIG. 2 is sectional views
showing the major steps employed in production of such a wiring
region.
[0075] As shown in FIG. 1, a plurality of lower-layer wirings 2 and
2a are formed on a base inter-level isolation film 1 formed on a
semiconductor substrate (e.g. a silicon substrate). The wirings 2
are formed in a wiring region of small wiring-to-wiring distance,
and the wirings 2a are formed in a wiring region of large
wiring-to-wiring distance. In the wiring region of small
wiring-to-wiring distance, the distance between wirings is such
that brings a noticeable increase in capacitance between wirings.
This is usually less than 0.5 .mu.m. On the other hand, in the
wiring region of large wiring-to-wiring distance, the capacitance
between wirings is not noticeably large. Where, the distance
between wirings is usually more than or equal to 0.5 .mu.m.
[0076] A first inter-level isolation film 3 is formed so as to fill
the spacings between the wirings 2. On the first inter-level
isolation film 3 is formed a protective isolation film 4. The base
inter-level isolation film 1 is constituted by an ordinary silicon
oxide film and has a relative dielectric constant of about 4.2.
Meanwhile, the first inter-level isolation film 3 is constituted by
an organic SOG film or the like and its relative dielectric
constant is determined to be smaller than the relative dielectric
constant of the isolation film 1. The protective isolation film 4
is constituted by an inorganic substance and, as will be mentioned
later, functions as an etching stopper for the first inter-level
isolation film 3.
[0077] In the region of wirings 2a having a large wiring-to-wiring
distance is formed a second inter-level isolation film 5 as an
inter-level isolation film. The second inter-level isolation film 5
is constituted by an isolation film of high moisture resistance and
high quality. The film 5 is, for example, a silicon oxide film
formed by chemical vapor deposition (CVD). In the given portions of
the second inter-level isolation film 5 are formed throughholes 6.
In each throughhole 6 is filled a metal plug 7, whereby electrical
connection holds between the metal plug 7 and a wiring 2a.
[0078] No throughhole is formed in the first inter-level isolation
film 3 made of a low-dielectric constant material and the
protective isolation film 4 formed thereon.
[0079] An upper-layer wiring structure is formed in a manner
similar to that used in formation of the lower-layer wiring
structure. That is, on isolation films such as the protective
isolation film 4, the second inter-level isolation film 5, and the
like are formed upper-layer wirings 8a and 8, etc., and an
upper-layer wiring 8 is connected with the metal plug 7. In the
spacings between the upper-layer wirings 8 is filled a first
inter-layer isolation film 9 made of a low-dielectric constant
material and, on the first inter-level isolation film 9 is formed a
protective isolation film 4. In the region of wirings 8a is formed
a second inter-level isolation film 10 as an inter-level isolation
film. The second inter-level isolation film 10, similarly to the
second-inter level isolation film 5, is constituted by an isolation
film of high moisture resistance and high quality. In the given
portions of the second inter-level isolation film 10 are formed
throughholes 11. In each throughhole 11 is filled a metal plug
12.
[0080] In the above formation of an upper-layer wiring strucure,
the first inter-level isolation film 9 is formed on the second
inter-level isolation film 5, and the second inter-level isolation
film 10 is formed on the protective isolation film 4. The above
constitution may be reversed. That is, the first inter-level
isolation film 9 may be formed on the protective isolation film 4,
and the second inter-level isolation film 10 may be formed on the
second inter-level isolation film 5.
[0081] As described above, the feature of the wiring structure
according to the first embodiment lies in that a first inter-level
isolation film (which is a low dielectric constant isolation film)
is formed in each wiring region of small wiring-to-wiring distance,
a second inter-level isolation film of high moisture resistance and
high quality is formed in each wiring region of large
wiring-to-wiring distance and that throughholes are formed only in
each second inter-level isolation film.
[0082] Next, description is made on the key steps employed in
production of the above-mentioned wiring structure, with reference
to FIG. 2. As shown in FIG. 2(a), a base inter-level isolation film
1 made of silicon oxide or the like is formed on a semiconductor
substrate. On the isolation film 1 is deposited a metal by
sputtering, to form a metal film. The metal film is an alloy film
made of aluminum copper (AlCu) or the like and has a thickness of
about 400 nm. The metal film may also be a laminated metal film
made of, for example, Ti, TiN and AlCu.
[0083] Next, the metal film is subjected to fine processing by
photolithography and dry etching to form lower-layer wirings 2 and
2a. The wirings 2 are wirings constituting a wiring region of small
wiring-to-wiring distance, and the wirings 2a are wirings
constituting a wiring region of large wiring-to-wiring
distance.
[0084] On the whole surfaces of the isolation film 1 and the
wirings 2 and 2a is formed a low-dielectric constant film, for
example, by spin-coating, on the whole surfaces, a coating solution
capable of forming an organic SOG film. The coating solution is
filled over the wirings 2 and 2a. Then, a heat treatment is applied
to heat-cure the solution and form an organic SOG film. The organic
SOG film has a relative dielectric constant of 3 or less. The
organic SOG film is subjected to chemical mechanical polishing
(CMP) for levelling, whereby a first inter-level isolation film 3
as shown in FIG. 2(a) is formed. The first inter-level isolation
film 3 is controlled so as to have a thickness of about 600 nm.
[0085] Next, on the first inter-level isolation film 3 is formed a
protective isolation film 4. The protective isolation film 4 is
formed by plasma CVD, is made of silicon nitride, silicon
oxynitride or silicon carbide, and is controlled so as to have a
thickness of about 50 nm.
[0086] Next, as shown in FIG. 2(b), photolithography and dry
etching are applied to remove the protective isolation film 4 and
the first inter-level isolation film 3 so that the portions of the
film 4 and the film 3 both present in the region of wirings 2 are
allowed to remain.
[0087] Next, a second inter-level isolation film 5 is formed by
deposition so as to cover the wirings 2a and the protective
isolation film 4. The second inter-level isolation film 5 is formed
by plasma CVD using bias ECR, is made of silicon oxide, and has a
thickness of about 800 nm.
[0088] Next, the second inter-level isolation film in a FIG. 2(b)
state is levelled by CMP, as shown in FIG. 2(c) In this CMP, the
protective isolation film 4 functions as an etching stopper. That
is, by using an abrasive with which a silicon oxide film is
selectively polished and to which a silicon nitride film or a
silicon oxynitride film is resistant to polishing, the second
inter-level isolation film 5 is polished selectively and the first
inter-level isolation film 3 is protected from polishing owing to
the presence of the protective isolation film 4. Further, the
protective isolation film 4 can significantly improve the film
thickness uniformity of the second inter-level isolation film 5
after polishing.
[0089] Next, throughholes 6 are formed in the given portions of the
second inter-level isolation film 5, and a metal plug 7 is filled
in each throughhole 7. The metal plug 7 is formed, for example, by
formation of a tungsten film by CVD and polishing thereof by
CMP.
[0090] Thus, a lower-layer wiring structure is formed. Thereon is
formed an upper-layer wiring structure as mentioned with respect to
FIG. 1. The process for formation of an upper-layer wiring
structure is similar to the above-mentioned process for formation
of a lower-layer wiring structure and, therefore, is not
mentioned.
[0091] As the first inter-layer isolation film 3, there maybe used
a hydroscopic organic isolation film (e.g. a polyimide film), a
porous inorganic SOG film having a density smaller than that of
silicon oxide film, a porous organic SOG film or the like. Or,
there may be used an inorganic isolation film such as SiOF film,
SiBN film or the like.
[0092] One of the features of the wiring structure of the present
invention lies in that a low-dielectric constant isolation film is
selectively formed in each wiring region of small wiring-to-wiring
distance, an inter-level isolation film of high moisture resistance
and high quality is formed in each wiring region of large
wiring-to-wiring distance and that throughholes are formed only in
each inter-level isolation film of high moisture resistance and
high quality. This feature is explained with reference to FIG. 3.
FIG. 3 is a plan view of a semiconductor device to which the
present invention is applied.
[0093] As shown in FIG. 3, a first inter-level isolation film 14
(which is a low-dielectric constant isolation film) is selectively
formed on the given areas of a semiconductor chip 1a. Thereby, the
parasitic capacitance between adjacent wirings is reduced and the
transfer speed of signal is increased.
[0094] Further, a second inter-level isolation film 15 (which is an
isolation film of high moisture resistance and high quality) is
formed on an area of the semiconductor chip 1a. Throughholes 16 for
connecting a lower wiring layer and an upper wiring layer are
formed in the second inter-level isolation film 15. In each
throughhole, a metal plug is filled.
[0095] In general, a low-dielectric constant isolation film has a
large thermal expansion coefficient, a small strength and high
hydroscopy. The hydroscopy becomes higher as the dielectric
constant becomes smaller.
[0096] Therefore, when throughholes are formed in a low-dielectric
constant isolation film, the electrical resistance of connections
between lower-layer wirings and upper-layer wirings via these
throughholes changes with the lapse of time. That is, the
reliability of wirings decreases largely with the lapse of time.
For example, the electrical resistance comes to increase due to the
presence of moisture and resulting corrosion of wirings
communicating with the throughholes or fluorination of aluminum
metal. Such quality deterioration is more striking when the wiring
structure has more layers. Due to such reduction in reliability of
wiring structure, the dielectric constant of inter-level isolation
film are not able to be lowered beyond a certain limit.
[0097] In contrast, in the above-mentioned embodiment of the
present invention, throughholes are formed only in the second
inter-level isolation film of high moisture resistance and high
quality. Therefore, a multi-layered wiring structure of high
performance and high reliability is made possible.
[0098] Next, description is made on the second embodiment of the
present invention. FIG. 4 is a sectional view of a wiring portion
of semiconductor device, for explaining the second embodiment of
the present invention. FIG. 5 and FIG. 6 are sectional views
showing the major steps employed in production of such a wiring
portion. In FIGS. 4 to 6, members having the same functions as in
the first embodiment are shown by the same symbols.
[0099] As shown in FIG. 4, a plurality of lower-layer wirings 2 and
2a are formed on a base inter-levvel isolation film 1 formed on a
semiconductor substrate In the surface areas of the isolation film
1 present between the wirings 2 are formed grooves 13. The wirings
2 are wirings of a wiring region of small wiring-to-wiring
distance, and the wirings 2a are wirings of a wiring region of
large wiring-to-wiring distance.
[0100] A first inter-level isolation film 3 is formed so as to fill
the gaps between the wirings 2 and the grooves 13. The isolation
film 1 is constituted by an ordinary silicon oxide film. Meanwhile,
the first inter-level isolation film 3 is constituted by an organic
SOG film or the like.
[0101] In the region of the wirings 2a having a large
wiring-to-wiring distance is formed a second inter-level isolation
film 5a as an inter-level isolation film. The second inter-level
isolation film 5a is constituted by an isolation film of high
moisture resistance and high quality which is made of an insulating
material different from that used in the first inter-level
isolation film 3. The isolation film 5a is, for example, a silicon
oxynitride film formed by CVD.
[0102] A third inter-level isolation film 17 is formed so as to
cover the first inter-level isolation film 3 and the second
inter-level isolation film 5a. The third inter-level isolation film
17, similarly to the second inter-level isolation film 5a, is
constituted by an isolation film of high moisture resistance and
high quality.
[0103] In the given portions of the second inter-level isolation
film 5a and the third inter-level isolation film 17 are formed
throughholes 6. In each throughhole 6 is filled a metal plug 7,
whereby electrical connection between plug and lower-layer wiring
2a is achieved.
[0104] Similarly to the case of the first embodiment, no
throughhole is formed in the first inter-level isolation film 3
constituted by a low-dielectric constant isolation film.
[0105] An upper wiring layer is formed in a manner similar to that
used in formation of a lower wiring layer. That is, upper-layer
wirings 8a and 8, etc. are formed on the third inter-level
isolation film 17, where by electrical connection between
upper-layer wiring 8 and metal plug 7 is achieved. In the surface
areas of the isolation film 17 present between the wirings 8 are
formed grooves 13. Between the wirings 8 and in the grooves 13 is
filled a first inter-level isolation film 9 constituted by a
low-dielectric constant isolation film. In the region of the
wirings 8a having a large wiring-to-wiring distance is formed a
second inter-level isolation film 10a as an inter-level isolation
film. A third inter-level isolation film 18 is formed so as to
cover the whole surfaces of isolation films 9 and 10a. The second
inter-level isolation film 10a and the third inter-level isolation
film 18 are each constituted by an isolation film of high moisture
resistance and high quality. In the given portions of the second
inter-level isolation film 10a and the third inter-level isolation
film 18 are formed throughholes 11. In each throughhole 11 is
filled a metal plug 12.
[0106] In the above-mentioned formation of an upper wiring layer,
the first inter-level isolation film 9 is formed on the second
inter-level isolation film 5a, and the second inter-level isolation
film 10a is formed on the first inter-level isolation film 3. The
above constitution may be reversed. That is, the first inter-level
isolation film 9 is formed on the first inter-level isolation film
3, and the second inter-level isolation film 10a is formed on the
second inter-level isolation film 5a.
[0107] As described above, the feature of the wiring structure
according to the second embodiment of the present invention lies in
that grooves of certain depth are formed at the surface areas of
each isolation film present at the bottom of each wiring level,
corresponding to each wiring region of small wiring-to-wiring
distance but not covered by the wirings of the region. A
low-dielectric constant isolation film is formed so as to fill not
only between the wirings of the region but also the grooves. As a
result, the parasitic capacitance between adjacent wirings due to
the fringe effect is greatly reduced. This merit is more striking
in a finer wiring structure.
[0108] The process for producing the above-mentioned wiring
structure is described with reference to FIG. 5 and FIG. 6. As
shown in FIG. 5(a), on a base inter-llevel isolation film 1
constituted by a silicon oxide film are formed lower-layer wirings
2 and 2a, in a manner similar to that mentioned in the first
embodiment. The wirings 2 are wirings of a wiring region of small
wiring-to-wiring distance, and the wirings 2a are wirings of a
wiring region of large wiring-to-wiring distance. The wirings 2 and
2a have a line width of about 0.3 .mu.m and a height of 0.4
.mu.m.
[0109] Next, on the whole surfaces of the isolation film 1, the
wirings 2 and the wirings 2a is formed a second inter-level
isolation film 5a. The second inter-level isolation film 5a is a
silicon oxynitride film formed by plasma CVD, and is levelled by
CMP. On the surface area of the second inter-level isolation film
5a covering the wirings 2a is formed a resist mask 19. As shown in
FIG. 5(b), by using the resist mask 19 as an etching mask, the
second inter-level isolation film 5a in the wiring region of small
wiring-to-wiring distance is subjected to anisotropic etching by
RIE. In this case, even part of the surface of the isolation film 1
is etched by RIE and grooves 13 of the same pattern as the wirings
2 are formed. The depth of each groove is controlled similar to the
line width of wiring 2. Then, the resist mask 19 is removed.
[0110] Next, as shown in FIG. 5(c), on the whole surfaces of the
resulting material is formed a first inter-level isolation film 3.
The first inter-level isolation film 3 is a low-dielectric constant
isolation film constituted by, for example, an organic SOG film
such as mentioned in the first embodiment. The thickness of the
first inter-level isolation film 3 is controlled at about 600
nm.
[0111] Next, the first inter-level isolation film 3 in a FIG. 5(c)
state is subjected to CMP for surface levelling, as shown in FIG.
6(a). In this polishing step, the second inter-level isolation film
5a functions as an etching stopper. That is, by using an abrasive
with which the first inter-level isolation film constituted by an
organic SOG film or the like is selectively polished and to which
the second inter-level isolation film constituted by a silicon
oxynitride film or the like has abrasion resistance, the first
inter-level isolation film 3 is polished selectively.
[0112] Next, as shown in FIG. 6(b), a third inter-level isolation
film 17 is formed on the levelled first inter-level isolation film
3 and the levelled second inter-level isolation film 5a. The third
inter-level isolation film 17 is a silicon oxide film formed by CVD
and has a thickness of about 300 nm. Thus, a lower-layer wiring
structure is formed. As the first inter-level isolation film 3,
there may be used a hydroscopic organic isolation film (e.g. a
polyimide film), a porous inorganic SOG film having a density
smaller than that of silicon oxide film, a porous organic SOG film
or the like. Or, an inorganic isolation film such as SiOF film,
SiBN film or the like may be used. In these cases, a silicon oxide
film may be used as the second inter-level isolation film 5a.
[0113] Next, as shown in FIG. 6(c), throughholes 6 are formed in
the given portions of the second inter-level isolation film 5a and
the third inter-level isolation film 17, both present in the wiring
region of large wiring-to-wiring distance. In each throughhole 6 is
filled a metal plug 7, whereby electrical connection between metal
plug 7 and wiring 2a is achieved.
[0114] Next, an upper-layer wiring structure as mentioned with
respect to FIG. 4 is formed. The process for formation of an
upper-layer wiring structure is performed in the similar manner to
the above-described process for formation of a lower wiring
layer.
[0115] In the second embodiment, each first inter-level isolation
film formed in each wiring region of small wiring-to-wiring
distance is filled even in the dents formed in each isolation film
present beneath the wirings of the region. As a result, the
parasitic capacitance generated between the bottom ends of adjacent
wirings is reduced.
[0116] In the present invention, as the low-dielectric constant
isolation film, there can be used, in addition to those films
mentioned above in the embodiments, films of HSQ (hydrogen
silsesquioxane), polyaryl ether, fluorinated polyaryl ether,
inorganic polysilazane, organic polysilazane, BCB
(benzocyclobutene), MSQ (methyl silsesquioxane),
fluorinatedpolyimide, plasma CF polymer, plasma CH polymer, Teflon
AF (trademark), Parylene N (trade mark), AF-4 (polyparaxylylene),
Polynaphthalene N, etc.
[0117] As described above, in each wiring layer level of the
semiconductor of the present invention, an inter-level isolation
film of low dielectric constant is formed in the region of small
wiring-to-wiring distance and an inter-level isolation film of high
moisture resistance and high quality is formed in the region of
large wiring-to-wiring distance; and throughholes for connecting
lower-layer wirings and upper-layer wirings are formed only in the
inter-level isolation film of high moisture resistance and high
quality.
[0118] Further, in polishing and levelling of the first inter-level
isolation film by CMP, the second inter-level isolation film is
used as an etching stopper.
[0119] As a result, the reliability of connection between
lower-layer wirings and upper-layer wirings is greatly improved and
a fine multi-layered wiring structure is made possible. Further,
the film thickness uniformity of the first inter-level isolation 3
on a semiconductor chip is greatly improved.
[0120] Further in the present invention, grooves of certain depth
are formed at the surface areas of each isolation film present at
the bottom of each wiring layer, corresponding to each wiring
region of small wiring-to-wiring distance but not covered by the
wirings of the region, and a low-dielectric constant film is formed
so as to fill not only the spacings between the wirings of said
region but also the grooves.
[0121] As a result, the parasitic capacitance between adjacent
wirings due to the fringe effect is greatly reduced. This merit is
more striking in a finer wiring structure.
[0122] Thus, there is easily obtained a fine multi-layered wiring
structure of high performance and high reliability, required in a
fine and multifunctional semiconductor device.
* * * * *